From c97a47f54e379198ceee88a1193a319f40420ec0 Mon Sep 17 00:00:00 2001 From: Kees Jongenburger Date: Mon, 24 Feb 2014 09:40:30 +0100 Subject: [PATCH] arm-refactor:indent the omap bsp code. Indent the omap bsd code using indent with the following settings in indent.pro. -bap -br -ce -ci4 -cli0 -d0 -di0 -i8 -ip4 -l79 -nbc -ncdb -ndj -nfc1 -nlp -npcs -psl -sc -sob -fca -l79 -lc79 Change-Id: I09e7de9ad4b33f78bff96e3de4470f1c5ba854ce --- kernel/arch/earm/bsp/ti/omap_init.c | 4 +- kernel/arch/earm/bsp/ti/omap_intr.c | 43 ++++--- kernel/arch/earm/bsp/ti/omap_padconf.c | 42 +++--- kernel/arch/earm/bsp/ti/omap_reset.c | 37 +++--- kernel/arch/earm/bsp/ti/omap_rtc.c | 5 +- kernel/arch/earm/bsp/ti/omap_serial.c | 23 ++-- kernel/arch/earm/bsp/ti/omap_timer.c | 171 ++++++++++++++----------- 7 files changed, 188 insertions(+), 137 deletions(-) diff --git a/kernel/arch/earm/bsp/ti/omap_init.c b/kernel/arch/earm/bsp/ti/omap_init.c index 6f30d30bb..1d54bfeca 100644 --- a/kernel/arch/earm/bsp/ti/omap_init.c +++ b/kernel/arch/earm/bsp/ti/omap_init.c @@ -4,7 +4,9 @@ #include "omap_rtc.h" #include "bsp_reset.h" -void bsp_init(){ +void +bsp_init() +{ /* map memory for padconf */ bsp_padconf_init(); diff --git a/kernel/arch/earm/bsp/ti/omap_intr.c b/kernel/arch/earm/bsp/ti/omap_intr.c index 836b596a0..862d43442 100644 --- a/kernel/arch/earm/bsp/ti/omap_intr.c +++ b/kernel/arch/earm/bsp/ti/omap_intr.c @@ -12,47 +12,60 @@ #include "hw_intr.h" #include "omap_intr_registers.h" -static struct omap_intr { +static struct omap_intr +{ vir_bytes base; int size; } omap_intr; - static kern_phys_map intr_phys_map; -int intr_init(const int auto_eoi) +int +intr_init(const int auto_eoi) { if (BOARD_IS_BBXM(machine.board_id)) { omap_intr.base = OMAP3_DM37XX_INTR_BASE; } else if (BOARD_IS_BB(machine.board_id)) { omap_intr.base = OMAP3_AM335X_INTR_BASE; } else { - panic("Can not do the interrupt setup. machine (0x%08x) is unknown\n",machine.board_id); + panic + ("Can not do the interrupt setup. machine (0x%08x) is unknown\n", + machine.board_id); }; - omap_intr.size = 0x1000 ; /* 4K */ + omap_intr.size = 0x1000; /* 4K */ - kern_phys_map_ptr(omap_intr.base,omap_intr.size, - &intr_phys_map, (vir_bytes) &omap_intr.base); + kern_phys_map_ptr(omap_intr.base, omap_intr.size, + &intr_phys_map, (vir_bytes) & omap_intr.base); return 0; } -void bsp_irq_handle(void) { +void +bsp_irq_handle(void) +{ /* Function called from assembly to handle interrupts */ /* get irq */ - int irq = mmio_read(omap_intr.base + OMAP3_INTCPS_SIR_IRQ) & OMAP3_INTR_ACTIVEIRQ_MASK; + int irq = + mmio_read(omap_intr.base + + OMAP3_INTCPS_SIR_IRQ) & OMAP3_INTR_ACTIVEIRQ_MASK; /* handle irq */ irq_handle(irq); - /* re-enable. this should not trigger interrupts due to current cpsr state */ - mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL,OMAP3_INTR_NEWIRQAGR); + /* re-enable. this should not trigger interrupts due to current cpsr + * state */ + mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL, + OMAP3_INTR_NEWIRQAGR); } -void bsp_irq_unmask(int irq) +void +bsp_irq_unmask(int irq) { - mmio_write(OMAP3_INTR_MIR_CLEAR(omap_intr.base, irq >> 5), 1 << (irq & 0x1f)); + mmio_write(OMAP3_INTR_MIR_CLEAR(omap_intr.base, irq >> 5), + 1 << (irq & 0x1f)); } -void bsp_irq_mask(const int irq) +void +bsp_irq_mask(const int irq) { - mmio_write(OMAP3_INTR_MIR_SET(omap_intr.base, irq >> 5), 1 << (irq & 0x1f)); + mmio_write(OMAP3_INTR_MIR_SET(omap_intr.base, irq >> 5), + 1 << (irq & 0x1f)); } diff --git a/kernel/arch/earm/bsp/ti/omap_padconf.c b/kernel/arch/earm/bsp/ti/omap_padconf.c index 3a5fa4f5f..1a803fdb0 100644 --- a/kernel/arch/earm/bsp/ti/omap_padconf.c +++ b/kernel/arch/earm/bsp/ti/omap_padconf.c @@ -23,28 +23,26 @@ struct omap_padconf unsigned int board_filter_mask; }; - static struct omap_padconf omap_padconfs[] = { - { - .base = PADCONF_DM37XX_REGISTERS_BASE, - .offset = PADCONF_DM37XX_REGISTERS_OFFSET, - .size = PADCONF_DM37XX_REGISTERS_SIZE, - .board_filter_value = BOARD_FILTER_BBXM_VALUE, - .board_filter_mask = BOARD_FILTER_BBXM_MASK, - }, - { - .base = PADCONF_AM335X_REGISTERS_BASE, - .offset = PADCONF_AM335X_REGISTERS_OFFSET, - .size = PADCONF_AM335X_REGISTERS_SIZE, - .board_filter_value = BOARD_FILTER_BB_VALUE, - .board_filter_mask = BOARD_FILTER_BB_MASK, - }, + { + .base = PADCONF_DM37XX_REGISTERS_BASE, + .offset = PADCONF_DM37XX_REGISTERS_OFFSET, + .size = PADCONF_DM37XX_REGISTERS_SIZE, + .board_filter_value = BOARD_FILTER_BBXM_VALUE, + .board_filter_mask = BOARD_FILTER_BBXM_MASK, + }, + { + .base = PADCONF_AM335X_REGISTERS_BASE, + .offset = PADCONF_AM335X_REGISTERS_OFFSET, + .size = PADCONF_AM335X_REGISTERS_SIZE, + .board_filter_value = BOARD_FILTER_BB_VALUE, + .board_filter_mask = BOARD_FILTER_BB_MASK, + }, }; /* initialized in init */ static struct omap_padconf *omap_padconf; - static kern_phys_map padconf_phys_map; int @@ -55,7 +53,8 @@ bsp_padconf_set(u32_t padconf, u32_t mask, u32_t value) return EINVAL; /* outside of valid range */ } - set32(padconf + omap_padconf->base + omap_padconf->offset, mask, value); + set32(padconf + omap_padconf->base + omap_padconf->offset, mask, + value); return OK; } @@ -66,16 +65,17 @@ bsp_padconf_init(void) int x; omap_padconf = NULL; /* find the correct padconf */ - for (x =0 ; x < sizeof(omap_padconfs)/sizeof(omap_padconfs[0]) ; x++) { - if ( (omap_padconfs[x].board_filter_mask & machine.board_id) == omap_padconfs[x].board_filter_value) { + for (x = 0; x < sizeof(omap_padconfs) / sizeof(omap_padconfs[0]); x++) { + if ((omap_padconfs[x].board_filter_mask & machine.board_id) == + omap_padconfs[x].board_filter_value) { omap_padconf = &omap_padconfs[x]; break; } } assert(omap_padconf); - + kern_phys_map_ptr(omap_padconf->base, omap_padconf->size, - &padconf_phys_map, (vir_bytes) &omap_padconf->base); + &padconf_phys_map, (vir_bytes) & omap_padconf->base); return; } diff --git a/kernel/arch/earm/bsp/ti/omap_reset.c b/kernel/arch/earm/bsp/ti/omap_reset.c index d85b81a52..c0c157dca 100644 --- a/kernel/arch/earm/bsp/ti/omap_reset.c +++ b/kernel/arch/earm/bsp/ti/omap_reset.c @@ -19,7 +19,7 @@ #define AM335X_PRM_DEVICE_OFFSET 0xf00 #define AM335X_PRM_RSTCTRL_REG 0x00 -#define AM335X_RST_GLOBAL_WARM_SW_BIT 0 +#define AM335X_RST_GLOBAL_WARM_SW_BIT 0 #define DM37XX_CM_BASE 0x48307000 #define DM37XX_CM_SIZE 0x1000 @@ -39,29 +39,33 @@ static kern_phys_map reset_phys_map; void bsp_reset_init(void) { - if(BOARD_IS_BBXM(machine.board_id)) { + if (BOARD_IS_BBXM(machine.board_id)) { omap_reset.base = DM37XX_CM_BASE; omap_reset.size = DM37XX_CM_SIZE; - } else if(BOARD_IS_BB(machine.board_id)) { + } else if (BOARD_IS_BB(machine.board_id)) { omap_reset.base = AM335X_CM_BASE; omap_reset.size = AM335X_CM_SIZE; } kern_phys_map_ptr(omap_reset.base, omap_reset.size, &reset_phys_map, - (vir_bytes) &omap_reset.base); + (vir_bytes) & omap_reset.base); } void bsp_reset(void) { - if(BOARD_IS_BBXM(machine.board_id)) { - mmio_set((omap_reset.base + DM37XX_PRM_RSTCTRL_REG), (1 << DM37XX_RST_DPLL3_BIT)); - } else if(BOARD_IS_BB(machine.board_id)) { - mmio_set((omap_reset.base + AM335X_PRM_DEVICE_OFFSET + AM335X_PRM_RSTCTRL_REG), (1 << AM335X_RST_GLOBAL_WARM_SW_BIT)); + if (BOARD_IS_BBXM(machine.board_id)) { + mmio_set((omap_reset.base + DM37XX_PRM_RSTCTRL_REG), + (1 << DM37XX_RST_DPLL3_BIT)); + } else if (BOARD_IS_BB(machine.board_id)) { + mmio_set((omap_reset.base + AM335X_PRM_DEVICE_OFFSET + + AM335X_PRM_RSTCTRL_REG), + (1 << AM335X_RST_GLOBAL_WARM_SW_BIT)); } } -void bsp_poweroff(void) +void +bsp_poweroff(void) { /* @@ -71,12 +75,13 @@ void bsp_poweroff(void) * The only way to pull the pin low is via ALARM2 (see TRM 20.3.3.8). * At this point PM should have already signaled readclock to set the alarm. */ - if (BOARD_IS_BB(machine.board_id)) { - /* rtc was frozen to prevent premature power-off, unfreeze it now */ - omap3_rtc_run(); + if (BOARD_IS_BB(machine.board_id)) { + /* rtc was frozen to prevent premature power-off, unfreeze it + * now */ + omap3_rtc_run(); - /* wait for the alarm to go off and PMIC to disable power to SoC */ - while (1); - } + /* wait for the alarm to go off and PMIC to disable power to + * SoC */ + while (1); + } } - diff --git a/kernel/arch/earm/bsp/ti/omap_rtc.c b/kernel/arch/earm/bsp/ti/omap_rtc.c index ff86b9d3a..3911cb1f8 100644 --- a/kernel/arch/earm/bsp/ti/omap_rtc.c +++ b/kernel/arch/earm/bsp/ti/omap_rtc.c @@ -42,7 +42,7 @@ omap3_rtc_init(void) { if (BOARD_IS_BB(machine.board_id)) { kern_phys_map_ptr(omap_rtc.base, omap_rtc.size, &rtc_phys_map, - (vir_bytes) &omap_rtc.base); + (vir_bytes) & omap_rtc.base); } } @@ -51,6 +51,7 @@ omap3_rtc_run(void) { if (BOARD_IS_BB(machine.board_id)) { /* Setting the stop bit starts the RTC running */ - mmio_set((omap_rtc.base + RTC_CTRL_REG), (1 << RTC_CTRL_RTC_STOP_BIT)); + mmio_set((omap_rtc.base + RTC_CTRL_REG), + (1 << RTC_CTRL_RTC_STOP_BIT)); } } diff --git a/kernel/arch/earm/bsp/ti/omap_serial.c b/kernel/arch/earm/bsp/ti/omap_serial.c index 8c1c56233..864709002 100644 --- a/kernel/arch/earm/bsp/ti/omap_serial.c +++ b/kernel/arch/earm/bsp/ti/omap_serial.c @@ -13,8 +13,8 @@ #include "omap_serial.h" - -struct omap_serial { +struct omap_serial +{ vir_bytes base; vir_bytes size; }; @@ -42,28 +42,30 @@ static kern_phys_map serial_phys_map; * The serial driver also gets used in the "pre_init" stage before the kernel is loaded * in high memory so keep in mind there are two copies of this code in the kernel. */ -void bsp_ser_init() +void +bsp_ser_init() { - if(BOARD_IS_BBXM(machine.board_id)) { + if (BOARD_IS_BBXM(machine.board_id)) { omap_serial.base = OMAP3_DM37XX_DEBUG_UART_BASE; } else if (BOARD_IS_BB(machine.board_id)) { omap_serial.base = OMAP3_AM335X_DEBUG_UART_BASE; } - omap_serial.size = 0x1000 ; /* 4k */ + omap_serial.size = 0x1000; /* 4k */ - kern_phys_map_ptr(omap_serial.base,omap_serial.size, - &serial_phys_map, (vir_bytes) &omap_serial.base); + kern_phys_map_ptr(omap_serial.base, omap_serial.size, + &serial_phys_map, (vir_bytes) & omap_serial.base); assert(omap_serial.base); } -void bsp_ser_putc(char c) +void +bsp_ser_putc(char c) { int i; assert(omap_serial.base); /* Wait until FIFO's empty */ for (i = 0; i < 100000; i++) { - if (mmio_read(omap_serial.base + OMAP3_LSR) & OMAP3_LSR_THRE) { + if (mmio_read(omap_serial.base + OMAP3_LSR) & OMAP3_LSR_THRE) { break; } } @@ -73,7 +75,8 @@ void bsp_ser_putc(char c) /* And wait again until FIFO's empty to prevent TTY from overwriting */ for (i = 0; i < 100000; i++) { - if (mmio_read(omap_serial.base + OMAP3_LSR) & (OMAP3_LSR_THRE | OMAP3_LSR_TEMT)) { + if (mmio_read(omap_serial.base + + OMAP3_LSR) & (OMAP3_LSR_THRE | OMAP3_LSR_TEMT)) { break; } } diff --git a/kernel/arch/earm/bsp/ti/omap_timer.c b/kernel/arch/earm/bsp/ti/omap_timer.c index c92d2ac4a..db570c067 100644 --- a/kernel/arch/earm/bsp/ti/omap_timer.c +++ b/kernel/arch/earm/bsp/ti/omap_timer.c @@ -20,13 +20,15 @@ static u64_t high_frc; struct omap_timer_registers; -struct omap_timer { +struct omap_timer +{ vir_bytes base; int irq_nr; struct omap_timer_registers *regs; }; -struct omap_timer_registers { +struct omap_timer_registers +{ vir_bytes TIDR; vir_bytes TIOCP_CFG; vir_bytes TISTAT; @@ -47,7 +49,7 @@ struct omap_timer_registers { vir_bytes TCVR; vir_bytes TOCR; vir_bytes TOWR; - + }; static struct omap_timer_registers regs_v1 = { @@ -91,11 +93,11 @@ static struct omap_timer_registers regs_v2 = { .TCAR1 = AM335X_TIMER_TCAR1, .TSICR = AM335X_TIMER_TSICR, .TCAR2 = AM335X_TIMER_TCAR2, - .TPIR = -1 , /* UNDEF */ - .TNIR = -1 , /* UNDEF */ - .TCVR = -1 , /* UNDEF */ - .TOCR = -1 , /* UNDEF */ - .TOWR = -1 /* UNDEF */ + .TPIR = -1, /* UNDEF */ + .TNIR = -1, /* UNDEF */ + .TCVR = -1, /* UNDEF */ + .TOCR = -1, /* UNDEF */ + .TOWR = -1 /* UNDEF */ }; static struct omap_timer dm37xx_timer = { @@ -110,12 +112,12 @@ static struct omap_timer dm37xx_fr_timer = { .irq_nr = OMAP3_GPT10_IRQ, .regs = ®s_v1 }; + /* normal timer */ static struct omap_timer am335x_timer = { .base = AM335X_DMTIMER1_1MS_BASE, .irq_nr = AM335X_INT_TINT1_1MS, .regs = ®s_v1 - }; /* free running timer */ @@ -128,10 +130,10 @@ static struct omap_timer am335x_fr_timer = { static struct omap_timer *timer; static struct omap_timer *fr_timer; - static int done = 0; -int bsp_register_timer_handler(const irq_handler_t handler) +int +bsp_register_timer_handler(const irq_handler_t handler) { /* Initialize the CLOCK's interrupt hook. */ omap3_timer_hook.proc_nr_e = NONE; @@ -144,52 +146,63 @@ int bsp_register_timer_handler(const irq_handler_t handler) return 0; } - /* meta data for remapping */ static kern_phys_map timer_phys_map; static kern_phys_map fr_timer_phys_map; -void omap3_frclock_init(void) +void +omap3_frclock_init(void) { - u32_t tisr; + u32_t tisr; - /* enable the clock */ - if(BOARD_IS_BBXM(machine.board_id)) { + /* enable the clock */ + if (BOARD_IS_BBXM(machine.board_id)) { fr_timer = &dm37xx_fr_timer; - kern_phys_map_ptr(fr_timer->base,ARM_PAGE_SIZE, &fr_timer_phys_map, (vir_bytes) &fr_timer->base); + kern_phys_map_ptr(fr_timer->base, ARM_PAGE_SIZE, + &fr_timer_phys_map, (vir_bytes) & fr_timer->base); /* Stop timer */ - mmio_clear(fr_timer->base + fr_timer->regs->TCLR, OMAP3_TCLR_ST); + mmio_clear(fr_timer->base + fr_timer->regs->TCLR, + OMAP3_TCLR_ST); /* Use functional clock source for GPTIMER10 */ mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10); - /* Scale timer down to 13/8 = 1.625 Mhz to roughly get microsecond ticks */ - /* The scale is computed as 2^(PTV+1). So if PTV == 2, we get 2^3 = 8. - */ - mmio_set(fr_timer->base + fr_timer->regs->TCLR, (2 << OMAP3_TCLR_PTV)); - } else if(BOARD_IS_BB(machine.board_id)) { + /* Scale timer down to 13/8 = 1.625 Mhz to roughly get + * microsecond ticks */ + /* The scale is computed as 2^(PTV+1). So if PTV == 2, we get + * 2^3 = 8. */ + mmio_set(fr_timer->base + fr_timer->regs->TCLR, + (2 << OMAP3_TCLR_PTV)); + } else if (BOARD_IS_BB(machine.board_id)) { fr_timer = &am335x_fr_timer; - kern_phys_map_ptr(fr_timer->base,ARM_PAGE_SIZE, &fr_timer_phys_map, (vir_bytes) &fr_timer->base); + kern_phys_map_ptr(fr_timer->base, ARM_PAGE_SIZE, + &fr_timer_phys_map, (vir_bytes) & fr_timer->base); /* Disable the module and wait for the module to be disabled */ - set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED); - while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE); + set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK, + CM_MODULEMODE_DISABLED); + while ((mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) + != CM_CLKCTRL_IDLEST_DISABLE); - set32(CLKSEL_TIMER7_CLK,CLKSEL_TIMER7_CLK_SEL_MASK, CLKSEL_TIMER7_CLK_SEL_SEL2); - while( (read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK) != CLKSEL_TIMER7_CLK_SEL_SEL2); + set32(CLKSEL_TIMER7_CLK, CLKSEL_TIMER7_CLK_SEL_MASK, + CLKSEL_TIMER7_CLK_SEL_SEL2); + while ((read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK) + != CLKSEL_TIMER7_CLK_SEL_SEL2); /* enable the module and wait for the module to be ready */ - set32(CM_PER_TIMER7_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE); - while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC); + set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK, + CM_MODULEMODE_ENABLE); + while ((mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) + != CM_CLKCTRL_IDLEST_FUNC); /* Stop timer */ - mmio_clear(fr_timer->base + fr_timer->regs->TCLR, OMAP3_TCLR_ST); + mmio_clear(fr_timer->base + fr_timer->regs->TCLR, + OMAP3_TCLR_ST); /* 24Mhz / 16 = 1.5 Mhz */ - mmio_set(fr_timer->base + fr_timer->regs->TCLR, (3 << OMAP3_TCLR_PTV)); - } - - + mmio_set(fr_timer->base + fr_timer->regs->TCLR, + (3 << OMAP3_TCLR_PTV)); + } /* Start and auto-reload at 0 */ mmio_write(fr_timer->base + fr_timer->regs->TLDR, 0x0); @@ -197,88 +210,100 @@ void omap3_frclock_init(void) /* Set up overflow interrupt */ tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG | - OMAP3_TISR_TCAR_IT_FLAG; + OMAP3_TISR_TCAR_IT_FLAG; /* Clear interrupt status */ - mmio_write(fr_timer->base + fr_timer->regs->TISR, tisr); - mmio_write(fr_timer->base + fr_timer->regs->TIER, OMAP3_TIER_OVF_IT_ENA); + mmio_write(fr_timer->base + fr_timer->regs->TISR, tisr); + mmio_write(fr_timer->base + fr_timer->regs->TIER, + OMAP3_TIER_OVF_IT_ENA); /* Start timer */ mmio_set(fr_timer->base + fr_timer->regs->TCLR, - OMAP3_TCLR_OVF_TRG|OMAP3_TCLR_AR|OMAP3_TCLR_ST|OMAP3_TCLR_PRE); + OMAP3_TCLR_OVF_TRG | OMAP3_TCLR_AR | OMAP3_TCLR_ST | + OMAP3_TCLR_PRE); done = 1; } -void omap3_frclock_stop() +void +omap3_frclock_stop() { mmio_clear(fr_timer->base + fr_timer->regs->TCLR, OMAP3_TCLR_ST); } - -void bsp_timer_init(unsigned freq) +void +bsp_timer_init(unsigned freq) { /* we only support 1ms resolution */ u32_t tisr; - if(BOARD_IS_BBXM(machine.board_id)) { + if (BOARD_IS_BBXM(machine.board_id)) { timer = &dm37xx_timer; - kern_phys_map_ptr(timer->base,ARM_PAGE_SIZE, &timer_phys_map, (vir_bytes) &timer->base); + kern_phys_map_ptr(timer->base, ARM_PAGE_SIZE, &timer_phys_map, + (vir_bytes) & timer->base); /* Stop timer */ mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST); /* Use 32 KHz clock source for GPTIMER1 */ mmio_clear(OMAP3_CM_CLKSEL_WKUP, OMAP3_CLKSEL_GPT1); - } else if(BOARD_IS_BB(machine.board_id)) { + } else if (BOARD_IS_BB(machine.board_id)) { timer = &am335x_timer; - kern_phys_map_ptr(timer->base,ARM_PAGE_SIZE, &timer_phys_map, (vir_bytes) &timer->base); + kern_phys_map_ptr(timer->base, ARM_PAGE_SIZE, &timer_phys_map, + (vir_bytes) & timer->base); /* disable the module and wait for the module to be disabled */ - set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED); - while( (mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE); - - - set32(CLKSEL_TIMER1MS_CLK,CLKSEL_TIMER1MS_CLK_SEL_MASK, CLKSEL_TIMER1MS_CLK_SEL_SEL2); - while( (read32(CLKSEL_TIMER1MS_CLK) & CLKSEL_TIMER1MS_CLK_SEL_MASK) != CLKSEL_TIMER1MS_CLK_SEL_SEL2); + set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK, + CM_MODULEMODE_DISABLED); + while ((mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) + != CM_CLKCTRL_IDLEST_DISABLE); + set32(CLKSEL_TIMER1MS_CLK, CLKSEL_TIMER1MS_CLK_SEL_MASK, + CLKSEL_TIMER1MS_CLK_SEL_SEL2); + while ((read32(CLKSEL_TIMER1MS_CLK) & + CLKSEL_TIMER1MS_CLK_SEL_MASK) != + CLKSEL_TIMER1MS_CLK_SEL_SEL2); /* enable the module and wait for the module to be ready */ - set32(CM_WKUP_TIMER1_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE); - while( (mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC); + set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK, + CM_MODULEMODE_ENABLE); + while ((mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) + != CM_CLKCTRL_IDLEST_FUNC); /* Stop timer */ mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST); } - /* Use 1-ms tick mode for GPTIMER1 TRM 16.2.4.2.1 */ mmio_write(timer->base + timer->regs->TPIR, 232000); mmio_write(timer->base + timer->regs->TNIR, -768000); - mmio_write(timer->base + timer->regs->TLDR, 0xffffffff - (32768 / freq) +1); - mmio_write(timer->base + timer->regs->TCRR, 0xffffffff - (32768 / freq) +1); - + mmio_write(timer->base + timer->regs->TLDR, + 0xffffffff - (32768 / freq) + 1); + mmio_write(timer->base + timer->regs->TCRR, + 0xffffffff - (32768 / freq) + 1); /* Set up overflow interrupt */ tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG | OMAP3_TISR_TCAR_IT_FLAG; /* Clear interrupt status */ - mmio_write(timer->base + timer->regs->TISR, tisr); + mmio_write(timer->base + timer->regs->TISR, tisr); mmio_write(timer->base + timer->regs->TIER, OMAP3_TIER_OVF_IT_ENA); /* Start timer */ mmio_set(timer->base + timer->regs->TCLR, - OMAP3_TCLR_OVF_TRG|OMAP3_TCLR_AR|OMAP3_TCLR_ST); + OMAP3_TCLR_OVF_TRG | OMAP3_TCLR_AR | OMAP3_TCLR_ST); /* also initilize the free runnning timer */ omap3_frclock_init(); } -void bsp_timer_stop() +void +bsp_timer_stop() { mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST); } -static u32_t read_frc(void) +static u32_t +read_frc(void) { if (done == 0) { return 0; } - return mmio_read(fr_timer->base + fr_timer->regs->TCRR); + return mmio_read(fr_timer->base + fr_timer->regs->TCRR); } /* @@ -295,26 +320,27 @@ static u32_t read_frc(void) * compose the 64 bits time based on the current timer value * and high_frc. */ -static void frc_overflow_check(u32_t cur_frc) +static void +frc_overflow_check(u32_t cur_frc) { static int prev_frc_valid; static u32_t prev_frc; - if(prev_frc_valid && prev_frc > cur_frc) { + if (prev_frc_valid && prev_frc > cur_frc) { high_frc++; } prev_frc = cur_frc; prev_frc_valid = 1; } -void bsp_timer_int_handler() +void +bsp_timer_int_handler() { /* Clear all interrupts */ - u32_t tisr,now; - + u32_t tisr, now; - /* when the kernel itself is running interrupts are disabled. - * We should therefore also read the overflow counter to detect - * this as to not miss events. */ + /* when the kernel itself is running interrupts are disabled. We + * should therefore also read the overflow counter to detect this as + * to not miss events. */ tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG | OMAP3_TISR_TCAR_IT_FLAG; mmio_write(timer->base + timer->regs->TISR, tisr); @@ -324,7 +350,8 @@ void bsp_timer_int_handler() } /* Use the free running clock as TSC */ -void read_tsc_64(u64_t *t) +void +read_tsc_64(u64_t * t) { u32_t now; now = read_frc(); -- 2.44.0