From 2478cde442d8d229c1b05d01be657ed01bb610da Mon Sep 17 00:00:00 2001 From: Philip Homburg Date: Mon, 6 Mar 2006 15:19:51 +0000 Subject: [PATCH] Print PCI capability types. --- drivers/pci/pci.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/ibm/pci.h | 7 ++++++- 2 files changed, 49 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 0effc1d5b..00a96b4f8 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -144,6 +144,7 @@ FORWARD _PROTOTYPE( void pcii_wreg32, (int busind, int devind, int port, u32_t value) ); FORWARD _PROTOTYPE( u16_t pcii_rsts, (int busind) ); FORWARD _PROTOTYPE( void pcii_wsts, (int busind, U16_t value) ); +FORWARD _PROTOTYPE( void print_capabilities, (int devind) ); /*===========================================================================* * helper functions for I/O * @@ -798,6 +799,9 @@ printf("probe_bus(%d)\n", busind); break; } + if (debug) + print_capabilities(devind); + if (nr_pcidev >= NR_PCIDEV) panic("PCI","too many PCI devices", nr_pcidev); devind= nr_pcidev; @@ -2209,6 +2213,45 @@ u16_t value; #endif } + +/*===========================================================================* + * print_capabilities * + *===========================================================================*/ +PRIVATE void print_capabilities(devind) +int devind; +{ + u8_t status, capptr, type, next; + char *str; + + /* Check capabilities bit in the device status register */ + status= pci_attr_r16(devind, PCI_SR); + if (!(status & PSR_CAPPTR)) + return; + + capptr= (pci_attr_r8(devind, PCI_CAPPTR) & PCI_CP_MASK); + while (capptr != 0) + { + type = pci_attr_r8(devind, capptr+CAP_TYPE); + next= (pci_attr_r8(devind, capptr+CAP_NEXT) & PCI_CP_MASK); + switch(type) + { + case 1: str= "PCI Power Management"; break; + case 2: str= "AGP"; break; + case 3: str= "Vital Product Data"; break; + case 4: str= "Slot Identification"; break; + case 5: str= "Message Signaled Interrupts"; break; + case 6: str= "CompactPCI Hot Swap"; break; + case 8: str= "AMD HyperTransport"; break; + case 0xf: str= "AMD I/O MMU"; break; + defuault: str= "(unknown type)"; break; + } + + printf(" @0x%x: capability type 0x%x: %s\n", + capptr, type, str); + capptr= next; + } +} + /* * $PchId: pci.c,v 1.7 2003/08/07 09:06:51 philip Exp $ */ diff --git a/include/ibm/pci.h b/include/ibm/pci.h index f14ea253b..3d4a88dc2 100644 --- a/include/ibm/pci.h +++ b/include/ibm/pci.h @@ -14,6 +14,7 @@ Created: Jan 2000 by Philip Homburg #define PSR_SSE 0x4000 /* Signaled System Error */ #define PSR_RMAS 0x2000 /* Received Master Abort Status */ #define PSR_RTAS 0x1000 /* Received Target Abort Status */ +#define PSR_CAPPTR 0x0010 /* Capabilities list */ #define PCI_REV 0x08 /* Revision ID */ #define PCI_PIFR 0x09 /* Prog. Interface Register */ #define PCI_SCR 0x0A /* Sub-Class Register */ @@ -41,8 +42,9 @@ Created: Jan 2000 by Philip Homburg #define PCI_SUBDID 0x2E /* Subsystem Device ID */ #define PCI_EXPROM 0x30 /* Expansion ROM Base Address */ #define PCI_CAPPTR 0x34 /* Capabilities Pointer */ +#define PCI_CP_MASK 0xfc /* Lower 2 bits should be ignored */ #define PCI_ILR 0x3C /* Interrupt Line Register */ -#define PCI_ILR_UNKNOWN 0xFF /* IRQ is unassigned or unknown */ +#define PCI_ILR_UNKNOWN 0xFF /* IRQ is unassigned or unknown */ #define PCI_IPR 0x3D /* Interrupt Pin Register */ #define PCI_MINGNT 0x3E /* Min Grant */ #define PCI_MAXLAT 0x3F /* Max Latency */ @@ -102,6 +104,9 @@ Created: Jan 2000 by Philip Homburg #define CBB_BC_INTEXCA 0x80 /* Interrupt are routed to ExCAs */ #define CBB_BC_CRST 0x40 /* Assert reset line */ +#define CAP_TYPE 0x00 /* Type field in capability */ +#define CAP_NEXT 0x01 /* Next field in capability */ + /* Device type values as ([PCI_BCR] << 16) | ([PCI_SCR] << 8) | [PCI_PIFR] */ #define PCI_T3_PCI2PCI 0x060400 /* PCI-to-PCI Bridge device */ #define PCI_T3_PCI2PCI_SUBTR 0x060401 /* Subtr. PCI-to-PCI Bridge */ -- 2.44.0