From d60d07f0459588cc6f421e30d37aadb6816d3ffc Mon Sep 17 00:00:00 2001 From: Kees Jongenburger Date: Wed, 25 Sep 2013 10:49:09 +0200 Subject: [PATCH] arm:caching enable barriers Change-Id: I2c54a3c3c8f0502bf365901d771a989f7c556958 --- kernel/arch/earm/pg_utils.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/kernel/arch/earm/pg_utils.c b/kernel/arch/earm/pg_utils.c index df5930691..e676f7ecb 100644 --- a/kernel/arch/earm/pg_utils.c +++ b/kernel/arch/earm/pg_utils.c @@ -178,7 +178,8 @@ int pg_mapkernel(void) assert(!(kern_phys_start % ARM_SECTION_SIZE)); pde = kern_vir_start / ARM_SECTION_SIZE; /* start pde */ while(mapped < kern_kernlen) { - pagedir[pde] = (kern_phys & ARM_VM_SECTION_MASK) | ARM_VM_SECTION + pagedir[pde] = (kern_phys & ARM_VM_SECTION_MASK) + | ARM_VM_SECTION | ARM_VM_SECTION_SUPER | ARM_VM_SECTION_DOMAIN | ARM_VM_SECTION_CACHED; @@ -192,6 +193,7 @@ int pg_mapkernel(void) void vm_enable_paging(void) { u32_t sctlr; + u32_t actlr; write_ttbcr(0); @@ -209,9 +211,20 @@ void vm_enable_paging(void) /* AFE set to zero (default reset value): not using simplified model. */ sctlr &= ~SCTLR_AFE; - /* Enable instruction and data cache */ + /* Enable instruction ,data cache and branch prediction */ sctlr |= SCTLR_C; sctlr |= SCTLR_I; + sctlr |= SCTLR_Z; + + /* Enable barriers */ + sctlr |= SCTLR_CP15BEN; + + /* Enable L2 cache (cortex-a8) */ + #define CORTEX_A8_L2EN (0x02) + actlr = read_actlr(); + actlr |= CORTEX_A8_L2EN; + write_actlr(actlr); + write_sctlr(sctlr); } -- 2.44.0