pci_reserve(devind);
/* printf("cr = 0x%x\n", pci_attr_r16(devind, PCI_CR)); */
bar= pci_attr_r32(devind, PCI_BAR) & 0xffffffe0;
- if ((bar & 0x3ff) >= 0x100-32 || bar < 0x400)
- {
- printf("rtl8029: ignoring bad base address 0x%x for QEMU\n",
- bar);
- /* panic("", "base address is not properly configured", NO_NUM); */
- }
+
+ if (bar < 0x400)
+ panic("", "base address is not properly configured", NO_NUM);
+
dep->de_base_port= bar;
ilr= pci_attr_r8(devind, PCI_ILR);
#if !__minix_vmd
-#define debug 0
#define irq_mode_pci(irq) ((void)0)
#endif
#define PBT_INTEL 1
#define PBT_PCIBRIDGE 2
+PRIVATE int debug= 0;
+
PRIVATE struct pcibus
{
int pb_type;
} pcidev[NR_PCIDEV];
PRIVATE int nr_pcidev= 0;
+/* Work around the limitation of the PCI emulation in QEMU 0.7.1 */
+PRIVATE int qemu_pci= 0;
+
FORWARD _PROTOTYPE( void pci_intel_init, (void) );
FORWARD _PROTOTYPE( void probe_bus, (int busind) );
FORWARD _PROTOTYPE( int do_isabridge, (int busind) );
{
static int first_time= 1;
+ long v;
+
if (!first_time)
return;
+ v= 0;
+ env_parse("qemu_pci", "d", 0, &v, 0, 1);
+ qemu_pci= v;
+
+ v= 0;
+ env_parse("pci_debug", "d", 0, &v, 0, 1);
+ debug= v;
+
+
/* We don't expect to interrupted */
assert(first_time == 1);
first_time= -1;
did= pci_attr_r16(devind, PCI_DID);
headt= pci_attr_r8(devind, PCI_HEADT);
sts= pci_attr_rsts(devind);
+
+ if (vid == NO_VID)
+ break; /* Nothing here */
+
if (sts & (PSR_SSE|PSR_RMAS|PSR_RTAS))
{
-#if 0
- printf(
+ if (qemu_pci)
+ {
+ printf(
"pci: ignoring bad value 0x%x in sts for QEMU\n",
sts & (PSR_SSE|PSR_RMAS|PSR_RTAS));
-#endif
- break;
- }
- if (vid == NO_VID)
- {
- /* Some bridge implementations do support
- * pci_attr_rsts.
- */
- break;
+ }
+ else
+ break;
}
dstr= pci_dev_name(vid, did);
printf("INT%c: %d\n", 'A'+i, irq);
if (!(elcr & (1 << irq)))
{
- printf("IRQ %d is not level triggered\n",
- irq);
- printf("(ignored for QEMU)\n");
- /* panic(NULL,NULL, NO_NUM); */
+ if (qemu_pci)
+ {
+ printf(
+ "IRQ is not level triggered (ignored for QEMU)\n");
+ }
+ else
+ {
+ panic("PCI",
+ "IRQ is not level triggered\n",
+ NO_NUM);
+ }
}
irq_mode_pci(irq);
}