From: acevest <zhaoyanbai@126.com>
Date: Thu, 11 Nov 2021 15:51:05 +0000 (+0800)
Subject: 添加对PCI代码的注释
X-Git-Url: http://zhaoyanbai.com/repos/doxygen.log?a=commitdiff_plain;h=610f911299afe60afccf60d400dc0554332b69da;p=kernel.git

添加对PCI代码的注释
---

diff --git a/drivers/pci.c b/drivers/pci.c
index b19fe9c..e1cd00a 100644
--- a/drivers/pci.c
+++ b/drivers/pci.c
@@ -226,6 +226,7 @@ void setup_pci() {
     }
 
     dump_pci_dev();
+    asm("cli;hlt;");
 }
 
 typedef struct pci_info {
@@ -239,15 +240,29 @@ pci_info_t pci_info[] = {
     {0x000000, 0, "VGA-Compatible devices", "Any device except for VGA-Compatible devices"},
     {0x000100, 0, "VGA-Compatible device", "VGA-Compatible Device"},
     {0x010000, 0, "SCSI Bus Controller", "SCSI Bus Controller"},
-    {0x0101, 1, "IDE Controller", "IDE Controller"},
+    {0x010100, 0, "IDE Controller", "ISA Compatibility mode-only controller"},
+    {0x010105, 0, "IDE Controller", "PCI native mode-only controller"},
+    {0x01010A, 0, "IDE Controller",
+     "ISA Compatibility mode controller, supports both channels switched to PCI native mode"},
+    {0x01010F, 0, "IDE Controller",
+     "PCI native mode controller, supports both channels switched to ISA compatibility mode"},
+    {0x010180, 0, "IDE Controller", "ISA Compatibility mode-only controller, supports bus mastering"},
+    {0x010185, 0, "IDE Controller", "PCI native mode-only controller, supports bus mastering"},
+    {0x01018A, 0, "IDE Controller",
+     "ISA Compatibility mode controller, supports both channels switched to PCI native mode, supports bus mastering"},
+    {0x01018F, 0, "IDE Controller",
+     "PCI native mode controller, supports both channels switched to ISA compatibility mode, supports bus mastering"},
     {0x010200, 0, "Floppy Disk Controller", "Floppy Disk Controller"},
     {0x010300, 0, "IPI Bus Controller", "IPI Bus Controller"},
     {0x010400, 0, "RAID Controller", "RAID Controller"},
     {0x010520, 0, "ATA Controller", "ATA Controller (Single DMA)"},
     {0x010530, 0, "ATA Controller", "ATA Controller (Chained DMA)"},
-    {0x010600, 0, "Serial ATA", "Serial ATA (Vendor Specific Interface)"},
-    {0x010601, 0, "Serial ATA", "Serial ATA (AHCI 1.0)"},
+    {0x010600, 0, "Serial ATA", "Vendor Specific Interface"},
+    {0x010601, 0, "Serial ATA", "AHCI 1.0"},
+    {0x010602, 0, "Serial ATA", "Serial Storage Bus"},
     {0x010700, 0, "SCSI", "Serial Attached SCSI (SAS)"},
+    {0x010801, 0, "NVM Controller", "NVMHCI"},
+    {0x010802, 0, "NVM Controller", "NVM Express"},
     {0x018000, 0, "Storage Controller", "Other Mass Storage Controller"},
     {0x020000, 0, "Ethernet Controller", "Ethernet Controller"},
     {0x020100, 0, "Token Ring Controller", "Token Ring Controller"},
@@ -278,12 +293,13 @@ pci_info_t pci_info[] = {
     {0x060500, 0, "PCMCIA Bridge", "PCMCIA Bridge"},
     {0x060600, 0, "NuBus Bridge", "NuBus Bridge"},
     {0x060700, 0, "CardBus Bridge", "CardBus Bridge"},
-    {0x0608, 1, "RACEway Bridge", "RACEway Bridge"},
-    {0x060940, 0, "PCI-to-PCI Bridge", "PCI-to-PCI Bridge (Semi-Transparent, Primary)"},
-    {0x060980, 0, "PCI-to-PCI Bridge", "PCI-to-PCI Bridge (Semi-Transparent, Secondary)"},
-    {0x060A00, 0, "InfiniBrand-to-PCI Host Bridge", "InfiniBrand-to-PCI Host Bridge"},
-    {0x068000, 0, "Other Bridge Device", "Other Bridge Device"},
-    {0x070000, 0, "Serial Controller", "Generic XT-Compatible Serial Controller"},
+    {0x060800, 0, "RACEway Bridge", "Transparent Mode"},
+    {0x060801, 0, "RACEway Bridge", "Endpoint Mode"},
+    {0x060940, 0, "PCI-to-PCI Bridge", "Semi-Transparent, Primary bus towards host CPU"},
+    {0x060980, 0, "PCI-to-PCI Bridge", "Semi-Transparent, Secondary bus towards host CPU"},
+    {0x060A, 1, "InfiniBrand-to-PCI Host Bridge", "InfiniBrand-to-PCI Host Bridge"},
+    {0x0680, 1, "Other Bridge Device", "Other Bridge Device"},
+    {0x070000, 0, "Serial Controller", " 8250-Generic XT-Compatible Serial Controller"},
     {0x070001, 0, "Serial Controller", "16450-Compatible Serial Controller"},
     {0x070002, 0, "Serial Controller", "16550-Compatible Serial Controller"},
     {0x070003, 0, "Serial Controller", "16650-Compatible Serial Controller"},
@@ -315,51 +331,54 @@ pci_info_t pci_info[] = {
     {0x080200, 0, "8254 System Timer", "Generic 8254 System Timer"},
     {0x080201, 0, "ISA System Timer", "ISA System Timer"},
     {0x080202, 0, "EISA System Timer", "EISA System Timer"},
+    {0x080203, 0, "Timer", "HPET"},
     {0x080300, 0, "Generic RTC Controller", "Generic RTC Controller"},
     {0x080301, 0, "ISA RTC Controller", "ISA RTC Controller"},
     {0x080400, 0, "Generic PCI Hot-Plug Controller", "Generic PCI Hot-Plug Controller"},
     {0x088000, 0, "Other System Peripheral", "Other System Peripheral"},
-    {0x090000, 0, "Keyboard Controller", "Keyboard Controller"},
-    {0x090100, 0, "Digitizer", "Digitizer"},
-    {0x090200, 0, "Mouse Controller", "Mouse Controller"},
-    {0x090300, 0, "Scanner Controller", "Scanner Controller"},
+    {0x0900, 1, "Keyboard Controller", "Keyboard Controller"},
+    {0x0901, 1, "Digitizer Pen", "Digitizer"},
+    {0x0902, 1, "Mouse Controller", "Mouse Controller"},
+    {0x0903, 1, "Scanner Controller", "Scanner Controller"},
     {0x090400, 0, "Gameport Controller (Generic)", "Gameport Controller (Generic)"},
     {0x090410, 0, "Gameport Contrlller (Legacy)", "Gameport Contrlller (Legacy)"},
     {0x098000, 0, "Other Input Controller", "Other Input Controller"},
     {0x0A0000, 0, "Generic Docking Station", "Generic Docking Station"},
     {0x0A8000, 0, "Other Docking Station", "Other Docking Station"},
-    {0x0B0000, 0, "386 Processor", "386 Processor"},
-    {0x0B0100, 0, "486 Processor", "486 Processor"},
-    {0x0B0200, 0, "Pentium Processor", "Pentium Processor"},
-    {0x0B1000, 0, "Alpha Processor", "Alpha Processor"},
-    {0x0B2000, 0, "PowerPC Processor", "PowerPC Processor"},
-    {0x0B3000, 0, "MIPS Processor", "MIPS Processor"},
-    {0x0B4000, 0, "Co-Processor", "Co-Processor"},
-    {0x0C0000, 0, "IEEE 1394 Controller", "IEEE 1394 Controller (FireWire)"},
-    {0x0C0010, 0, "IEEE 1394 Controller", "IEEE 1394 Controller (1394 OpenHCI Spec)"},
-    {0x0C0100, 0, "ACCESS.bus", "ACCESS.bus"},
-    {0x0C0200, 0, "SSA", "SSA"},
-    {0x0C0300, 0, "USB", "USB (Universal Host Controller Spec)"},
-    {0x0C0310, 0, "USB", "USB (Open Host Controller Spec"},
-    {0x0C0320, 0, "USB2 Host Controller", "USB2 Host Controller (Intel Enhanced Host Controller Interface)"},
-    {0x0C0380, 0, "USB", "USB"},
-    {0x0C03FE, 0, "USB", "USB (Not Host Controller)"},
-    {0x0C0400, 0, "Fibre Channel", "Fibre Channel"},
-    {0x0C0500, 0, "SMBus", "SMBus"},
+    {0x0B00, 1, "386 Processor", "386 Processor"},
+    {0x0B01, 1, "486 Processor", "486 Processor"},
+    {0x0B02, 1, "Pentium Processor", "Pentium Processor"},
+    {0x0B10, 1, "Alpha Processor", "Alpha Processor"},
+    {0x0B20, 1, "PowerPC Processor", "PowerPC Processor"},
+    {0x0B30, 1, "MIPS Processor", "MIPS Processor"},
+    {0x0B40, 1, "Co-Processor", "Co-Processor"},
+    {0x0B80, 1, "Other Processor", "Other Processor"},
+    {0x0C0000, 0, "FireWire IEEE 1394 Controller", "Generic"},
+    {0x0C0010, 0, "FireWire IEEE 1394 Controller", "OHCI"},
+    {0x0C01, 1, "ACCESS Bus Controller", "ACCESS Bus Controller"},
+    {0x0C02, 1, "SSA", "SSA"},
+    {0x0C0300, 0, "USB", "UHCI (Universal Host Controller Spec)"},
+    {0x0C0310, 0, "USB", "OHCI (Open Host Controller Spec"},
+    {0x0C0320, 0, "USB2 Host Controller", "EHCI (Intel Enhanced Host Controller Interface)"},
+    {0x0C0330, 0, "USB3 Host Controller", "XHCI (USB3) Controller"},
+    {0x0C0380, 0, "USB Controller", "Unspecified"},
+    {0x0C03FE, 0, "USB Device", "USB (Not Host Controller)"},
+    {0x0C04, 1, "Fibre Channel", "Fibre Channel"},
+    {0x0C05, 1, "SMBus", "SMBus"},
     {0x0C0600, 0, "InfiniBand", "InfiniBand"},
     {0x0C0700, 0, "IPMI SMIC Interface", "IPMI SMIC Interface"},
     {0x0C0701, 0, "IPMI Kybd Interface", "IPMI Kybd Controller Style Interface"},
     {0x0C0702, 0, "IPMI Block Interface", "IPMI Block Transfer Interface"},
     {0x0C0800, 0, "SERCOS Interface", "SERCOS Interface Standard (IEC 61491)"},
     {0x0C0900, 0, "CANbus", "CANbus"},
-    {0x0D0000, 0, "iRDA Controller", "iRDA Compatible Controller"},
-    {0x0D0100, 0, "IR Controller", "Consumer IR Controller"},
-    {0x0D1000, 0, "RF Controller", "RF Controller"},
-    {0x0D1100, 0, "Bluetooth Controller", "Bluetooth Controller"},
-    {0x0D1200, 0, "Broadband Controller", "Broadband Controller"},
-    {0x0D2000, 0, "Ethernet Controller (802.11a)", "Ethernet Controller (802.11a)"},
-    {0x0D2100, 0, "Ethernet Controller (802.11b)", "Ethernet Controller (802.11b)"},
-    {0x0D8000, 0, "Wireless Controller", "Other Wireless Controller"},
+    {0x0D00, 1, "iRDA Controller", "iRDA Compatible Controller"},
+    {0x0D01, 1, "IR Controller", "Consumer IR Controller"},
+    {0x0D10, 1, "RF Controller", "RF Controller"},
+    {0x0D11, 1, "Bluetooth Controller", "Bluetooth Controller"},
+    {0x0D12, 1, "Broadband Controller", "Broadband Controller"},
+    {0x0D20, 1, "Ethernet Controller (802.11a)", "Ethernet Controller (802.11a)"},
+    {0x0D21, 1, "Ethernet Controller (802.11b)", "Ethernet Controller (802.11b)"},
+    {0x0D80, 1, "Wireless Controller", "Other Wireless Controller"},
     {0x0E00, 1, "I20 Architecture", "I20 Architecture"},
     {0x0E0000, 0, "Message FIFO", "Message FIFO"},
     {0x0F0100, 0, "TV Controller", "TV Controller"},
diff --git a/include/pci.h b/include/pci.h
index 51d24bf..10f4160 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -23,6 +23,36 @@
 #define PCI_DATA 0xCFC  // CONFIG_DATA
 
 // PCI Device
+//  All PCI compliant devices must support the Vendor ID, Device ID, Command and Status, Revision ID, Class Code and
+//  Header Type fields.Implementation of the other registers is optional, depending upon the devices functionality.
+
+// Command: Provides control over a device's ability to generate and respond to PCI cycles. Where the only functionality
+// guaranteed to be supported by all devices is, when a 0 is written to this register, the device is disconnected from
+// the PCI bus for all accesses except Configuration Space access. Class Code: A read-only register that specifies the
+// type of function the device performs.
+// Command的bit2比较重要(Bus Master)，如果将它置为1，则该设备可以充当总线的主设备，否则，设备无法生成对PCI的访问。
+// 这个位需要在对硬盘DMA的时候用到
+
+// Subclass: A read-only register that specifies the specific function the device performs.
+
+// Prog IF(Programming Interface Byte): 一个只读寄存器，指定设备具有的寄存器级别的编程接口(如果有的话)
+
+// Header Type: 表示0x10字节开始的具体布局，同时指示该Device是否支持多个Function
+//  0x00 - General Device
+//  0x01 - PCI-to-PCI Bridge
+//  0x02 - CardBus Bridge
+//  如果bit7置位，则该Device有多个Function，否则为只支持单个Function的Device
+
+// Interrupt Line: 指示该设备连接到系统中的中断控制器的哪个引脚，对于x86架构来说，该寄存器对应于中断控制器IRQ编号0-15（
+// 而不是 I/O APIC IRQ 编号。  值0xFF为没有连接的意思。
+
+// Interrupt Pin: 指明设备使用哪个中断引脚，值0x01对应INTA#, 0x02对应INTB#， 0x03对应INTC#, 0x04对应INTD#,
+// 0x00表示不使用中断引脚。
+
+// Capabilities Pointer: Points (i.e. an offset into this function's configuration space) to a linked list of new
+// capabilities implemented by the device. Used if bit 4 of the status register (Capabilities List bit) is set to 1. The
+// bottom two bits are reserved and should be masked before the Pointer is used to access the Configuration Space.
+
 /*
  * 31                        16 15                         0
  * +---------------------------+---------------------------+ 00H
@@ -32,7 +62,7 @@
  * +-----------------------------------------+-------------+ 08H
  * |  Class Code |  Subclass   |   Prog IF   |  Revision   |
  * +-------------+-------------+-------------+-------------+ 0CH
- * |    BIST     | Header Type |LatencyTimer |CacheLineSize|
+ * |    BIST     | Header Type |LatencyTimer |CacheLineSize|           // BITS: built-in self test
  * +-------------+-------------+-------------+-------------+ 10H
  * |                Base Address Register 0                |
  * +-------------------------------------------------------+ 14H
@@ -192,8 +222,6 @@ void pci_write_config_word(int value, int cmd);
 void pci_write_config_long(int value, int cmd);
 
 // PCI Bridge
-//  All PCI compliant devices must support the Vendor ID, Device ID, Command and Status, Revision ID, Class Code and
-//  Header Type fields.Implementation of the other registers is optional, depending upon the devices functionality.
 /*
  * 31                        16 15                         0
  * +---------------------------+---------------------------+ 00H