From: acezhao Date: Fri, 24 May 2019 09:20:39 +0000 (+0800) Subject: add stm32 X-Git-Url: http://zhaoyanbai.com/repos/doxygen.log?a=commitdiff_plain;h=2dd62d76d39bf87022c4463afb644612fad46b64;p=acecode.git add stm32 --- diff --git a/learn/stm32/F103/.cproject b/learn/stm32/F103/.cproject new file mode 100644 index 0000000..b2ee816 --- /dev/null +++ b/learn/stm32/F103/.cproject @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/learn/stm32/F103/.gitignore b/learn/stm32/F103/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/learn/stm32/F103/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/learn/stm32/F103/.project b/learn/stm32/F103/.project new file mode 100644 index 0000000..34e4117 --- /dev/null +++ b/learn/stm32/F103/.project @@ -0,0 +1,28 @@ + + + F103 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + fr.ac6.mcu.ide.core.MCUProjectNature + fr.ac6.mcu.ide.core.MCUSingleCoreProjectNature + + diff --git a/learn/stm32/F103/.settings/language.settings.xml b/learn/stm32/F103/.settings/language.settings.xml new file mode 100644 index 0000000..5ccf38d --- /dev/null +++ b/learn/stm32/F103/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/learn/stm32/F103/F103 Run.cfg b/learn/stm32/F103/F103 Run.cfg new file mode 100644 index 0000000..0dfaba6 --- /dev/null +++ b/learn/stm32/F103/F103 Run.cfg @@ -0,0 +1,35 @@ +# This is an OneNetMini board with a single STM32F103C8Tx chip +# +# Generated by System Workbench for STM32 +# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s) + +source [find interface/stlink.cfg] + +set WORKAREASIZE 0x5000 + +transport select "hla_swd" + +set CHIPNAME STM32F103C8Tx +set BOARDNAME OneNetMini + +# CHIPNAMES state +set CHIPNAME_CPU0_ACTIVATED 1 + +# Enable debug when in low power modes +set ENABLE_LOW_POWER 1 + +# Stop Watchdog counters when halt +set STOP_WATCHDOG 1 + +# STlink Debug clock frequency +set CLOCK_FREQ 4000 + +# use software system reset +reset_config none +set CONNECT_UNDER_RESET 0 + +# BCTM CPU variables + + + +source [find target/stm32f1x.cfg] diff --git a/learn/stm32/F103/LinkerScript.ld b/learn/stm32/F103/LinkerScript.ld new file mode 100644 index 0000000..3d876cb --- /dev/null +++ b/learn/stm32/F103/LinkerScript.ld @@ -0,0 +1,202 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : Auto-generated by Ac6 System Workbench +** +** Abstract : Linker script for STM32F103C8Tx Device from STM32F1 series +** 20Kbytes RAM +** 64Kbytes ROM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed �as is,� without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 Ac6

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of Ac6 nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20005000; /* end of RAM */ + +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K + ROM (rx) : ORIGIN = 0x8000000, LENGTH = 64K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into ROM memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into ROM memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into ROM memory*/ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into RAM memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> ROM + + + /* Uninitialized data section into RAM memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/learn/stm32/F103/src/debug.h b/learn/stm32/F103/src/debug.h new file mode 100644 index 0000000..878c656 --- /dev/null +++ b/learn/stm32/F103/src/debug.h @@ -0,0 +1,13 @@ +/* + * debug.h + * + * Created on: May 24, 2019 + * Author: ace + */ + +#ifndef DEBUG_H_ +#define DEBUG_H_ + + + +#endif /* DEBUG_H_ */ diff --git a/learn/stm32/F103/src/gpio.c b/learn/stm32/F103/src/gpio.c new file mode 100644 index 0000000..a33b6ac --- /dev/null +++ b/learn/stm32/F103/src/gpio.c @@ -0,0 +1,34 @@ +/* + * gpio.c + * + * Created on: May 24, 2019 + * Author: ace + */ + +#include "gpio.h" + + + +void GPIOSetOutput(GPIO_t *gpio, uint32_t pin, GPIOOutputMode_t mode, GPIOOutputSpeed_t speed) { + uint32_t *CR = pin < 8 ? &gpio->CRL : &gpio->CRH; + uint32_t n = (pin < 8 ? pin : pin - 8) * 4; + + uint32_t mask = 0x0FU; + *CR &= ~mask << n; // 清除CNF、MODE的比特位 + *CR |= (mode|speed) << n; // 设置为相应的输出模块+相应的速度 +} + + +void GPIOToggle(GPIO_t *gpio, uint32_t pin) { + gpio->ODR ^= 1 << pin; +} + + + +void GPIOWrite(GPIO_t *gpio, uint32_t pin, uint32_t level) { + if(level == LOW) { + gpio->BRR |= 1 << pin; + } else { + gpio->BSRR |= 1 << pin; + } +} diff --git a/learn/stm32/F103/src/gpio.h b/learn/stm32/F103/src/gpio.h new file mode 100644 index 0000000..ba418e5 --- /dev/null +++ b/learn/stm32/F103/src/gpio.h @@ -0,0 +1,56 @@ +/* + * gpio.h + * + * Created on: May 24, 2019 + * Author: ace + */ + +#ifndef GPIO_H_ +#define GPIO_H_ + +#include "stm32f103.h" + + +typedef struct { + uint32_t CRL; + uint32_t CRH; + uint32_t IDR; + uint32_t ODR; + uint32_t BSRR; // Bit Set Reset Register + uint32_t BRR; // Bit Reset Register + uint32_t LCKR; +} GPIO_t; + +#define GPIOA ((GPIO_t*)GPIOA_BASE) +#define GPIOB ((GPIO_t*)GPIOB_BASE) +#define GPIOC ((GPIO_t*)GPIOC_BASE) +#define GPIOD ((GPIO_t*)GPIOD_BASE) +#define GPIOE ((GPIO_t*)GPIOE_BASE) + + +typedef enum { + GPIO_OUTPUT_MODE_GP_PP = 0x00, + GPIO_OUTPUT_MODE_GP_OD = 0x01, + GPIO_OUTPUT_MODE_AF_PP = 0x02, + GPIO_OUTPUT_MODE_AF_OD = 0x03, +} GPIOOutputMode_t; + + +typedef enum { + GPIO_OUTPUT_SPEED_10MHZ = 0x01, + GPIO_OUTPUT_SPEED_20MHZ = 0x02, + GPIO_OUTPUT_SPEED_50MHZ = 0x03, +} GPIOOutputSpeed_t; + +#define HIGH 1 +#define LOW 0 + + + +void GPIOSetOutput(GPIO_t *gpio, uint32_t pin, GPIOOutputMode_t mode, GPIOOutputSpeed_t speed); + +void GPIOToggle(GPIO_t *gpio, uint32_t pin); +void GPIOWrite(GPIO_t *gpio, uint32_t pin, uint32_t level); + + +#endif /* GPIO_H_ */ diff --git a/learn/stm32/F103/src/main.c b/learn/stm32/F103/src/main.c new file mode 100644 index 0000000..da17e68 --- /dev/null +++ b/learn/stm32/F103/src/main.c @@ -0,0 +1,45 @@ +/* + * main.c + * + * Created on: May 24, 2019 + * Author: ace + */ + + +#include "stm32f103.h" + + +#include "gpio.h" +#include "rcc.h" + +#define APB2ENR (*(unsigned int*)(RCC_BASE+0x18)) + +unsigned int pin = 8; + + +void SystemInit() { + // 使能时钟 + RCCEnableGPIOBClock(); + + GPIOSetOutput(GPIOB, pin, GPIO_OUTPUT_MODE_GP_PP, GPIO_OUTPUT_SPEED_50MHZ); +} + +void delay() { + int i=65536; + while(i--); +} + +int main() { + + while(1) { + GPIOWrite(GPIOB, pin, HIGH); + delay(); + GPIOWrite(GPIOB, pin, LOW); + delay(); + continue; + GPIOToggle(GPIOB, pin); + delay(); + } + + return 0; +} diff --git a/learn/stm32/F103/src/rcc.c b/learn/stm32/F103/src/rcc.c new file mode 100644 index 0000000..aee943b --- /dev/null +++ b/learn/stm32/F103/src/rcc.c @@ -0,0 +1,12 @@ +/* + * rcc.c + * + * Created on: May 24, 2019 + * Author: ace + */ + +#include "rcc.h" + +void __RCCEnableAPB2(uint32_t en) { + RCC->APB2ENR |= en; +} diff --git a/learn/stm32/F103/src/rcc.h b/learn/stm32/F103/src/rcc.h new file mode 100644 index 0000000..23370aa --- /dev/null +++ b/learn/stm32/F103/src/rcc.h @@ -0,0 +1,44 @@ +/* + * rcc.h + * + * Created on: May 24, 2019 + * Author: ace + */ + +#ifndef RCC_H_ +#define RCC_H_ + +#include "stm32f103.h" + +typedef struct { + uint32_t CR; + uint32_t CFGR; + uint32_t CIR; + uint32_t APB2RSTR; + uint32_t APB1RSTR; + uint32_t AHBENR; + uint32_t APB2ENR; + uint32_t APB1ENR; + uint32_t BDCR; + uint32_t CSR; +} RCC_t; + +#define RCC ((RCC_t*) RCC_BASE) + +#define RCC_APB2ENR_IOPAEN 0x00000004 +#define RCC_APB2ENR_IOPBEN 0x00000008 +#define RCC_APB2ENR_IOPCEN 0x00000010 +#define RCC_APB2ENR_IOPDEN 0x00000020 +#define RCC_APB2ENR_IOPEEN 0x00000040 + + + +void __RCCEnableAPB2(uint32_t en); + +#define RCCEnableGPIOAClock() __RCCEnableAPB2(RCC_APB2ENR_IOPAEN) +#define RCCEnableGPIOBClock() __RCCEnableAPB2(RCC_APB2ENR_IOPBEN) +#define RCCEnableGPIOCClock() __RCCEnableAPB2(RCC_APB2ENR_IOPCEN) +#define RCCEnableGPIODClock() __RCCEnableAPB2(RCC_APB2ENR_IOPDEN) +#define RCCEnableGPIOEClock() __RCCEnableAPB2(RCC_APB2ENR_IOPEEN) + +#endif /* RCC_H_ */ diff --git a/learn/stm32/F103/src/stm32f103.h b/learn/stm32/F103/src/stm32f103.h new file mode 100644 index 0000000..5ddcb91 --- /dev/null +++ b/learn/stm32/F103/src/stm32f103.h @@ -0,0 +1,31 @@ +/* + * registers.h + * + * Created on: May 24, 2019 + * Author: ace + */ + +#ifndef STM32F103_H_ +#define STM32F103_H_ + + +#include + + +#define PERIPH_BASE 0x40000000 +#define APB1PERIPH_BASE (PERIPH_BASE+0x00000) +#define APB2PERIPH_BASE (PERIPH_BASE+0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE+0x20000) + + +#define GPIOA_BASE (APB2PERIPH_BASE+0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE+0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE+0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE+0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE+0x1800) + +#define RCC_BASE (AHBPERIPH_BASE+0x1000) + + + +#endif /* STM32F103_H_ */ diff --git a/learn/stm32/F103/startup/startup_stm32.s b/learn/stm32/F103/startup/startup_stm32.s new file mode 100644 index 0000000..2cfb412 --- /dev/null +++ b/learn/stm32/F103/startup/startup_stm32.s @@ -0,0 +1,408 @@ +/** + ****************************************************************************** + * @file startup_stm32.s dedicated to STM32F103C8Tx device + * @author Ac6 + * @version V1.0.0 + * @date 2019-05-24 + ****************************************************************************** + */ + + +.syntax unified +.cpu cortex-m3 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The STM32F103C8Tx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window Watchdog interrupt */ + .word PVD_IRQHandler /* PVD through EXTI line detection interrupt */ + .word TAMPER_IRQHandler /* Tamper interrupt */ + .word RTC_IRQHandler /* RTC global interrupt */ + .word FLASH_IRQHandler /* Flash global interrupt */ + .word RCC_IRQHandler /* RCC global interrupt */ + .word EXTI0_IRQHandler /* EXTI Line0 interrupt */ + .word EXTI1_IRQHandler /* EXTI Line1 interrupt */ + .word EXTI2_IRQHandler /* EXTI Line2 interrupt */ + .word EXTI3_IRQHandler /* EXTI Line3 interrupt */ + .word EXTI4_IRQHandler /* EXTI Line4 interrupt */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel1 global interrupt */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel2 global interrupt */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel3 global interrupt */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel4 global interrupt */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel5 global interrupt */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel6 global interrupt */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel7 global interrupt */ + .word ADC1_2_IRQHandler /* ADC1 and ADC2 global interrupt */ + .word USB_HP_CAN_TX_IRQHandler /* USB High Priority or CAN TX interrupts */ + .word USB_LP_CAN_RX0_IRQHandler /* USB Low Priority or CAN RX0 interrupts */ + .word CAN_RX1_IRQHandler /* CAN RX1 interrupt */ + .word CAN_SCE_IRQHandler /* CAN SCE interrupt */ + .word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupts */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM3_IRQHandler /* TIM3 global interrupt */ + .word TIM4_IRQHandler /* TIM4 global interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 error interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 event interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_IRQHandler /* SPI2 global interrupt */ + .word USART1_IRQHandler /* USART1 global interrupt */ + .word USART2_IRQHandler /* USART2 global interrupt */ + .word USART3_IRQHandler /* USART3 global interrupt */ + .word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */ + .word RTCAlarm_IRQHandler /* RTC Alarms through EXTI line interrupt */ + .word 0 /* Reserved */ + .word TIM8_BRK_IRQHandler /* TIM8 Break interrupt */ + .word TIM8_UP_IRQHandler /* TIM8 Update interrupt */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation interrupts */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare interrupt */ + .word ADC3_IRQHandler /* ADC3 global interrupt */ + .word FSMC_IRQHandler /* FSMC global interrupt */ + .word SDIO_IRQHandler /* SDIO global interrupt */ + .word TIM5_IRQHandler /* TIM5 global interrupt */ + .word SPI3_IRQHandler /* SPI3 global interrupt */ + .word UART4_IRQHandler /* UART4 global interrupt */ + .word UART5_IRQHandler /* UART5 global interrupt */ + .word TIM6_IRQHandler /* TIM6 global interrupt */ + .word TIM7_IRQHandler /* TIM7 global interrupt */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 global interrupt */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 global interrupt */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 global interrupt */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 and DMA2 Channel5 global interrupt */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN_TX_IRQHandler + .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN_RX0_IRQHandler + .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak SystemInit + +/************************ (C) COPYRIGHT Ac6 *****END OF FILE****/ diff --git a/learn/stm32/F103/startup/sysmem.c b/learn/stm32/F103/startup/sysmem.c new file mode 100644 index 0000000..bd95902 --- /dev/null +++ b/learn/stm32/F103/startup/sysmem.c @@ -0,0 +1,82 @@ +/** +***************************************************************************** +** +** File : sysmem.c +** +** Author : Ac6 +** +** Abstract : System Workbench Minimal System Memory calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : System Workbench for MCU +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** +**

© COPYRIGHT(c) 2014 Ac6

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of Ac6 nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Includes */ +#include +#include + +/* Variables */ +extern int errno; +register char * stack_ptr asm("sp"); + +/* Functions */ + +/** + _sbrk + Increase program data space. Malloc and related functions depend on this +**/ +caddr_t _sbrk(int incr) +{ + extern char end asm("end"); + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) + heap_end = &end; + + prev_heap_end = heap_end; + if (heap_end + incr > stack_ptr) + { + errno = ENOMEM; + return (caddr_t) -1; + } + + heap_end += incr; + + return (caddr_t) prev_heap_end; +} +