vm:enable the instruction and data caches.

Enable the instruction and data caches. Whether data is cached
will depend on the MMU entries.

Change-Id: I51e9ebc38924db5525d4e7ad9ab69b2a5b1ca7b4

diff --git a/kernel/arch/arm/pg_utils.c b/kernel/arch/arm/pg_utils.c
index 15877d4c8aa5fcea11f38bdc416992e22ddb972d..1d3bec48e1b5ee6823b512e7692d937242507356 100644 (file)
--- a/kernel/arch/arm/pg_utils.c
+++ b/kernel/arch/arm/pg_utils.c
@@ -211,9 +211,14 @@ void vm_enable_paging(void)
        /* Set all Domains to Client */
        write_dacr(0x55555555);
 
-       /* Enable MMU and access flag */
        sctlr = read_sctlr();
+
+       /* Enable MMU */
        sctlr |= (SCTLR_M);
+
+       /* Enable instruction and data cache */
+       sctlr |= SCTLR_C;
+       sctlr |= SCTLR_I;
        write_sctlr(sctlr);
 }