2012/10/17 12:00:00,share/terminfo
2012/02/10 16:16:12,share/zoneinfo
2011/12/25 06:09:09,sys/arch/i386/stand
+2012/10/17 12:00:00,sys/arch/x86/include
2012/01/16 18:47:57,sys/lib/libsa
2011/10/30 00:28:57,sys/lib/libz
2012/10/17 12:00:00,sys/Makefile
INCSDIR=/usr/include/x86
-INCS= \
+INCS= aout_machdep.h \
bootinfo.h \
+ cacheinfo.h \
cpu.h \
+ cpu_ucode.h \
+ cputypes.h \
+ cpuvar.h \
float.h \
ieee.h ieeefp.h \
- math.h mutex.h \
+ intr.h intrdefs.h \
+ lock.h \
+ math.h mutex.h mtrr.h \
pio.h \
+ pmap.h \
+ pmap_pv.h \
+ psl.h \
+ pte.h \
rwlock.h \
-
+ specialreg.h \
+ sysarch.h \
+ trap.h \
+ via_padlock.h
.include <bsd.kinc.mk>
--- /dev/null
+/* $NetBSD: acpi_machdep.h,v 1.11 2012/09/23 00:31:05 chs Exp $ */
+
+/*
+ * Copyright 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_ACPI_MACHDEP_H_
+#define _X86_ACPI_MACHDEP_H_
+
+/*
+ * Machine-dependent code for ACPI.
+ */
+#include <machine/pio.h>
+#include <machine/i82489var.h>
+#include <machine/i82489reg.h>
+
+ACPI_STATUS acpi_md_OsInitialize(void);
+ACPI_PHYSICAL_ADDRESS acpi_md_OsGetRootPointer(void);
+
+#define acpi_md_OsIn8(x) inb((x))
+#define acpi_md_OsIn16(x) inw((x))
+#define acpi_md_OsIn32(x) inl((x))
+
+#define acpi_md_OsOut8(x, v) outb((x), (v))
+#define acpi_md_OsOut16(x, v) outw((x), (v))
+#define acpi_md_OsOut32(x, v) outl((x), (v))
+
+ACPI_STATUS acpi_md_OsInstallInterruptHandler(UINT32,
+ ACPI_OSD_HANDLER, void *, void **);
+void acpi_md_OsRemoveInterruptHandler(void *);
+
+ACPI_STATUS acpi_md_OsMapMemory(ACPI_PHYSICAL_ADDRESS, UINT32, void **);
+void acpi_md_OsUnmapMemory(void *, UINT32);
+ACPI_STATUS acpi_md_OsGetPhysicalAddress(void *LogicalAddress,
+ ACPI_PHYSICAL_ADDRESS *PhysicalAddress);
+
+BOOLEAN acpi_md_OsReadable(void *, UINT32);
+BOOLEAN acpi_md_OsWritable(void *, UINT32);
+void acpi_md_OsDisableInterrupt(void);
+void acpi_md_OsEnableInterrupt(void);
+
+int acpi_md_sleep(int);
+void acpi_md_sleep_init(void);
+
+uint32_t acpi_md_pdc(void);
+uint32_t acpi_md_ncpus(void);
+struct acpi_softc;
+void acpi_md_callback(struct acpi_softc *);
+
+#endif /* !_X86_ACPI_MACHDEP_H_ */
--- /dev/null
+/* $NetBSD: aout_machdep.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $ */
+
+/*
+ * Copyright (c) 1993 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_EXEC_H_
+#define _X86_EXEC_H_
+
+#define AOUT_LDPGSZ 4096
+
+/* Relocation format. */
+struct relocation_info_i386 {
+ int r_address; /* offset in text or data segment */
+ unsigned int r_symbolnum : 24, /* ordinal number of add symbol */
+ r_pcrel : 1, /* 1 if value should be pc-relative */
+ r_length : 2, /* log base 2 of value's width */
+ r_extern : 1, /* 1 if need to add symbol to value */
+ r_baserel : 1, /* linkage table relative */
+ r_jmptable : 1, /* relocate to jump table */
+ r_relative : 1, /* load address relative */
+ r_copy : 1; /* run time copy */
+};
+#define relocation_info relocation_info_i386
+
+#endif /* _X86_EXEC_H_ */
--- /dev/null
+/* $NetBSD: apicvar.h,v 1.5 2008/04/28 20:23:40 martin Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_APICVAR_H_
+#define _X86_APICVAR_H_
+
+struct apic_attach_args {
+ int apic_id;
+ int apic_version;
+ int flags;
+#define IOAPIC_PICMODE 0x01
+#define IOAPIC_VWIRE 0x02
+ paddr_t apic_address;
+ int apic_vecbase;
+};
+
+void apic_format_redir(const char *, const char *, int, u_int32_t, u_int32_t);
+
+#endif /* !_X86_APICVAR_H_ */
--- /dev/null
+/* $NetBSD: autoconf.h,v 1.3 2011/10/18 23:25:20 dyoung Exp $ */
+#ifndef _X86_AUTOCONF_H_
+#define _X86_AUTOCONF_H_
+
+#include <sys/device.h>
+
+void device_pci_props_register(device_t, void *);
+device_t device_pci_register(device_t, void *);
+device_t device_isa_register(device_t, void *);
+
+#endif /* _X86_AUTOCONF_H_ */
--- /dev/null
+/* $NetBSD: bios32.h,v 1.5 2008/04/28 20:23:40 martin Exp $ */
+
+/*-
+ * Copyright (c) 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1999, by UCHIYAMA Yasushi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the developer may NOT be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+struct bios32_entry_info {
+ paddr_t bei_base;
+ psize_t bei_size;
+ paddr_t bei_entry;
+};
+
+typedef struct bios32_entry_info *bios32_entry_info_t;
+
+struct bios32_entry {
+ void * offset;
+ u_int16_t segment;
+} __packed;
+
+typedef struct bios32_entry *bios32_entry_t;
+
+#define BIOS32_MAKESIG(a, b, c, d) \
+ ((a) | ((b) << 8) | ((c) << 16) | ((d) << 24))
+
+void bios32_init(void);
+int bios32_service(u_int32_t, bios32_entry_t, bios32_entry_info_t);
--- /dev/null
+/* $NetBSD: bus_defs.h,v 1.2 2011/08/25 15:06:10 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_BUS_H_
+#define _X86_BUS_H_
+
+#include <x86/busdefs.h>
+
+#ifdef BUS_SPACE_DEBUG
+#define BUS_SPACE_ALIGNED_ADDRESS(p, t) \
+ ((((u_long)(p)) & (sizeof(t)-1)) == 0)
+#define BUS_SPACE_ALIGNED_POINTER(p, t) BUS_SPACE_ALIGNED_ADDRESS(p, t)
+#else
+#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
+#endif /* BUS_SPACE_DEBUG */
+
+/*
+ * Bus address and size types
+ */
+typedef paddr_t bus_addr_t;
+typedef size_t bus_size_t;
+
+struct bus_space_tag;
+typedef struct bus_space_tag *bus_space_tag_t;
+
+struct bus_space_tag {
+ int bst_type;
+ bus_space_tag_t bst_super;
+ /* bst_present: bitmap indicating overrides present (1) in *this* tag,
+ * bst_exists: bitmap indicating overrides present (1) in *this* tag
+ * or in an ancestor's tag (follow bst_super to ancestors)
+ */
+ uint64_t bst_present;
+ uint64_t bst_exists;
+ const struct bus_space_overrides *bst_ov;
+ void *bst_ctx;
+};
+
+typedef vaddr_t bus_space_handle_t;
+
+typedef struct x86_bus_dma_tag *bus_dma_tag_t;
+typedef struct x86_bus_dmamap *bus_dmamap_t;
+
+#define BUS_DMA_TAG_VALID(__t) ((__t) != NULL)
+
+/*
+ * bus_dma_segment_t
+ *
+ * Describes a single contiguous DMA transaction. Values
+ * are suitable for programming into DMA registers.
+ */
+typedef struct x86_bus_dma_segment {
+ bus_addr_t ds_addr; /* DMA address */
+ bus_size_t ds_len; /* length of transfer */
+} bus_dma_segment_t;
+
+/*
+ * bus_dmamap_t
+ *
+ * Describes a DMA mapping. XXX exposing structure to LKM.
+ */
+struct x86_bus_dmamap {
+ /*
+ * PRIVATE MEMBERS: not for use by machine-independent code.
+ */
+ bus_size_t _dm_size; /* largest DMA transfer mappable */
+ int _dm_segcnt; /* number of segs this map can map */
+ bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */
+ bus_size_t _dm_boundary; /* don't cross this */
+ bus_addr_t _dm_bounce_thresh; /* bounce threshold; see tag */
+ int _dm_flags; /* misc. flags */
+
+ void *_dm_cookie; /* cookie for bus-specific functions */
+
+ /*
+ * PUBLIC MEMBERS: these are used by machine-independent code.
+ */
+ bus_size_t dm_maxsegsz; /* largest possible segment */
+ bus_size_t dm_mapsize; /* size of the mapping */
+ int dm_nsegs; /* # valid segments in mapping */
+ bus_dma_segment_t dm_segs[1]; /* segments; variable length */
+};
+
+#endif /* _X86_BUS_H_ */
--- /dev/null
+/* $NetBSD: bus_funcs.h,v 1.1 2011/07/01 17:10:01 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_BUS_FUNCS_H_
+#define _X86_BUS_FUNCS_H_
+
+extern bus_space_tag_t x86_bus_space_mem;
+extern bus_space_tag_t x86_bus_space_io;
+
+int _x86_memio_map(bus_space_tag_t t, bus_addr_t addr,
+ bus_size_t size, int flags, bus_space_handle_t *bshp);
+void _x86_memio_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t size, bus_addr_t *);
+
+#endif /* _X86_BUS_FUNCS_H_ */
--- /dev/null
+/* $NetBSD: bus_private.h,v 1.14 2011/09/01 15:10:31 christos Exp $ */
+/* NetBSD: bus.h,v 1.8 2005/03/09 19:04:46 matt Exp */
+
+/*-
+ * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(_X86_BUS_PRIVATE_H_)
+#define _X86_BUS_PRIVATE_H_
+
+/*
+ * Cookie used for bounce buffers. A pointer to one of these it stashed in
+ * the DMA map.
+ */
+struct x86_bus_dma_cookie {
+ int id_flags; /* flags; see below */
+
+ /*
+ * Information about the original buffer used during
+ * DMA map syncs. Note that origibuflen is only used
+ * for ID_BUFTYPE_LINEAR.
+ */
+ void *id_origbuf; /* pointer to orig buffer if
+ bouncing */
+ bus_size_t id_origbuflen; /* ...and size */
+ int id_buftype; /* type of buffer */
+
+ void *id_bouncebuf; /* pointer to the bounce buffer */
+ bus_size_t id_bouncebuflen; /* ...and size */
+ int id_nbouncesegs; /* number of valid bounce segs */
+ bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer
+ physical memory segments */
+};
+
+/* id_flags */
+#define X86_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */
+#define X86_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */
+#define X86_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */
+
+/* id_buftype */
+#define X86_DMA_BUFTYPE_INVALID 0
+#define X86_DMA_BUFTYPE_LINEAR 1
+#define X86_DMA_BUFTYPE_MBUF 2
+#define X86_DMA_BUFTYPE_UIO 3
+#define X86_DMA_BUFTYPE_RAW 4
+
+/*
+ * default address translation macros, which are appropriate where
+ * paddr_t == bus_addr_t.
+ */
+
+#if !defined(_BUS_PHYS_TO_BUS)
+#define _BUS_PHYS_TO_BUS(pa) ((bus_addr_t)(pa))
+#endif /* !defined(_BUS_PHYS_TO_BUS) */
+
+#if !defined(_BUS_BUS_TO_PHYS)
+#define _BUS_BUS_TO_PHYS(ba) ((paddr_t)(ba))
+#endif /* !defined(_BUS_BUS_TO_PHYS) */
+
+#if !defined(_BUS_VM_PAGE_TO_BUS)
+#define _BUS_VM_PAGE_TO_BUS(pg) _BUS_PHYS_TO_BUS(VM_PAGE_TO_PHYS(pg))
+#endif /* !defined(_BUS_VM_PAGE_TO_BUS) */
+
+#if !defined(_BUS_BUS_TO_VM_PAGE)
+#define _BUS_BUS_TO_VM_PAGE(ba) PHYS_TO_VM_PAGE(ba)
+#endif /* !defined(_BUS_BUS_TO_VM_PAGE) */
+
+#if !defined(_BUS_PMAP_ENTER)
+#define _BUS_PMAP_ENTER(pmap, va, ba, prot, flags) \
+ pmap_enter(pmap, va, ba, prot, flags)
+#endif /* _BUS_PMAP_ENTER */
+
+#if !defined(_BUS_VIRT_TO_BUS)
+#include <uvm/uvm.h>
+
+static __inline bus_addr_t _bus_virt_to_bus(struct pmap *, vaddr_t);
+#define _BUS_VIRT_TO_BUS(pm, va) _bus_virt_to_bus((pm), (va))
+
+static __inline bus_addr_t
+_bus_virt_to_bus(struct pmap *pm, vaddr_t va)
+{
+ paddr_t pa;
+
+ if (!pmap_extract(pm, va, &pa)) {
+ panic("_bus_virt_to_bus");
+ }
+
+ return _BUS_PHYS_TO_BUS(pa);
+}
+#endif /* !defined(_BUS_VIRT_TO_BUS) */
+
+/*
+ * by default, the end address of RAM visible on bus is the same as the
+ * largest physical address.
+ */
+#ifndef _BUS_AVAIL_END
+#define _BUS_AVAIL_END (avail_end)
+#endif
+
+struct x86_bus_dma_tag {
+ bus_dma_tag_t bdt_super;
+ /* bdt_present: bitmap indicating overrides present (1) in *this* tag,
+ * bdt_exists: bitmap indicating overrides present (1) in *this* tag
+ * or in an ancestor's tag (follow bdt_super to ancestors)
+ */
+ uint64_t bdt_present;
+ uint64_t bdt_exists;
+ const struct bus_dma_overrides *bdt_ov;
+ void *bdt_ctx;
+ /*
+ * The `bounce threshold' is checked while we are loading
+ * the DMA map. If the physical address of the segment
+ * exceeds the threshold, an error will be returned. The
+ * caller can then take whatever action is necessary to
+ * bounce the transfer. If this value is 0, it will be
+ * ignored.
+ */
+ int _tag_needs_free;
+ bus_addr_t _bounce_thresh;
+ bus_addr_t _bounce_alloc_lo;
+ bus_addr_t _bounce_alloc_hi;
+ int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *);
+};
+
+#endif /* !defined(_X86_BUS_PRIVATE_H_) */
--- /dev/null
+/* $NetBSD: busdefs.h,v 1.2 2008/04/28 20:23:40 martin Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_BUSDEFS_H_
+#define _X86_BUSDEFS_H_
+
+/*
+ * Values for the x86 bus space tag, not to be used directly by MI code.
+ */
+#define X86_BUS_SPACE_IO 0 /* space is i/o space */
+#define X86_BUS_SPACE_MEM 1 /* space is mem space */
+
+#define __BUS_SPACE_HAS_STREAM_METHODS 1
+
+#endif /* _X86_BUSDEFS_H_ */
--- /dev/null
+/* $NetBSD: cacheinfo.h,v 1.13 2011/12/04 17:00:10 chs Exp $ */
+
+#ifndef _X86_CACHEINFO_H_
+#define _X86_CACHEINFO_H_
+
+struct x86_cache_info {
+ uint8_t cai_index;
+ uint8_t cai_desc;
+ uint8_t cai_associativity;
+ u_int cai_totalsize; /* #entries for TLB, bytes for cache */
+ u_int cai_linesize; /* or page size for TLB */
+#ifndef _KERNEL
+ const char *cai_string;
+#endif
+};
+
+#define CAI_ITLB 0 /* Instruction TLB (4K pages) */
+#define CAI_ITLB2 1 /* Instruction TLB (2/4M pages) */
+#define CAI_DTLB 2 /* Data TLB (4K pages) */
+#define CAI_DTLB2 3 /* Data TLB (2/4M pages) */
+#define CAI_ICACHE 4 /* Instruction cache */
+#define CAI_DCACHE 5 /* Data cache */
+#define CAI_L2CACHE 6 /* Level 2 cache */
+#define CAI_L3CACHE 7 /* Level 3 cache */
+#define CAI_L1_1GBITLB 8 /* L1 1GB Page instruction TLB */
+#define CAI_L1_1GBDTLB 9 /* L1 1GB Page data TLB */
+#define CAI_L2_1GBITLB 10 /* L2 1GB Page instruction TLB */
+#define CAI_L2_1GBDTLB 11 /* L2 1GB Page data TLB */
+#define CAI_L2_ITLB 12 /* L2 Instruction TLB (4K pages) */
+#define CAI_L2_ITLB2 13 /* L2 Instruction TLB (2/4M pages) */
+#define CAI_L2_DTLB 14 /* L2 Data TLB (4K pages) */
+#define CAI_L2_DTLB2 15 /* L2 Data TLB (2/4M pages) */
+
+#define CAI_COUNT 16
+
+/*
+ * AMD Cache Info:
+ *
+ * Barcelona, Phenom:
+ *
+ * Function 8000.0005 L1 TLB/Cache Information
+ * EAX -- L1 TLB 2/4MB pages
+ * EBX -- L1 TLB 4K pages
+ * ECX -- L1 D-cache
+ * EDX -- L1 I-cache
+ *
+ * Function 8000.0006 L2 TLB/Cache Information
+ * EAX -- L2 TLB 2/4MB pages
+ * EBX -- L2 TLB 4K pages
+ * ECX -- L2 Unified cache
+ * EDX -- L3 Unified Cache
+ *
+ * Function 8000.0019 TLB 1GB Page Information
+ * EAX -- L1 1GB pages
+ * EBX -- L2 1GB pages
+ * ECX -- reserved
+ * EDX -- reserved
+ *
+ * Athlon, Duron:
+ *
+ * Function 8000.0005 L1 TLB/Cache Information
+ * EAX -- L1 TLB 2/4MB pages
+ * EBX -- L1 TLB 4K pages
+ * ECX -- L1 D-cache
+ * EDX -- L1 I-cache
+ *
+ * Function 8000.0006 L2 TLB/Cache Information
+ * EAX -- L2 TLB 2/4MB pages
+ * EBX -- L2 TLB 4K pages
+ * ECX -- L2 Unified cache
+ * EDX -- reserved
+ *
+ * K5, K6:
+ *
+ * Function 8000.0005 L1 TLB/Cache Information
+ * EAX -- reserved
+ * EBX -- TLB 4K pages
+ * ECX -- L1 D-cache
+ * EDX -- L1 I-cache
+ *
+ * K6-III:
+ *
+ * Function 8000.0006 L2 Cache Information
+ * EAX -- reserved
+ * EBX -- reserved
+ * ECX -- L2 Unified cache
+ * EDX -- reserved
+ */
+
+/* L1 TLB 2/4MB pages */
+#define AMD_L1_EAX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
+#define AMD_L1_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
+#define AMD_L1_EAX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
+#define AMD_L1_EAX_ITLB_ENTRIES(x) ( (x) & 0xff)
+
+/* L1 TLB 4K pages */
+#define AMD_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
+#define AMD_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
+#define AMD_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
+#define AMD_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff)
+
+/* L1 Data Cache */
+#define AMD_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
+#define AMD_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff)
+#define AMD_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff)
+#define AMD_L1_ECX_DC_LS(x) ( (x) & 0xff)
+
+/* L1 Instruction Cache */
+#define AMD_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
+#define AMD_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff)
+#define AMD_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff)
+#define AMD_L1_EDX_IC_LS(x) ( (x) & 0xff)
+
+/* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */
+
+/* L2 TLB 2/4MB pages */
+#define AMD_L2_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
+#define AMD_L2_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
+#define AMD_L2_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
+#define AMD_L2_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
+
+/* L2 TLB 4K pages */
+#define AMD_L2_EBX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
+#define AMD_L2_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
+#define AMD_L2_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
+#define AMD_L2_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
+
+/* L2 Cache */
+#define AMD_L2_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024)
+#define AMD_L2_ECX_C_ASSOC(x) (((x) >> 12) & 0xf)
+#define AMD_L2_ECX_C_LPT(x) (((x) >> 8) & 0xf)
+#define AMD_L2_ECX_C_LS(x) ( (x) & 0xff)
+
+/* L3 Cache */
+#define AMD_L3_EDX_C_SIZE(x) ((((x) >> 18) & 0xffff) * 1024 * 512)
+#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xff)
+#define AMD_L3_EDX_C_LPT(x) (((x) >> 8) & 0xf)
+#define AMD_L3_EDX_C_LS(x) ( (x) & 0xff)
+
+/* L1 TLB 1GB pages */
+#define AMD_L1_1GB_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
+#define AMD_L1_1GB_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
+#define AMD_L1_1GB_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
+#define AMD_L1_1GB_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
+
+/* L2 TLB 1GB pages */
+#define AMD_L2_1GB_EBX_DUTLB_ASSOC(x) (((x) >> 28) & 0xf)
+#define AMD_L2_1GB_EBX_DUTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
+#define AMD_L2_1GB_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
+#define AMD_L2_1GB_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
+
+/*
+ * VIA Cache Info:
+ *
+ * Nehemiah (at least)
+ *
+ * Function 8000.0005 L1 TLB/Cache Information
+ * EAX -- reserved
+ * EBX -- L1 TLB 4K pages
+ * ECX -- L1 D-cache
+ * EDX -- L1 I-cache
+ *
+ * Function 8000.0006 L2 Cache Information
+ * EAX -- reserved
+ * EBX -- reserved
+ * ECX -- L2 Unified cache
+ * EDX -- reserved
+ */
+
+/* L1 TLB 4K pages */
+#define VIA_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
+#define VIA_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
+#define VIA_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
+#define VIA_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff)
+
+/* L1 Data Cache */
+#define VIA_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
+#define VIA_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff)
+#define VIA_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff)
+#define VIA_L1_ECX_DC_LS(x) ( (x) & 0xff)
+
+/* L1 Instruction Cache */
+#define VIA_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
+#define VIA_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff)
+#define VIA_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff)
+#define VIA_L1_EDX_IC_LS(x) ( (x) & 0xff)
+
+/* L2 Cache (pre-Nehemiah) */
+#define VIA_L2_ECX_C_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
+#define VIA_L2_ECX_C_ASSOC(x) (((x) >> 16) & 0xff)
+#define VIA_L2_ECX_C_LPT(x) (((x) >> 8) & 0xff)
+#define VIA_L2_ECX_C_LS(x) ( (x) & 0xff)
+
+/* L2 Cache (Nehemiah and newer) */
+#define VIA_L2N_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024)
+#define VIA_L2N_ECX_C_ASSOC(x) (((x) >> 12) & 0xf)
+#define VIA_L2N_ECX_C_LPT(x) (((x) >> 8) & 0xf)
+#define VIA_L2N_ECX_C_LS(x) ( (x) & 0xff)
+
+#ifdef _KERNEL
+#define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e }
+#else
+#define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e, f }
+#endif
+
+/*
+ * XXX Currently organized mostly by cache type, but would be
+ * XXX easier to maintain if it were in descriptor type order.
+ */
+#define INTEL_CACHE_INFO { \
+__CI_TBL(CAI_ITLB, 0x01, 4, 32, 4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \
+__CI_TBL(CAI_ITLB2, 0x02, 0xff, 2, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0x03, 4, 64, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB2, 0x04, 4, 8, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_DTLB2, 0x05, 4, 32, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
+__CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
+__CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
+__CI_TBL(CAI_ITLB, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \
+__CI_TBL(CAI_DTLB2, 0x56, 4, 16, 4 * 1024 * 1024, NULL), \
+__CI_TBL(CAI_DTLB2, 0x57, 4, 16, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \
+__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
+__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
+__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
+__CI_TBL(CAI_ITLB, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \
+__CI_TBL(CAI_ITLB, 0xb2, 4, 64, 4 * 1024, NULL), \
+__CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \
+__CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \
+__CI_TBL(CAI_ICACHE, 0x09, 4, 32 * 1024, 64, NULL), \
+__CI_TBL(CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL), \
+__CI_TBL(CAI_DCACHE, 0x0a, 2, 8 * 1024, 32, NULL), \
+__CI_TBL(CAI_DCACHE, 0x0c, 4, 16 * 1024, 32, NULL), \
+__CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x21, 8, 256 * 1024, 64, NULL), /* L2 (MLC) */ \
+__CI_TBL(CAI_L2CACHE, 0x39, 4, 128 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x3a, 6, 192 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x3b, 2, 128 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x3c, 4, 256 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x3d, 6, 384 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x3e, 4, 512 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x40, 0, 0, 0, "not present"), \
+__CI_TBL(CAI_L2CACHE, 0x41, 4, 128 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x42, 4, 256 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x43, 4, 512 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x44, 4, 1 * 1024 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x45, 4, 2 * 1024 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x48, 12, 3 * 1024 * 1024, 64, NULL), \
+ \
+/* 0x49 Is L2 on Xeon MP (Family 0f, Model 06), L3 otherwise */ \
+__CI_TBL(CAI_L2CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x4e, 24, 6 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_DCACHE, 0x60, 8, 16 * 1024, 64, NULL), \
+__CI_TBL(CAI_DCACHE, 0x66, 4, 8 * 1024, 64, NULL), \
+__CI_TBL(CAI_DCACHE, 0x67, 4, 16 * 1024, 64, NULL), \
+__CI_TBL(CAI_DCACHE, 0x2c, 8, 32 * 1024, 64, NULL), \
+__CI_TBL(CAI_DCACHE, 0x68, 4, 32 * 1024, 64, NULL), \
+__CI_TBL(CAI_ICACHE, 0x70, 8, 12 * 1024, 64, "12K uOp cache"), \
+__CI_TBL(CAI_ICACHE, 0x71, 8, 16 * 1024, 64, "16K uOp cache"), \
+__CI_TBL(CAI_ICACHE, 0x72, 8, 32 * 1024, 64, "32K uOp cache"), \
+__CI_TBL(CAI_ICACHE, 0x73, 8, 64 * 1024, 64, "64K uOp cache"), \
+__CI_TBL(CAI_L2CACHE, 0x78, 4, 1 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x79, 8, 128 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x7a, 8, 256 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x7b, 8, 512 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x7c, 8, 1 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x7d, 8, 2 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x7f, 2, 512 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x82, 8, 256 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x83, 8, 512 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x84, 8, 1 * 1024 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x85, 8, 2 * 1024 * 1024, 32, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x86, 4, 512 * 1024, 64, NULL), \
+__CI_TBL(CAI_L2CACHE, 0x87, 8, 1 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x22, 0xff, 512 * 1024, 64, "sectored, 4-way "), \
+__CI_TBL(CAI_L3CACHE, 0x23, 0xff, 1 * 1024 * 1024, 64, "sectored, 8-way "), \
+__CI_TBL(CAI_L3CACHE, 0x25, 0xff, 2 * 1024 * 1024, 64, "sectored, 8-way "), \
+__CI_TBL(CAI_L3CACHE, 0x29, 0xff, 4 * 1024 * 1024, 64, "sectored, 8-way "), \
+__CI_TBL(CAI_L3CACHE, 0x46, 4, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x47, 8, 8 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x4a, 12, 6 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x4b, 16, 8 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x4c, 12,12 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0x4d, 16,16 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xd0, 4, 512 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xd1, 4, 1 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xd2, 4, 2 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xd6, 8, 1 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xd7, 8, 2 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xd8, 8, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xdc, 12, 3 * 512 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xdd, 12, 3 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xde, 12, 6 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xe2, 16, 2 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xe3, 16, 4 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xe4, 16, 8 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xea, 24,12 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xeb, 24,24 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \
+__CI_TBL(0, 0, 0, 0, 0, NULL) \
+}
+
+#define AMD_L2CACHE_INFO { \
+__CI_TBL(0, 0x01, 1, 0, 0, NULL), \
+__CI_TBL(0, 0x02, 2, 0, 0, NULL), \
+__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
+__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
+__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
+__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
+__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \
+__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
+__CI_TBL(0, 0x0d, 96, 0, 0, NULL), \
+__CI_TBL(0, 0x0e, 128, 0, 0, NULL), \
+__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
+__CI_TBL(0, 0x00, 0, 0, 0, NULL) \
+}
+
+#define AMD_L3CACHE_INFO { \
+__CI_TBL(0, 0x01, 1, 0, 0, NULL), \
+__CI_TBL(0, 0x02, 2, 0, 0, NULL), \
+__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
+__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
+__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
+__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
+__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \
+__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
+__CI_TBL(0, 0x0d, 96, 0, 0, NULL), \
+__CI_TBL(0, 0x0e, 128, 0, 0, NULL), \
+__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
+__CI_TBL(0, 0x00, 0, 0, 0, NULL) \
+}
+
+#endif /* _X86_CACHEINFO_H_ */
-/* $NetBSD: cpu.h,v 1.45 2011/12/30 17:57:49 cherry Exp $ */
+/* $NetBSD: cpu.h,v 1.52 2012/07/15 15:17:56 dsl Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
#ifdef XEN
#include <xen/xen-public/xen.h>
#include <xen/xen-public/event_channel.h>
+#include <sys/mutex.h>
#endif /* XEN */
struct intrsource;
int ci_fpsaving; /* save in progress */
int ci_fpused; /* XEN: FPU was used by curlwp */
cpuid_t ci_cpuid; /* our CPU ID */
- int ci_cpumask; /* (1 << CPU ID) */
+ int _unused;
uint32_t ci_acpiid; /* our ACPI/MADT ID */
uint32_t ci_initapicid; /* our intitial APIC ID */
#if defined(XEN) && (defined(PAE) || defined(__x86_64__))
/* Currently active user PGD (can't use rcr3() with Xen) */
pd_entry_t * ci_kpm_pdir; /* per-cpu PMD (va) */
- paddr_t ci_kpm_pdirpa; /* per-cpu PMD (pa) */
+ paddr_t ci_kpm_pdirpa; /* per-cpu PMD (pa) */
+ kmutex_t ci_kpm_mtx;
#if defined(__x86_64__)
+ /* per-cpu version of normal_pdes */
+ pd_entry_t * ci_normal_pdes[3]; /* Ok to hardcode. only for x86_64 && XEN */
paddr_t ci_xen_current_user_pgd;
#endif /* __x86_64__ */
#endif /* XEN et.al */
-
char *ci_doubleflt_stack;
char *ci_ddbipi_stack;
void cpu_boot_secondary_processors(void);
void cpu_init_idle_lwps(void);
void cpu_init_msrs(struct cpu_info *, bool);
-void cpu_load_pmap(struct pmap *);
+void cpu_load_pmap(struct pmap *, struct pmap *);
void cpu_broadcast_halt(void);
void cpu_kick(struct cpu_info *);
-extern uint32_t cpus_attached;
-
#define curcpu() x86_curcpu()
#define curlwp x86_curlwp()
#define curpcb ((struct pcb *)lwp_getpcb(curlwp))
extern int biosbasemem;
extern int biosextmem;
-extern int cpu;
+extern int cputype;
extern int cpuid_level;
extern int cpu_class;
extern char cpu_brand_string[];
void lgdt(struct region_descriptor *);
#ifdef XEN
void lgdt_finish(void);
-void i386_switch_context(lwp_t *);
#endif
struct pcb;
void savectx(struct pcb *);
void lwp_trampoline(void);
-void child_trampoline(void);
#ifdef XEN
void startrtclock(void);
void xen_delay(unsigned int);
void xen_initclocks(void);
-void xen_suspendclocks(void);
-void xen_resumeclocks(void);
+void xen_suspendclocks(struct cpu_info *);
+void xen_resumeclocks(struct cpu_info *);
#else
/* clock.c */
void initrtclock(u_long);
--- /dev/null
+/* $NetBSD: cpu_counter.h,v 1.5 2011/02/02 12:26:42 bouyer Exp $ */
+
+/*-
+ * Copyright (c) 2000, 2008 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Bill Sommerfeld.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_CPU_COUNTER_H_
+#define _X86_CPU_COUNTER_H_
+
+#ifdef _KERNEL
+
+uint64_t cpu_counter(void);
+uint64_t cpu_counter_serializing(void);
+uint32_t cpu_counter32(void);
+uint64_t cpu_frequency(struct cpu_info *);
+int cpu_hascounter(void);
+
+#endif /* _KERNEL */
+
+#endif /* !_X86_CPU_COUNTER_H_ */
--- /dev/null
+/* $NetBSD: cpu_msr.h,v 1.7 2009/10/05 23:59:31 rmind Exp $ */
+
+/*-
+ * Copyright (c) 2007 Juan Romero Pardines.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_CPU_MSR_H
+#define _X86_CPU_MSR_H
+
+#include <sys/param.h>
+#include <sys/types.h>
+
+#ifdef _KERNEL
+
+struct msr_rw_info {
+ int msr_read;
+ int msr_type;
+ uint64_t msr_value;
+ uint64_t msr_mask;
+};
+
+static inline void
+x86_msr_xcall(void *arg1, void *arg2)
+{
+ struct msr_rw_info *msrdat = arg1;
+ uint64_t msr = 0;
+
+ KASSERT(msrdat->msr_type != 0);
+
+ /* Read the MSR requested and apply the mask if defined. */
+ if (msrdat->msr_read) {
+ msr = rdmsr(msrdat->msr_type);
+ if (msrdat->msr_mask) {
+ msr &= ~msrdat->msr_mask;
+ }
+ }
+ /* Assign (or extract, on read) the value and perform the write. */
+ msr |= msrdat->msr_value;
+ wrmsr(msrdat->msr_type, msr);
+}
+
+#endif /* ! _KERNEL */
+#endif /* ! _X86_CPU_MSR_H */
--- /dev/null
+/* $NetBSD: cpu_ucode.h,v 1.2 2012/08/29 17:13:22 drochner Exp $ */
+/*
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Christoph Egger.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_CPU_UCODE_H_
+#define _X86_CPU_UCODE_H_
+
+#define CPU_UCODE_LOADER_AMD 0
+struct cpu_ucode_version_amd {
+ uint64_t version;
+};
+
+#define CPU_UCODE_LOADER_INTEL1 1
+struct cpu_ucode_version_intel1 {
+ uint32_t ucodeversion;
+ int platformid;
+};
+
+#ifdef _KERNEL
+#include <sys/cpu.h>
+#include <sys/cpuio.h>
+#include <dev/firmload.h>
+
+int cpu_ucode_amd_get_version(struct cpu_ucode_version *);
+/* XXX COMPAT */
+int compat6_cpu_ucode_amd_get_version(struct compat6_cpu_ucode *);
+int cpu_ucode_amd_firmware_open(firmware_handle_t *, const char *);
+int cpu_ucode_amd_apply(struct cpu_ucode_softc *, int);
+
+int cpu_ucode_intel_get_version(struct cpu_ucode_version *);
+int cpu_ucode_intel_firmware_open(firmware_handle_t *, const char *);
+int cpu_ucode_intel_apply(struct cpu_ucode_softc *, int);
+#endif /* _KERNEL */
+
+struct intel1_ucode_header {
+ uint32_t uh_header_ver;
+ uint32_t uh_rev;
+ uint32_t uh_date;
+ uint32_t uh_signature;
+ uint32_t uh_checksum;
+ uint32_t uh_loader_rev;
+ uint32_t uh_proc_flags;
+ uint32_t uh_data_size;
+ uint32_t uh_total_size;
+ uint32_t uh_reserved[3];
+};
+
+struct intel1_ucode_proc_signature {
+ uint32_t ups_signature;
+ uint32_t ups_proc_flags;
+ uint32_t ups_checksum;
+};
+
+struct intel1_ucode_ext_table {
+ uint32_t uet_count;
+ uint32_t uet_checksum;
+ uint32_t uet_reserved[3];
+ struct intel1_ucode_proc_signature uet_proc_sig[1];
+};
+
+#endif
--- /dev/null
+/* $NetBSD: cpufunc.h,v 1.13 2011/09/24 10:32:52 jym Exp $ */
+
+/*-
+ * Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum, and by Andrew Doran.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_CPUFUNC_H_
+#define _X86_CPUFUNC_H_
+
+/*
+ * Functions to provide access to x86-specific instructions.
+ */
+
+#include <sys/cdefs.h>
+#include <sys/types.h>
+
+#include <machine/segments.h>
+#include <machine/specialreg.h>
+
+#ifdef _KERNEL
+
+void x86_pause(void);
+void x86_lfence(void);
+void x86_sfence(void);
+void x86_mfence(void);
+void x86_flush(void);
+#ifndef XEN
+void x86_patch(bool);
+#endif
+void invlpg(vaddr_t);
+void lidt(struct region_descriptor *);
+void lldt(u_short);
+void ltr(u_short);
+void lcr0(u_long);
+u_long rcr0(void);
+void lcr2(vaddr_t);
+vaddr_t rcr2(void);
+void lcr3(vaddr_t);
+vaddr_t rcr3(void);
+void lcr4(vaddr_t);
+vaddr_t rcr4(void);
+void lcr8(vaddr_t);
+vaddr_t rcr8(void);
+void tlbflush(void);
+void tlbflushg(void);
+void dr0(void *, uint32_t, uint32_t, uint32_t);
+vaddr_t rdr6(void);
+void ldr6(vaddr_t);
+void wbinvd(void);
+void breakpoint(void);
+void x86_hlt(void);
+void x86_stihlt(void);
+u_int x86_getss(void);
+void fldcw(void *);
+void fnclex(void);
+void fninit(void);
+void fnsave(void *);
+void fnstcw(void *);
+void fnstsw(void *);
+void fp_divide_by_0(void);
+void frstor(void *);
+void fwait(void);
+void clts(void);
+void stts(void);
+void fldummy(const double *);
+void fxsave(void *);
+void fxrstor(void *);
+void x86_monitor(const void *, uint32_t, uint32_t);
+void x86_mwait(uint32_t, uint32_t);
+void x86_ldmxcsr(void *);
+#define x86_cpuid(a,b) x86_cpuid2((a),0,(b))
+void x86_cpuid2(unsigned, unsigned, unsigned *);
+
+/* Use read_psl, write_psl when saving and restoring interrupt state. */
+void x86_disable_intr(void);
+void x86_enable_intr(void);
+u_long x86_read_psl(void);
+void x86_write_psl(u_long);
+
+/* Use read_flags, write_flags to adjust other members of %eflags. */
+u_long x86_read_flags(void);
+void x86_write_flags(u_long);
+
+void x86_reset(void);
+
+/*
+ * Some of the undocumented AMD64 MSRs need a 'passcode' to access.
+ *
+ * See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
+ */
+
+#define OPTERON_MSR_PASSCODE 0x9c5a203aU
+
+uint64_t rdmsr(u_int);
+uint64_t rdmsr_locked(u_int, u_int);
+int rdmsr_safe(u_int, uint64_t *);
+uint64_t rdtsc(void);
+uint64_t rdpmc(u_int);
+void wrmsr(u_int, uint64_t);
+void wrmsr_locked(u_int, u_int, uint64_t);
+void setfs(int);
+void setusergs(int);
+
+#endif /* _KERNEL */
+
+#endif /* !_X86_CPUFUNC_H_ */
--- /dev/null
+/* $NetBSD: cputypes.h,v 1.3 2011/01/27 18:44:40 bouyer Exp $ */
+
+/*
+ * Copyright (c) 1993 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Classes of Processor. CPU identification code depends on
+ * this starting at 0, and having an increment of one.
+ */
+
+#define CPUCLASS_386 0
+#define CPUCLASS_486 1
+#define CPUCLASS_586 2
+#define CPUCLASS_686 3
+
+/*
+ * Kinds of Processor. Only the first 7 are used, as they are processors
+ * that might not have a cpuid instruction.
+ */
+
+#define CPU_386SX 0 /* Intel 80386SX */
+#define CPU_386 1 /* Intel 80386DX */
+#define CPU_486SX 2 /* Intel 80486SX */
+#define CPU_486 3 /* Intel 80486DX */
+#define CPU_486DLC 4 /* Cyrix 486DLC */
+#define CPU_6x86 5 /* Cyrix/IBM 6x86 */
+#define CPU_NX586 6 /* NexGen 586 */
+#define CPU_586 7 /* Intel P.....m (I hate lawyers; it's TM) */
+#define CPU_AM586 8 /* AMD Am486 and Am5x86 */
+#define CPU_K5 9 /* AMD K5 */
+#define CPU_K6 10 /* NexGen 686 aka AMD K6 */
+#define CPU_686 11 /* Intel Pentium Pro */
+#define CPU_C6 12 /* IDT WinChip C6 */
+#define CPU_TMX86 13 /* Transmeta TMx86 */
+
+/*
+ * CPU vendors
+ */
+
+#define CPUVENDOR_UNKNOWN 0
+#define CPUVENDOR_INTEL 1
+#define CPUVENDOR_CYRIX 2
+#define CPUVENDOR_NEXGEN 3
+#define CPUVENDOR_AMD 4
+#define CPUVENDOR_IDT 5
+#define CPUVENDOR_TRANSMETA 6
+#define CPUVENDOR_VORTEX86 7
+
+/*
+ * Some other defines, dealing with values returned by cpuid.
+ */
+
+#define CPU_MAXMODEL 15 /* Models within family range 0-15 */
+#define CPU_DEFMODEL 16 /* Value for unknown model -> default */
+#define CPU_MINFAMILY 4 /* Lowest that cpuid can return (486) */
+#define CPU_MAXFAMILY 7 /* Highest consecutive # we know (fake P4) */
+#define CPU_FAMILY_P4 15 /* Family number for Pentium 4 */
--- /dev/null
+/* $NetBSD: cpuvar.h,v 1.46 2012/04/20 22:23:24 rmind Exp $ */
+
+/*-
+ * Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1999 Stefan Grefen
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _X86_CPUVAR_H_
+#define _X86_CPUVAR_H_
+
+struct cpu_functions {
+#ifndef XEN
+ int (*start)(struct cpu_info *, paddr_t);
+#else /* XEN */
+ int (*start)(struct cpu_info *, vaddr_t);
+#endif /* XEN */
+ int (*stop)(struct cpu_info *);
+ void (*cleanup)(struct cpu_info *);
+};
+
+extern const struct cpu_functions mp_cpu_funcs;
+
+#define CPU_ROLE_SP 0
+#define CPU_ROLE_BP 1
+#define CPU_ROLE_AP 2
+
+struct cpu_attach_args {
+ int cpu_id;
+ int cpu_number;
+ int cpu_role;
+ const struct cpu_functions *cpu_func;
+};
+
+struct cpufeature_attach_args {
+ struct cpu_info *ci;
+ const char *name;
+};
+
+#ifdef _KERNEL
+#include <sys/kcpuset.h>
+#if defined(_KERNEL_OPT)
+#include "opt_multiprocessor.h"
+#endif /* defined(_KERNEL_OPT) */
+
+int x86_ipi(int, int, int);
+void x86_self_ipi(int);
+int x86_ipi_init(int);
+int x86_ipi_startup(int, int);
+void x86_errata(void);
+
+void identifycpu(struct cpu_info *);
+void identifycpu_cpuids(struct cpu_info *);
+void cpu_init(struct cpu_info *);
+void cpu_init_tss(struct cpu_info *);
+void cpu_init_first(void);
+
+void x86_cpu_idle_init(void);
+void x86_cpu_idle_halt(void);
+void x86_cpu_idle_mwait(void);
+#ifdef XEN
+void x86_cpu_idle_xen(void);
+#endif
+
+void cpu_get_tsc_freq(struct cpu_info *);
+void pat_init(struct cpu_info *);
+
+extern int cpu_vendor;
+extern bool x86_mp_online;
+
+extern uint32_t cpu_feature[5];
+
+#endif /* _KERNEL */
+
+#endif /* !_X86_CPUVAR_H_ */
--- /dev/null
+/* $NetBSD: db_machdep.h,v 1.3 2011/04/30 16:58:35 christos Exp $ */
+
+#ifndef _X86_DB_MACHDEP_H_
+#define _X86_DB_MACHDEP_H_
+
+#define INKERNEL(va) (((vaddr_t)(va)) >= VM_MIN_KERNEL_ADDRESS)
+
+#define NONE 0
+#define TRAP 1
+#define SYSCALL 2
+#define INTERRUPT 3
+#define INTERRUPT_TSS 4
+#define TRAP_TSS 5
+
+#define MAXNARG 16
+
+struct db_variable;
+
+#ifdef __x86_64__
+#define tf_sp tf_rsp
+#define tf_ip tf_rip
+#define tf_bp tf_rbp
+#define pcb_bp pcb_rbp
+#define pcb_sp pcb_rsp
+#define x86_frame x86_64_frame
+#else
+#define tf_sp tf_esp
+#define tf_ip tf_eip
+#define tf_bp tf_ebp
+#define pcb_bp pcb_ebp
+#define pcb_sp pcb_esp
+#define x86_frame i386_frame
+#endif
+
+int db_x86_regop(const struct db_variable *, db_expr_t *, int);
+int db_numargs(long *);
+int db_nextframe(long **, long **, long **, db_addr_t *, long *, int,
+ void (*) (const char *, ...));
+db_sym_t db_frame_info(long *, db_addr_t, const char **, db_expr_t *,
+ int *, int *);
+
+#endif /* _X86_DB_MACHDEP_H_ */
--- /dev/null
+/* $NetBSD: est.h,v 1.1 2011/02/23 11:43:22 jruoho Exp $ */
+
+/*
+ * Copyright (c) 2003 Michael Eriksson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_EST_H_
+#define _X86_EST_H_
+
+int via_get_bus_clock(struct cpu_info *);
+int viac7_get_bus_clock(struct cpu_info *);
+int p3_get_bus_clock(struct cpu_info *);
+int p4_get_bus_clock(struct cpu_info *);
+
+#endif /* !_X86_EST_H_ */
--- /dev/null
+/* $NetBSD: genfb_machdep.h,v 1.3 2011/02/09 13:24:23 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2009 Jared D. McNeill <jmcneill@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_GENFB_MACHDEP_H
+#define _X86_GENFB_MACHDEP_H
+
+int x86_genfb_cnattach(void);
+void x86_genfb_mtrr_init(uint64_t, uint32_t);
+void x86_genfb_set_console_dev(device_t);
+void x86_genfb_ddb_trap_callback(int);
+
+#endif /* !_X86_GENFB_MACHDEP_H */
--- /dev/null
+/* $NetBSD: i82093reg.h,v 1.3 2011/08/17 14:55:11 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Typically, the first apic lives here.
+ */
+#define IOAPIC_BASE_DEFAULT 0xfec00000
+
+#define IOAPIC_MSIADDR_BASE 0xfee00000
+#define IOAPIC_MSIADDR_DSTID_MASK __BITS(19, 12)
+#define IOAPIC_MSIADDR_RSVD0_MASK __BITS(11, 4)
+#define IOAPIC_MSIADDR_RH __BIT(3)
+#define IOAPIC_MSIADDR_DM __BIT(2)
+#define IOAPIC_MSIADDR_RSVD1_MASK __BITS(1, 0)
+
+#define IOAPIC_MSIDATA_VECTOR_MASK __BITS(7, 0)
+#define IOAPIC_MSIDATA_DM_MASK __BITS(10, 8)
+#define IOAPIC_MSIDATA_DM_FIXED __SHIFTIN(0, IOAPIC_MSIDATA_DM_MASK)
+#define IOAPIC_MSIDATA_DM_LOPRI __SHIFTIN(1, IOAPIC_MSIDATA_DM_MASK)
+#define IOAPIC_MSIDATA_DM_SMI __SHIFTIN(2, IOAPIC_MSIDATA_DM_MASK)
+#define IOAPIC_MSIDATA_DM_RSVD0 __SHIFTIN(3, IOAPIC_MSIDATA_DM_MASK)
+#define IOAPIC_MSIDATA_DM_NMI __SHIFTIN(4, IOAPIC_MSIDATA_DM_MASK)
+#define IOAPIC_MSIDATA_DM_INIT __SHIFTIN(5, IOAPIC_MSIDATA_DM_MASK)
+#define IOAPIC_MSIDATA_DM_RSVD1 __SHIFTIN(6, IOAPIC_MSIDATA_DM_MASK)
+#define IOAPIC_MSIDATA_DM_EXTINT __SHIFTIN(7, IOAPIC_MSIDATA_DM_MASK)
+#define IOAPIC_MSIDATA_RSVD0_MASK __BITS(13, 11)
+#define IOAPIC_MSIDATA_LEVEL_MASK __BIT(14)
+#define IOAPIC_MSIDATA_LEVEL_DEASSERT __SHIFTIN(0, IOAPIC_MSIDATA_LEVEL_MASK)
+#define IOAPIC_MSIDATA_LEVEL_ASSERT __SHIFTIN(1, IOAPIC_MSIDATA_LEVEL_MASK)
+#define IOAPIC_MSIDATA_TRGMODE_MASK __BIT(15)
+#define IOAPIC_MSIDATA_TRGMODE_EDGE \
+ __SHIFTIN(0, IOAPIC_MSIDATA_TRGMODE_MASK)
+#define IOAPIC_MSIDATA_TRGMODE_LEVEL \
+ __SHIFTIN(1, IOAPIC_MSIDATA_TRGMODE_MASK)
+#define IOAPIC_MSIDATA_RSVD1_MASK __BITS(31, 16)
+
+/*
+ * Memory-space registers.
+ */
+
+/*
+ * The externally visible registers are all 32 bits wide;
+ * store the register number of interest in IOAPIC_REG, and store/fetch
+ * the real value in IOAPIC_DATA.
+ */
+
+
+
+#define IOAPIC_REG 0x0000
+#define IOAPIC_DATA 0x0010
+
+/*
+ * Internal I/O APIC registers.
+ */
+
+#define IOAPIC_ID 0x00
+
+#define IOAPIC_ID_SHIFT 24
+#define IOAPIC_ID_MASK 0x0f000000
+
+/* Version, and maximum interrupt pin number. */
+
+#define IOAPIC_VER 0x01
+
+#define IOAPIC_VER_SHIFT 0
+#define IOAPIC_VER_MASK 0x000000ff
+
+#define IOAPIC_MAX_SHIFT 16
+#define IOAPIC_MAX_MASK 0x00ff0000
+
+/*
+ * Arbitration ID. Same format as IOAPIC_ID register.
+ */
+#define IOAPIC_ARB 0x02
+
+/*
+ * Redirection table registers.
+ */
+
+#define IOAPIC_REDHI(pin) (0x11 + ((pin)<<1))
+#define IOAPIC_REDLO(pin) (0x10 + ((pin)<<1))
+
+#define IOAPIC_REDHI_DEST_SHIFT 24 /* destination. */
+#define IOAPIC_REDHI_DEST_MASK 0xff000000
+
+#define IOAPIC_REDLO_MASK 0x00010000 /* 0=enabled; 1=masked */
+
+#define IOAPIC_REDLO_LEVEL 0x00008000 /* 0=edge, 1=level */
+#define IOAPIC_REDLO_RIRR 0x00004000 /* remote IRR; read only */
+#define IOAPIC_REDLO_ACTLO 0x00002000 /* 0=act. hi; 1=act. lo */
+#define IOAPIC_REDLO_DELSTS 0x00001000 /* 0=idle; 1=send pending */
+#define IOAPIC_REDLO_DSTMOD 0x00000800 /* 0=physical; 1=logical */
+
+#define IOAPIC_REDLO_DEL_MASK 0x00000700 /* del. mode mask */
+#define IOAPIC_REDLO_DEL_SHIFT 8
+
+#define IOAPIC_REDLO_DEL_FIXED 0
+#define IOAPIC_REDLO_DEL_LOPRI 1
+#define IOAPIC_REDLO_DEL_SMI 2
+#define IOAPIC_REDLO_DEL_NMI 4
+#define IOAPIC_REDLO_DEL_INIT 5
+#define IOAPIC_REDLO_DEL_EXTINT 7
+
+#define IOAPIC_REDLO_VECTOR_MASK 0x000000ff /* delivery vector */
+
+#define IMCR_ADDR 0x22
+#define IMCR_DATA 0x23
+
+#define IMCR_REGISTER 0x70
+#define IMCR_PIC 0x00
+#define IMCR_APIC 0x01
--- /dev/null
+/* $NetBSD: i82093var.h,v 1.12 2012/06/15 13:55:22 yamt Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_I82093VAR_H_
+#define _X86_I82093VAR_H_
+
+#include <sys/device.h>
+#include <machine/apicvar.h>
+
+struct ioapic_pin
+{
+ struct ioapic_pin *ip_next; /* next pin on this vector */
+ struct mp_intr_map *ip_map;
+ int ip_vector; /* IDT vector */
+ int ip_type;
+ struct cpu_info *ip_cpu; /* target CPU */
+};
+
+struct ioapic_softc {
+ device_t sc_dev;
+ struct pic sc_pic;
+ struct ioapic_softc *sc_next;
+ int sc_apicid;
+ int sc_apic_vers;
+ int sc_apic_vecbase; /* global int base if ACPI */
+ int sc_apic_sz; /* apic size*/
+ int sc_flags;
+ paddr_t sc_pa; /* PA of ioapic */
+ volatile uint32_t *sc_reg; /* KVA of ioapic addr */
+ volatile uint32_t *sc_data; /* KVA of ioapic data */
+ struct ioapic_pin *sc_pins; /* sc_apic_sz entries */
+};
+
+/*
+ * MP: intr_handle_t is bitfielded.
+ * ih&0xff -> legacy irq number.
+ * ih&0x10000000 -> if 0, old-style isa irq; if 1, routed via ioapic.
+ * (ih&0xff0000)>>16 -> ioapic id.
+ * (ih&0x00ff00)>>8 -> ioapic pin.
+ *
+ * 0x80000000 is used by pci_intr_machdep.c for MPSAFE_MASK
+ */
+
+#define APIC_INT_VIA_APIC 0x10000000
+#define APIC_INT_APIC_MASK 0x00ff0000
+#define APIC_INT_APIC_SHIFT 16
+#define APIC_INT_PIN_MASK 0x0000ff00
+#define APIC_INT_PIN_SHIFT 8
+
+#define APIC_IRQ_APIC(x) ((x & APIC_INT_APIC_MASK) >> APIC_INT_APIC_SHIFT)
+#define APIC_IRQ_PIN(x) ((x & APIC_INT_PIN_MASK) >> APIC_INT_PIN_SHIFT)
+#define APIC_IRQ_ISLEGACY(x) (!((x) & APIC_INT_VIA_APIC))
+#define APIC_IRQ_LEGACY_IRQ(x) ((x) & 0xff)
+
+void ioapic_print_redir(struct ioapic_softc *, const char *, int);
+void ioapic_format_redir(char *, const char *, int, uint32_t, uint32_t);
+struct ioapic_softc *ioapic_find(int);
+struct ioapic_softc *ioapic_find_bybase(int);
+
+void ioapic_enable(void);
+void ioapic_reenable(void);
+
+extern int nioapics;
+extern struct ioapic_softc *ioapics;
+
+#endif /* !_X86_I82093VAR_H_ */
--- /dev/null
+/* $NetBSD: i82489reg.h,v 1.11 2012/01/20 18:47:04 hannken Exp $ */
+
+/*-
+ * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Frank van der Linden.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*
+ * Registers and constants for the 82489DX and Pentium (and up) integrated
+ * "local" APIC.
+ */
+
+#define LAPIC_ID 0x020 /* ID. RW */
+# define LAPIC_ID_MASK 0xff000000
+# define LAPIC_ID_SHIFT 24
+
+#define LAPIC_VERS 0x030 /* Version. R */
+# define LAPIC_VERSION_MASK 0x000000ff
+# define LAPIC_VERSION_LVT_MASK 0x00ff0000
+# define LAPIC_VERSION_LVT_SHIFT 16
+
+#define LAPIC_TPRI 0x080 /* Task Prio. RW */
+# define LAPIC_TPRI_MASK 0x000000ff
+# define LAPIC_TPRI_INT_MASK 0x000000f0
+# define LAPIC_TPRI_SUB_MASK 0x0000000f
+
+#define LAPIC_APRI 0x090 /* Arbitration prio R */
+# define LAPIC_APRI_MASK 0x000000ff
+
+#define LAPIC_PPRI 0x0a0 /* Processor prio. R */
+#define LAPIC_EOI 0x0b0 /* End Int. W */
+#define LAPIC_RRR 0x0c0 /* Remote read R */
+#define LAPIC_LDR 0x0d0 /* Logical dest. RW */
+
+#define LAPIC_DFR 0x0e0 /* Dest. format RW */
+# define LAPIC_DFR_MASK 0xf0000000
+# define LAPIC_DFR_FLAT 0xf0000000
+# define LAPIC_DFR_CLUSTER 0x00000000
+
+#define LAPIC_SVR 0x0f0 /* Spurious intvec RW */
+# define LAPIC_SVR_VECTOR_MASK 0x000000ff
+# define LAPIC_SVR_VEC_FIX 0x0000000f
+# define LAPIC_SVR_VEC_PROG 0x000000f0
+# define LAPIC_SVR_ENABLE 0x00000100
+# define LAPIC_SVR_SWEN 0x00000100
+# define LAPIC_SVR_FOCUS 0x00000200
+# define LAPIC_SVR_FDIS 0x00000200
+
+#define LAPIC_ISR 0x100 /* In-Service Status */
+#define LAPIC_TMR 0x180 /* Trigger Mode */
+#define LAPIC_IRR 0x200 /* Interrupt Req */
+#define LAPIC_ESR 0x280 /* Err status. R */
+
+#define LAPIC_ICRLO 0x300 /* Int. cmd. RW */
+# define LAPIC_DLMODE_MASK 0x00000700
+# define LAPIC_DLMODE_FIXED 0x00000000
+# define LAPIC_DLMODE_LOW 0x00000100
+# define LAPIC_DLMODE_SMI 0x00000200
+# define LAPIC_DLMODE_NMI 0x00000400
+# define LAPIC_DLMODE_INIT 0x00000500
+# define LAPIC_DLMODE_STARTUP 0x00000600
+# define LAPIC_DLMODE_EXTINT 0x00000700
+
+# define LAPIC_DSTMODE_PHYS 0x00000000
+# define LAPIC_DSTMODE_LOG 0x00000800
+
+# define LAPIC_DLSTAT_BUSY 0x00001000
+# define LAPIC_DLSTAT_IDLE 0x00000000
+
+# define LAPIC_LEVEL_MASK 0x00004000
+# define LAPIC_LEVEL_ASSERT 0x00004000
+# define LAPIC_LEVEL_DEASSERT 0x00000000
+
+# define LAPIC_TRIGGER_MASK 0x00008000
+# define LAPIC_TRIGGER_EDGE 0x00000000
+# define LAPIC_TRIGGER_LEVEL 0x00008000
+
+# define LAPIC_DEST_MASK 0x000c0000
+# define LAPIC_DEST_DEFAULT 0x00000000
+# define LAPIC_DEST_SELF 0x00040000
+# define LAPIC_DEST_ALLINCL 0x00080000
+# define LAPIC_DEST_ALLEXCL 0x000c0000
+
+
+#define LAPIC_ICRHI 0x310 /* Int. cmd. RW */
+
+#define LAPIC_LVTT 0x320 /* Loc.vec.(timer) RW */
+# define LAPIC_LVTT_VEC_MASK 0x000000ff
+# define LAPIC_LVTT_DS 0x00001000
+# define LAPIC_LVTT_M 0x00010000
+# define LAPIC_LVTT_TM 0x00020000
+
+#define LAPIC_TMINT 0x330 /* Loc.vec (Thermal) */
+#define LAPIC_PCINT 0x340 /* Loc.vec (Perf Mon) */
+#define LAPIC_LVINT0 0x350 /* Loc.vec (LINT0) RW */
+# define LAPIC_LVT_MASKED 0x00010000
+# define LAPIC_LVT_LEVTRIG 0x00008000
+# define LAPIC_LVT_REMOTE_IRR 0x00004000
+# define LAPIC_INP_POL 0x00002000
+# define LAPIC_PEND_SEND 0x00001000
+
+#define LAPIC_LVINT1 0x360 /* Loc.vec (LINT1) RW */
+#define LAPIC_LVERR 0x370 /* Loc.vec (ERROR) RW */
+#define LAPIC_ICR_TIMER 0x380 /* Initial count RW */
+#define LAPIC_CCR_TIMER 0x390 /* Current count RO */
+
+#define LAPIC_DCR_TIMER 0x3e0 /* Divisor config register */
+# define LAPIC_DCRT_DIV1 0x0b
+# define LAPIC_DCRT_DIV2 0x00
+# define LAPIC_DCRT_DIV4 0x01
+# define LAPIC_DCRT_DIV8 0x02
+# define LAPIC_DCRT_DIV16 0x03
+# define LAPIC_DCRT_DIV32 0x08
+# define LAPIC_DCRT_DIV64 0x09
+# define LAPIC_DCRT_DIV128 0x0a
+
+#define LAPIC_BASE 0xfee00000
+
+#define LAPIC_IRQ_MASK(i) (1 << ((i) + 1))
+
+/* Extended APIC registers, valid when CPUID features4 EAPIC is present */
+#define LEAPIC_FR 0x400 /* Feature register */
+# define LEAPIC_FR_ELC __BITS(23,16) /* Ext. Lvt Count RO */
+# define LEAPIC_FR_EIDCAP __BIT(2) /* Ext. Apic ID Cap. RO */
+# define LEAPIC_FR_SEIOCAP __BIT(1) /* Specific EOI Cap. RO */
+# define LEAPIC_FR_IERCAP __BIT(0) /* Intr. Enable Reg. RO */
+
+#define LEAPIC_CR 0x410 /* Control Register */
+# define LEAPIC_CR_EID_ENABLE __BIT(2) /* Ext. Apic ID enable */
+# define LEAPIC_CR_SEOI_ENABLE __BIT(1) /* Specific EOI enable */
+# define LEAPIC_CR_IER_ENABLE __BIT(0) /* Enable writes to IER */
+
+#define LEAPIC_SEOIR 0x420 /* Specific EOI Register */
+# define LEAPIC_SEOI_VEC __BITS(7,0)
+
+#define LEAPIC_IER_480 0x480 /* Interrupts 0-31 */
+#define LEAPIC_IER_490 0x490 /* Interrupts 32-63 */
+#define LEAPIC_IER_4B0 0x4B0 /* Interrupts 64-95 */
+#define LEAPIC_IER_4C0 0x4C0 /* Interrupts 96-127 */
+#define LEAPIC_IER_4D0 0x4D0 /* Interrupts 128-159 */
+#define LEAPIC_IER_4E0 0x4E0 /* Interrupts 160-191 */
+#define LEAPIC_IER_4F0 0x4F0 /* Interrupts 192-255 */
+
+/* Extended Local Vector Table Entries */
+#define LEAPIC_LVTR_500 0x500
+#define LEAPIC_LVTR_504 0x504
+#define LEAPIC_LVTR_508 0x508
+#define LEAPIC_LVTR_50C 0x50C
+#define LEAPIC_LVTR_510 0x510
+#define LEAPIC_LVTR_514 0x514
+#define LEAPIC_LVTR_518 0x518
+#define LEAPIC_LVTR_51C 0x51C
+#define LEAPIC_LVTR_520 0x520
+#define LEAPIC_LVTR_524 0x524
+#define LEAPIC_LVTR_528 0x528
+#define LEAPIC_LVTR_52C 0x52C
+#define LEAPIC_LVTR_530 0x530
+# define LEAPIC_LVTR_MASK __BIT(16) /* interrupt masked RW */
+# define LEAPIC_LVTR_DSTAT __BIT(12) /* delivery state RO */
+# define LEAPIC_LVTR_MSGTYPE __BITS(10,8) /* Message type */
+# define LEAPIC_LVTR_VEC __BITS(7,0) /* the intr. vector */
+
+/*
+ * Model specific registers
+ */
+
+#define LAPIC_MSR 0x001b
+# define LAPIC_MSR_BSP 0x00000100 /* boot processor */
+# define LAPIC_MSR_ENABLE_x2 0x00000400 /* x2APIC mode */
+# define LAPIC_MSR_ENABLE 0x00000800 /* software enable */
+# define LAPIC_MSR_ADDR 0xfffff000 /* physical address */
+
--- /dev/null
+/* $NetBSD: i82489var.h,v 1.14 2011/06/12 03:35:50 rmind Exp $ */
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Frank van der Linden.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_I82489VAR_H_
+#define _X86_I82489VAR_H_
+
+/*
+ * Software definitions belonging to Local APIC driver.
+ */
+
+static __inline uint32_t i82489_readreg(int);
+static __inline void i82489_writereg(int, uint32_t);
+
+#ifdef _KERNEL
+extern volatile uint32_t local_apic[];
+extern volatile uint32_t lapic_tpr;
+#endif
+
+static __inline uint32_t
+i82489_readreg(int reg)
+{
+ return *((volatile uint32_t *)(((volatile uint8_t *)local_apic)
+ + reg));
+}
+
+static __inline void
+i82489_writereg(int reg, uint32_t val)
+{
+ *((volatile uint32_t *)(((volatile uint8_t *)local_apic) + reg)) = val;
+}
+
+#define lapic_cpu_number() (i82489_readreg(LAPIC_ID) >> LAPIC_ID_SHIFT)
+
+/*
+ * "spurious interrupt vector"; vector used by interrupt which was
+ * aborted because the CPU masked it after it happened but before it
+ * was delivered.. "Oh, sorry, i caught you at a bad time".
+ * Low-order 4 bits must be all ones.
+ */
+extern void Xintrspurious(void);
+#define LAPIC_SPURIOUS_VECTOR 0xef
+
+/*
+ * Vectors used for inter-processor interrupts.
+ */
+extern void Xintr_lapic_ipi(void);
+extern void Xrecurse_lapic_ipi(void);
+extern void Xresume_lapic_ipi(void);
+#define LAPIC_IPI_VECTOR 0xe0
+
+extern void Xintr_lapic_tlb(void);
+#define LAPIC_TLB_VECTOR 0xe1
+
+/*
+ * Vector used for local apic timer interrupts.
+ */
+
+extern void Xintr_lapic_ltimer(void);
+extern void Xresume_lapic_ltimer(void);
+extern void Xrecurse_lapic_ltimer(void);
+#define LAPIC_TIMER_VECTOR 0xc0
+
+/*
+ * 'pin numbers' for local APIC
+ */
+#define LAPIC_PIN_TIMER 0
+#define LAPIC_PIN_PCINT 2
+#define LAPIC_PIN_LVINT0 3
+#define LAPIC_PIN_LVINT1 4
+#define LAPIC_PIN_LVERR 5
+
+extern void Xintr_lapic0(void);
+extern void Xintr_lapic2(void);
+extern void Xintr_lapic3(void);
+extern void Xintr_lapic4(void);
+extern void Xintr_lapic5(void);
+
+
+struct cpu_info;
+
+extern void lapic_boot_init(paddr_t);
+extern void lapic_set_lvt(void);
+extern void lapic_enable(void);
+extern void lapic_calibrate_timer(struct cpu_info *ci);
+extern void lapic_initclocks(void);
+
+#endif
--- /dev/null
+/* $NetBSD: i8259.h,v 1.4 2003/08/07 16:30:32 agc Exp $ */
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)icu.h 5.6 (Berkeley) 5/9/91
+ */
+
+#ifndef _X86_I8259_H_
+#define _X86_I8259_H_
+
+#include <dev/isa/isareg.h>
+
+#ifndef _LOCORE
+
+/*
+ * Interrupt "level" mechanism variables, masks, and macros
+ */
+extern unsigned i8259_imen; /* interrupt mask enable */
+extern unsigned i8259_setmask(unsigned);
+
+#define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
+
+extern void i8259_default_setup(void);
+extern void i8259_reinit(void);
+
+#endif /* !_LOCORE */
+
+/*
+ * Interrupt enable bits -- in order of priority
+ */
+#define IRQ_SLAVE 2
+
+/*
+ * Interrupt Control offset into Interrupt descriptor table (IDT)
+ */
+#define ICU_OFFSET 32 /* 0-31 are processor exceptions */
+#define ICU_LEN 16 /* 32-47 are ISA interrupts */
+
+
+#define ICU_HARDWARE_MASK
+
+/*
+ * These macros are fairly self explanatory. If ICU_SPECIAL_MASK_MODE is
+ * defined, we try to take advantage of the ICU's `special mask mode' by only
+ * EOIing the interrupts on return. This avoids the requirement of masking and
+ * unmasking. We can't do this without special mask mode, because the ICU
+ * would also hold interrupts that it thinks are of lower priority.
+ *
+ * Many machines do not support special mask mode, so by default we don't try
+ * to use it.
+ */
+
+#define IRQ_BIT(num) (1 << ((num) % 8))
+#define IRQ_BYTE(num) ((num) >> 3)
+
+#define i8259_late_ack(num)
+
+#ifdef ICU_SPECIAL_MASK_MODE
+
+#define i8259_asm_ack1(num)
+#define i8259_asm_ack2(num) \
+ movb $(0x60|IRQ_SLAVE),%al /* specific EOI for IRQ2 */ ;\
+ outb %al,$IO_ICU1
+#define i8259_asm_mask(num)
+#define i8259_asm_unmask(num) \
+ movb $(0x60|(num%8)),%al /* specific EOI */ ;\
+ outb %al,$ICUADDR
+
+#else /* ICU_SPECIAL_MASK_MODE */
+
+#ifndef AUTO_EOI_1
+#define i8259_asm_ack1(num) \
+ movb $(0x60|(num%8)),%al /* specific EOI */ ;\
+ outb %al,$IO_ICU1
+#else
+#define i8259_asm_ack1(num)
+#endif
+
+#ifndef AUTO_EOI_2
+#define i8259_asm_ack2(num) \
+ movb $(0x60|(num%8)),%al /* specific EOI */ ;\
+ outb %al,$IO_ICU2 /* do the second ICU first */ ;\
+ movb $(0x60|IRQ_SLAVE),%al /* specific EOI for IRQ2 */ ;\
+ outb %al,$IO_ICU1
+#else
+#define i8259_asm_ack2(num)
+#endif
+
+#ifdef PIC_MASKDELAY
+#define MASKDELAY pushl %eax ; inb $0x84,%al ; popl %eax
+#else
+#define MASKDELAY
+#endif
+
+#ifdef ICU_HARDWARE_MASK
+
+#define i8259_asm_mask(num) \
+ movb CVAROFF(i8259_imen, IRQ_BYTE(num)),%al ;\
+ orb $IRQ_BIT(num),%al ;\
+ movb %al,CVAROFF(i8259_imen, IRQ_BYTE(num)) ;\
+ MASKDELAY ;\
+ outb %al,$(ICUADDR+1)
+#define i8259_asm_unmask(num) \
+ movb CVAROFF(i8259_imen, IRQ_BYTE(num)),%al ;\
+ andb $~IRQ_BIT(num),%al ;\
+ movb %al,CVAROFF(i8259_imen, IRQ_BYTE(num)) ;\
+ MASKDELAY ;\
+ outb %al,$(ICUADDR+1)
+
+#else /* ICU_HARDWARE_MASK */
+
+#define i8259_asm_mask(num)
+#define i8259_asm_unmask(num)
+
+#endif /* ICU_HARDWARE_MASK */
+#endif /* ICU_SPECIAL_MASK_MODE */
+
+#endif /* !_X86_I8259_H_ */
-/* $NetBSD: ieeefp.h,v 1.3 2010/07/31 21:47:54 joerg Exp $ */
+/* $NetBSD: ieeefp.h,v 1.4 2011/03/26 19:52:20 christos Exp $ */
/*
* Written by J.T. Conklin, Apr 6, 1995
#define FP_X_IMP FE_INEXACT /* imprecise (loss of precision) */
typedef enum {
- FP_RN=FE_TONEAREST, /* round to nearest representable number */
- FP_RM=FE_DOWNWARD, /* round toward negative infinity */
- FP_RP=FE_UPWARD, /* round toward positive infinity */
- FP_RZ=FE_TOWARDZERO /* round to zero (truncate) */
+ FP_RN=FE_TONEAREST, /* round to nearest representable num */
+ FP_RM=FE_DOWNWARD, /* round toward negative infinity */
+ FP_RP=FE_UPWARD, /* round toward positive infinity */
+ FP_RZ=FE_TOWARDZERO /* round to zero (truncate) */
} fp_rnd;
+typedef enum {
+ FP_PS = 0, /* 24 bit (single-precision) */
+ FP_PRS, /* reserved */
+ FP_PD, /* 53 bit (double-precision) */
+ FP_PE /* 64 bit (extended-precision) */
+} fp_prec;
+
+
#endif /* _X86_IEEEFP_H_ */
--- /dev/null
+/* $NetBSD: intr.h,v 1.43 2011/08/01 10:42:23 drochner Exp $ */
+
+/*-
+ * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum, and by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_INTR_H_
+#define _X86_INTR_H_
+
+#define __HAVE_FAST_SOFTINTS
+#define __HAVE_PREEMPTION
+
+#ifdef _KERNEL
+#include <sys/types.h>
+#else
+#include <stdbool.h>
+#endif
+
+#include <sys/evcnt.h>
+#include <machine/intrdefs.h>
+
+#ifndef _LOCORE
+#include <machine/pic.h>
+
+/*
+ * Struct describing an interrupt source for a CPU. struct cpu_info
+ * has an array of MAX_INTR_SOURCES of these. The index in the array
+ * is equal to the stub number of the stubcode as present in vector.s
+ *
+ * The primary CPU's array of interrupt sources has its first 16
+ * entries reserved for legacy ISA irq handlers. This means that
+ * they have a 1:1 mapping for arrayindex:irq_num. This is not
+ * true for interrupts that come in through IO APICs, to find
+ * their source, go through ci->ci_isources[index].is_pic
+ *
+ * It's possible to always maintain a 1:1 mapping, but that means
+ * limiting the total number of interrupt sources to MAX_INTR_SOURCES
+ * (32), instead of 32 per CPU. It also would mean that having multiple
+ * IO APICs which deliver interrupts from an equal pin number would
+ * overlap if they were to be sent to the same CPU.
+ */
+
+struct intrstub {
+ void *ist_entry;
+ void *ist_recurse;
+ void *ist_resume;
+};
+
+struct intrsource {
+ int is_maxlevel; /* max. IPL for this source */
+ int is_pin; /* IRQ for legacy; pin for IO APIC,
+ -1 for MSI */
+ struct intrhand *is_handlers; /* handler chain */
+ struct pic *is_pic; /* originating PIC */
+ void *is_recurse; /* entry for spllower */
+ void *is_resume; /* entry for doreti */
+ lwp_t *is_lwp; /* for soft interrupts */
+ struct evcnt is_evcnt; /* interrupt counter */
+ int is_flags; /* see below */
+ int is_type; /* level, edge */
+ int is_idtvec;
+ int is_minlevel;
+ char is_evname[32]; /* event counter name */
+};
+
+#define IS_LEGACY 0x0001 /* legacy ISA irq source */
+#define IS_IPI 0x0002
+#define IS_LOG 0x0004
+
+/*
+ * Interrupt handler chains. *_intr_establish() insert a handler into
+ * the list. The handler is called with its (single) argument.
+ */
+
+struct intrhand {
+ int (*ih_fun)(void *);
+ void *ih_arg;
+ int ih_level;
+ int (*ih_realfun)(void *);
+ void *ih_realarg;
+ struct intrhand *ih_next;
+ struct intrhand **ih_prevp;
+ int ih_pin;
+ int ih_slot;
+ struct cpu_info *ih_cpu;
+};
+
+#define IMASK(ci,level) (ci)->ci_imask[(level)]
+#define IUNMASK(ci,level) (ci)->ci_iunmask[(level)]
+
+#ifdef _KERNEL
+
+void Xspllower(int);
+void spllower(int);
+int splraise(int);
+void softintr(int);
+
+/*
+ * Convert spl level to local APIC level
+ */
+
+#define APIC_LEVEL(l) ((l) << 4)
+
+/*
+ * Miscellaneous
+ */
+
+#define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x))
+#define spl0() spllower(IPL_NONE)
+#define splx(x) spllower(x)
+
+typedef uint8_t ipl_t;
+typedef struct {
+ ipl_t _ipl;
+} ipl_cookie_t;
+
+static inline ipl_cookie_t
+makeiplcookie(ipl_t ipl)
+{
+
+ return (ipl_cookie_t){._ipl = ipl};
+}
+
+static inline int
+splraiseipl(ipl_cookie_t icookie)
+{
+
+ return splraise(icookie._ipl);
+}
+
+#include <sys/spl.h>
+
+/*
+ * Stub declarations.
+ */
+
+void Xsoftintr(void);
+void Xpreemptrecurse(void);
+void Xpreemptresume(void);
+
+extern struct intrstub i8259_stubs[];
+extern struct intrstub ioapic_edge_stubs[];
+extern struct intrstub ioapic_level_stubs[];
+
+struct cpu_info;
+
+struct pcibus_attach_args;
+
+void intr_default_setup(void);
+void x86_nmi(void);
+void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *, bool);
+void intr_disestablish(struct intrhand *);
+void intr_add_pcibus(struct pcibus_attach_args *);
+const char *intr_string(int);
+void cpu_intr_init(struct cpu_info *);
+int intr_find_mpmapping(int, int, int *);
+struct pic *intr_findpic(int);
+void intr_printconfig(void);
+
+int x86_send_ipi(struct cpu_info *, int);
+void x86_broadcast_ipi(int);
+void x86_ipi_handler(void);
+
+extern void (*ipifunc[X86_NIPI])(struct cpu_info *);
+
+#endif /* _KERNEL */
+
+#endif /* !_LOCORE */
+
+#endif /* !_X86_INTR_H_ */
--- /dev/null
+/* $NetBSD: intrdefs.h,v 1.17 2011/11/06 11:40:47 cherry Exp $ */
+
+#ifndef _X86_INTRDEFS_H_
+#define _X86_INTRDEFS_H_
+
+/* Interrupt priority levels. */
+#define IPL_NONE 0x0 /* nothing */
+#define IPL_PREEMPT 0x1 /* fake, to prevent recursive preemptions */
+#define IPL_SOFTCLOCK 0x2 /* timeouts */
+#define IPL_SOFTBIO 0x3 /* block I/O passdown */
+#define IPL_SOFTNET 0x4 /* protocol stacks */
+#define IPL_SOFTSERIAL 0x5 /* serial passdown */
+#define IPL_VM 0x6 /* low I/O, memory allocation */
+#define IPL_SCHED 0x7 /* medium I/O, scheduler, clock */
+#define IPL_HIGH 0x8 /* high I/O, statclock, IPIs */
+#define NIPL 9
+
+/* Interrupt sharing types. */
+#define IST_NONE 0 /* none */
+#define IST_PULSE 1 /* pulsed */
+#define IST_EDGE 2 /* edge-triggered */
+#define IST_LEVEL 3 /* level-triggered */
+
+/*
+ * Local APIC masks and software interrupt masks, in order
+ * of priority. Must not conflict with SIR_* below.
+ */
+#define LIR_IPI 31
+#define LIR_TIMER 30
+
+/*
+ * XXX These should be lowest numbered, but right now would
+ * conflict with the legacy IRQs. Their current position
+ * means that soft interrupt take priority over hardware
+ * interrupts when lowering the priority level!
+ */
+#define SIR_SERIAL 29
+#define SIR_NET 28
+#define SIR_BIO 27
+#define SIR_CLOCK 26
+#define SIR_PREEMPT 25
+
+/*
+ * Maximum # of interrupt sources per CPU. 32 to fit in one word.
+ * ioapics can theoretically produce more, but it's not likely to
+ * happen. For multiple ioapics, things can be routed to different
+ * CPUs.
+ */
+#define MAX_INTR_SOURCES 32
+#define NUM_LEGACY_IRQS 16
+
+/*
+ * Low and high boundaries between which interrupt gates will
+ * be allocated in the IDT.
+ */
+#define IDT_INTR_LOW (0x20 + NUM_LEGACY_IRQS)
+#define IDT_INTR_HIGH 0xef
+
+#ifndef XEN
+
+#define X86_IPI_HALT 0x00000001
+#define X86_IPI_MICROSET 0x00000002
+#define X86_IPI__UNUSED1 0x00000004
+#define X86_IPI_SYNCH_FPU 0x00000008
+#define X86_IPI_MTRR 0x00000010
+#define X86_IPI_GDT 0x00000020
+#define X86_IPI_XCALL 0x00000040
+#define X86_IPI_ACPI_CPU_SLEEP 0x00000080
+#define X86_IPI_KPREEMPT 0x00000100
+
+#define X86_NIPI 9
+
+#define X86_IPI_NAMES { "halt IPI", "timeset IPI", "unused", \
+ "FPU synch IPI", "MTRR update IPI", \
+ "GDT update IPI", "xcall IPI", \
+ "ACPI CPU sleep IPI", "kpreempt IPI" }
+#endif /* XEN */
+
+#define IREENT_MAGIC 0x18041969
+
+#endif /* _X86_INTRDEFS_H_ */
--- /dev/null
+/* $NetBSD: ipmivar.h,v 1.11 2010/08/01 08:16:14 mlelstv Exp $ */
+
+/*
+ * Copyright (c) 2005 Jordan Hargrave
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+
+#include <dev/sysmon/sysmonvar.h>
+
+#ifndef _IPMIVAR_H_
+#define _IPMIVAR_H_
+
+#define IPMI_IF_KCS 1
+#define IPMI_IF_SMIC 2
+#define IPMI_IF_BT 3
+
+#define IPMI_IF_KCS_NREGS 2
+#define IPMI_IF_SMIC_NREGS 3
+#define IPMI_IF_BT_NREGS 3
+
+struct ipmi_thread;
+struct ipmi_softc;
+
+struct ipmi_attach_args {
+ bus_space_tag_t iaa_iot;
+ bus_space_tag_t iaa_memt;
+
+ int iaa_if_type;
+ int iaa_if_rev;
+ int iaa_if_iotype;
+ int iaa_if_iobase;
+ int iaa_if_iospacing;
+ int iaa_if_irq;
+ int iaa_if_irqlvl;
+};
+
+struct ipmi_if {
+ const char *name;
+ int nregs;
+ void *(*buildmsg)(struct ipmi_softc *, int, int, int,
+ const void *, int *);
+ int (*sendmsg)(struct ipmi_softc *, int, const uint8_t *);
+ int (*recvmsg)(struct ipmi_softc *, int, int *, uint8_t *);
+ int (*reset)(struct ipmi_softc *);
+ int (*probe)(struct ipmi_softc *);
+};
+
+struct ipmi_softc {
+ device_t sc_dev;
+
+ struct ipmi_if *sc_if; /* Interface layer */
+ int sc_if_iospacing; /* Spacing of I/O ports */
+ int sc_if_rev; /* IPMI Revision */
+ struct ipmi_attach_args sc_ia;
+
+ void *sc_ih; /* Interrupt/IO handles */
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+
+ int sc_btseq;
+
+ struct lwp *sc_kthread;
+
+ int sc_max_retries;
+
+ kmutex_t sc_poll_mtx;
+ kcondvar_t sc_poll_cv;
+
+ kmutex_t sc_cmd_mtx;
+ kmutex_t sc_sleep_mtx;
+ kcondvar_t sc_cmd_sleep;
+
+ struct ipmi_bmc_args *sc_iowait_args;
+
+ struct ipmi_sensor *current_sensor;
+ volatile bool sc_thread_running;
+ volatile bool sc_tickle_due;
+ struct sysmon_wdog sc_wdog;
+ struct sysmon_envsys *sc_envsys;
+ envsys_data_t *sc_sensor;
+ int sc_nsensors; /* total number of sensors */
+
+ char sc_buf[64];
+ bool sc_buf_rsvd;
+};
+
+struct ipmi_thread {
+ struct ipmi_softc *sc;
+ volatile int running;
+};
+
+#define IPMI_WDOG_USE_NOLOG __BIT(7)
+#define IPMI_WDOG_USE_NOSTOP __BIT(6)
+#define IPMI_WDOG_USE_RSVD1 __BITS(5, 3)
+#define IPMI_WDOG_USE_USE_MASK __BITS(2, 0)
+#define IPMI_WDOG_USE_USE_RSVD __SHIFTIN(0, IPMI_WDOG_USE_USE_MASK);
+#define IPMI_WDOG_USE_USE_FRB2 __SHIFTIN(1, IPMI_WDOG_USE_USE_MASK);
+#define IPMI_WDOG_USE_USE_POST __SHIFTIN(2, IPMI_WDOG_USE_USE_MASK);
+#define IPMI_WDOG_USE_USE_OSLOAD __SHIFTIN(3, IPMI_WDOG_USE_USE_MASK);
+#define IPMI_WDOG_USE_USE_OS __SHIFTIN(4, IPMI_WDOG_USE_USE_MASK);
+#define IPMI_WDOG_USE_USE_OEM __SHIFTIN(5, IPMI_WDOG_USE_USE_MASK);
+
+#define IPMI_WDOG_ACT_PRE_RSVD1 __BIT(7)
+#define IPMI_WDOG_ACT_PRE_MASK __BITS(6, 4)
+#define IPMI_WDOG_ACT_PRE_DISABLED __SHIFTIN(0, IPMI_WDOG_ACT_MASK)
+#define IPMI_WDOG_ACT_PRE_SMI __SHIFTIN(1, IPMI_WDOG_ACT_MASK)
+#define IPMI_WDOG_ACT_PRE_NMI __SHIFTIN(2, IPMI_WDOG_ACT_MASK)
+#define IPMI_WDOG_ACT_PRE_INTERRUPT __SHIFTIN(3, IPMI_WDOG_ACT_MASK)
+#define IPMI_WDOG_ACT_PRE_RSVD0 __BIT(3)
+#define IPMI_WDOG_ACT_MASK __BITS(2, 0)
+#define IPMI_WDOG_ACT_DISABLED __SHIFTIN(0, IPMI_WDOG_ACT_MASK)
+#define IPMI_WDOG_ACT_RESET __SHIFTIN(1, IPMI_WDOG_ACT_MASK)
+#define IPMI_WDOG_ACT_PWROFF __SHIFTIN(2, IPMI_WDOG_ACT_MASK)
+#define IPMI_WDOG_ACT_PWRCYCLE __SHIFTIN(3, IPMI_WDOG_ACT_MASK)
+
+#define IPMI_WDOG_FLAGS_RSVD1 __BITS(7, 6)
+#define IPMI_WDOG_FLAGS_OEM __BIT(5)
+#define IPMI_WDOG_FLAGS_OS __BIT(4)
+#define IPMI_WDOG_FLAGS_OSLOAD __BIT(3)
+#define IPMI_WDOG_FLAGS_POST __BIT(2)
+#define IPMI_WDOG_FLAGS_FRB2 __BIT(1)
+#define IPMI_WDOG_FLAGS_RSVD0 __BIT(0)
+
+struct ipmi_set_watchdog {
+ uint8_t wdog_use;
+ uint8_t wdog_action;
+ uint8_t wdog_pretimeout;
+ uint8_t wdog_flags;
+ uint16_t wdog_timeout;
+} __packed;
+
+struct ipmi_get_watchdog {
+ uint8_t wdog_use;
+ uint8_t wdog_action;
+ uint8_t wdog_pretimeout;
+ uint8_t wdog_flags;
+ uint16_t wdog_timeout;
+ uint16_t wdog_countdown;
+} __packed;
+
+void ipmi_poll_thread(void *);
+
+int kcs_probe(struct ipmi_softc *);
+int kcs_reset(struct ipmi_softc *);
+int kcs_sendmsg(struct ipmi_softc *, int, const uint8_t *);
+int kcs_recvmsg(struct ipmi_softc *, int, int *len, uint8_t *);
+
+int bt_probe(struct ipmi_softc *);
+int bt_reset(struct ipmi_softc *);
+int bt_sendmsg(struct ipmi_softc *, int, const uint8_t *);
+int bt_recvmsg(struct ipmi_softc *, int, int *, uint8_t *);
+
+int smic_probe(struct ipmi_softc *);
+int smic_reset(struct ipmi_softc *);
+int smic_sendmsg(struct ipmi_softc *, int, const uint8_t *);
+int smic_recvmsg(struct ipmi_softc *, int, int *, uint8_t *);
+
+struct dmd_ipmi {
+ uint8_t dmd_sig[4]; /* Signature 'IPMI' */
+ uint8_t dmd_i2c_address; /* Address of BMC */
+ uint8_t dmd_nvram_address; /* Address of NVRAM */
+ uint8_t dmd_if_type; /* IPMI Interface Type */
+ uint8_t dmd_if_rev; /* IPMI Interface Revision */
+} __packed;
+
+
+#define APP_NETFN 0x06
+#define APP_GET_DEVICE_ID 0x01
+#define APP_RESET_WATCHDOG 0x22
+#define APP_SET_WATCHDOG_TIMER 0x24
+#define APP_GET_WATCHDOG_TIMER 0x25
+
+#define TRANSPORT_NETFN 0xC
+#define BRIDGE_NETFN 0x2
+
+#define STORAGE_NETFN 0x0A
+#define STORAGE_GET_FRU_INV_AREA 0x10
+#define STORAGE_READ_FRU_DATA 0x11
+#define STORAGE_RESERVE_SDR 0x22
+#define STORAGE_GET_SDR 0x23
+#define STORAGE_ADD_SDR 0x24
+#define STORAGE_ADD_PARTIAL_SDR 0x25
+#define STORAGE_DELETE_SDR 0x26
+#define STORAGE_RESERVE_SEL 0x42
+#define STORAGE_GET_SEL 0x43
+#define STORAGE_ADD_SEL 0x44
+#define STORAGE_ADD_PARTIAL_SEL 0x45
+#define STORAGE_DELETE_SEL 0x46
+
+#define SE_NETFN 0x04
+#define SE_GET_SDR_INFO 0x20
+#define SE_GET_SDR 0x21
+#define SE_RESERVE_SDR 0x22
+#define SE_GET_SENSOR_FACTOR 0x23
+#define SE_SET_SENSOR_HYSTERESIS 0x24
+#define SE_GET_SENSOR_HYSTERESIS 0x25
+#define SE_SET_SENSOR_THRESHOLD 0x26
+#define SE_GET_SENSOR_THRESHOLD 0x27
+#define SE_SET_SENSOR_EVENT_ENABLE 0x28
+#define SE_GET_SENSOR_EVENT_ENABLE 0x29
+#define SE_REARM_SENSOR_EVENTS 0x2A
+#define SE_GET_SENSOR_EVENT_STATUS 0x2B
+#define SE_GET_SENSOR_READING 0x2D
+#define SE_SET_SENSOR_TYPE 0x2E
+#define SE_GET_SENSOR_TYPE 0x2F
+
+struct sdrhdr {
+ uint16_t record_id; /* SDR Record ID */
+ uint8_t sdr_version; /* SDR Version */
+ uint8_t record_type; /* SDR Record Type */
+ uint8_t record_length; /* SDR Record Length */
+} __packed;
+
+/* SDR: Record Type 1 */
+struct sdrtype1 {
+ struct sdrhdr sdrhdr;
+
+ uint8_t owner_id;
+ uint8_t owner_lun;
+ uint8_t sensor_num;
+
+ uint8_t entity_id;
+ uint8_t entity_instance;
+ uint8_t sensor_init;
+ uint8_t sensor_caps;
+ uint8_t sensor_type;
+ uint8_t event_code;
+ uint16_t trigger_mask;
+ uint16_t reading_mask;
+ uint16_t settable_mask;
+ uint8_t units1;
+ uint8_t units2;
+ uint8_t units3;
+ uint8_t linear;
+ uint8_t m;
+ uint8_t m_tolerance;
+ uint8_t b;
+ uint8_t b_accuracy;
+ uint8_t accuracyexp;
+ uint8_t rbexp;
+ uint8_t analogchars;
+ uint8_t nominalreading;
+ uint8_t normalmax;
+ uint8_t normalmin;
+ uint8_t sensormax;
+ uint8_t sensormin;
+ uint8_t uppernr;
+ uint8_t upperc;
+ uint8_t uppernc;
+ uint8_t lowernr;
+ uint8_t lowerc;
+ uint8_t lowernc;
+ uint8_t physt;
+ uint8_t nhyst;
+ uint8_t resvd[2];
+ uint8_t oem;
+ uint8_t typelen;
+ uint8_t name[1];
+} __packed;
+
+/* SDR: Record Type 2 */
+struct sdrtype2 {
+ struct sdrhdr sdrhdr;
+
+ uint8_t owner_id;
+ uint8_t owner_lun;
+ uint8_t sensor_num;
+
+ uint8_t entity_id;
+ uint8_t entity_instance;
+ uint8_t sensor_init;
+ uint8_t sensor_caps;
+ uint8_t sensor_type;
+ uint8_t event_code;
+ uint16_t trigger_mask;
+ uint16_t reading_mask;
+ uint16_t set_mask;
+ uint8_t units1;
+ uint8_t units2;
+ uint8_t units3;
+ uint8_t share1;
+ uint8_t share2;
+ uint8_t physt;
+ uint8_t nhyst;
+ uint8_t resvd[3];
+ uint8_t oem;
+ uint8_t typelen;
+ uint8_t name[1];
+} __packed;
+
+int ipmi_probe(struct ipmi_attach_args *);
+
+#endif /* _IPMIVAR_H_ */
--- /dev/null
+/* $NetBSD: isa_machdep.h,v 1.11 2011/07/01 18:22:39 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)isa.h 5.7 (Berkeley) 5/9/91
+ */
+
+/*
+ * Various pieces of the i386 port want to include this file without
+ * or in spite of using isavar.h, and should be fixed.
+ */
+
+#ifndef _X86_ISA_MACHDEP_H_ /* XXX */
+#define _X86_ISA_MACHDEP_H_ /* XXX */
+
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <dev/isa/isadmavar.h>
+
+/*
+ * XXX THIS FILE IS A MESS. copyright: berkeley's probably.
+ * contents from isavar.h and isareg.h, mostly the latter.
+ * perhaps charles's?
+ *
+ * copyright from berkeley's isa.h which is now dev/isa/isareg.h.
+ */
+
+/*
+ * Types provided to machine-independent ISA code.
+ */
+struct x86_isa_chipset {
+ struct isa_dma_state ic_dmastate;
+};
+
+typedef struct x86_isa_chipset *isa_chipset_tag_t;
+
+struct isabus_attach_args; /* XXX */
+
+/*
+ * Functions provided to machine-independent ISA code.
+ */
+void isa_attach_hook(device_t, device_t,
+ struct isabus_attach_args *);
+void isa_detach_hook(isa_chipset_tag_t, device_t);
+int isa_intr_alloc(isa_chipset_tag_t, int, int, int *);
+const struct evcnt *isa_intr_evcnt(isa_chipset_tag_t ic, int irq);
+void *isa_intr_establish(isa_chipset_tag_t ic, int irq, int type,
+ int level, int (*ih_fun)(void *), void *ih_arg);
+void isa_intr_disestablish(isa_chipset_tag_t ic, void *handler);
+int isa_mem_alloc(bus_space_tag_t, bus_size_t, bus_size_t,
+ bus_addr_t, int, bus_addr_t *, bus_space_handle_t *);
+void isa_mem_free(bus_space_tag_t, bus_space_handle_t, bus_size_t);
+
+#define isa_dmadestroy(ic) \
+ _isa_dmadestroy(&(ic)->ic_dmastate)
+#define isa_dmainit(ic, bst, dmat, d) \
+ _isa_dmainit(&(ic)->ic_dmastate, (bst), (dmat), (d))
+#define isa_dmacascade(ic, c) \
+ _isa_dmacascade(&(ic)->ic_dmastate, (c))
+#define isa_dmamaxsize(ic, c) \
+ _isa_dmamaxsize(&(ic)->ic_dmastate, (c))
+#define isa_dmamap_create(ic, c, s, f) \
+ _isa_dmamap_create(&(ic)->ic_dmastate, (c), (s), (f))
+#define isa_dmamap_destroy(ic, c) \
+ _isa_dmamap_destroy(&(ic)->ic_dmastate, (c))
+#define isa_dmastart(ic, c, a, n, p, f, bf) \
+ _isa_dmastart(&(ic)->ic_dmastate, (c), (a), (n), (p), (f), (bf))
+#define isa_dmaabort(ic, c) \
+ _isa_dmaabort(&(ic)->ic_dmastate, (c))
+#define isa_dmacount(ic, c) \
+ _isa_dmacount(&(ic)->ic_dmastate, (c))
+#define isa_dmafinished(ic, c) \
+ _isa_dmafinished(&(ic)->ic_dmastate, (c))
+#define isa_dmadone(ic, c) \
+ _isa_dmadone(&(ic)->ic_dmastate, (c))
+#define isa_dmafreeze(ic) \
+ _isa_dmafreeze(&(ic)->ic_dmastate)
+#define isa_dmathaw(ic) \
+ _isa_dmathaw(&(ic)->ic_dmastate)
+#define isa_dmamem_alloc(ic, c, s, ap, f) \
+ _isa_dmamem_alloc(&(ic)->ic_dmastate, (c), (s), (ap), (f))
+#define isa_dmamem_free(ic, c, a, s) \
+ _isa_dmamem_free(&(ic)->ic_dmastate, (c), (a), (s))
+#define isa_dmamem_map(ic, c, a, s, kp, f) \
+ _isa_dmamem_map(&(ic)->ic_dmastate, (c), (a), (s), (kp), (f))
+#define isa_dmamem_unmap(ic, c, k, s) \
+ _isa_dmamem_unmap(&(ic)->ic_dmastate, (c), (k), (s))
+#define isa_dmamem_mmap(ic, c, a, s, o, p, f) \
+ _isa_dmamem_mmap(&(ic)->ic_dmastate, (c), (a), (s), (o), (p), (f))
+#define isa_drq_alloc(ic, c) \
+ _isa_drq_alloc(&(ic)->ic_dmastate, c)
+#define isa_drq_free(ic, c) \
+ _isa_drq_free(&(ic)->ic_dmastate, c)
+#define isa_drq_isfree(ic, c) \
+ _isa_drq_isfree(&(ic)->ic_dmastate, (c))
+#define isa_malloc(ic, c, s, p, f) \
+ _isa_malloc(&(ic)->ic_dmastate, (c), (s), (p), (f))
+#define isa_free(a, p) \
+ _isa_free((a), (p))
+#define isa_mappage(m, o, p) \
+ _isa_mappage((m), (o), (p))
+
+/*
+ * for ACPI code
+ */
+
+void isa_reinit_irq(void);
+
+/*
+ * ALL OF THE FOLLOWING ARE MACHINE-DEPENDENT, AND SHOULD NOT BE USED
+ * BY PORTABLE CODE.
+ */
+
+extern struct x86_bus_dma_tag isa_bus_dma_tag;
+
+/*
+ * XXX Various seemingly PC-specific constants, some of which may be
+ * unnecessary anyway.
+ */
+
+/*
+ * RAM Physical Address Space (ignoring the above mentioned "hole")
+ */
+#define RAM_BEGIN 0x0000000 /* Start of RAM Memory */
+#define RAM_END 0x1000000 /* End of RAM Memory */
+#define RAM_SIZE (RAM_END - RAM_BEGIN)
+
+/*
+ * Oddball Physical Memory Addresses
+ */
+#define COMPAQ_RAMRELOC 0x80c00000 /* Compaq RAM relocation/diag */
+#define COMPAQ_RAMSETUP 0x80c00002 /* Compaq RAM setup */
+#define WEITEK_FPU 0xC0000000 /* WTL 2167 */
+#define CYRIX_EMC 0xC0000000 /* Cyrix EMC */
+
+/*
+ * stuff that used to be in pccons.c
+ */
+#define MONO_BASE 0x3B4
+#define MONO_BUF 0xB0000
+#define CGA_BASE 0x3D4
+#define CGA_BUF 0xB8000
+
+/*
+ * Variables and macros to deal with the ISA I/O hole.
+ * XXX These should be converted to machine- and bus-mapping-independent
+ * function definitions, invoked through the softc.
+ */
+
+extern vaddr_t atdevbase; /* kernel virtual address of "hole" */
+
+/*
+ * Given a kernel virtual address for some location
+ * in the "hole" I/O space, return a physical address.
+ */
+#define ISA_PHYSADDR(v) ((bus_addr_t)(v) - atdevbase + IOM_BEGIN)
+
+/*
+ * Given a physical address in the "hole",
+ * return a kernel virtual address.
+ */
+#define ISA_HOLE_VADDR(p) ((void *) ((vaddr_t)(p) - IOM_BEGIN + atdevbase))
+
+
+/*
+ * Miscellanous functions.
+ */
+void sysbeep(int, int); /* beep with the system speaker */
+
+#endif /* _X86_ISA_MACHDEP_H_ XXX */
--- /dev/null
+/* $NetBSD: lock.h,v 1.26 2012/10/11 11:12:21 apb Exp $ */
+
+/*-
+ * Copyright (c) 2000, 2006 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe and Andrew Doran.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Machine-dependent spin lock operations.
+ */
+
+#ifndef _X86_LOCK_H_
+#define _X86_LOCK_H_
+
+#include <sys/param.h>
+
+static __inline int
+__SIMPLELOCK_LOCKED_P(__cpu_simple_lock_t *__ptr)
+{
+ return *__ptr == __SIMPLELOCK_LOCKED;
+}
+
+static __inline int
+__SIMPLELOCK_UNLOCKED_P(__cpu_simple_lock_t *__ptr)
+{
+ return *__ptr == __SIMPLELOCK_UNLOCKED;
+}
+
+static __inline void
+__cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
+{
+
+ *__ptr = __SIMPLELOCK_LOCKED;
+}
+
+static __inline void
+__cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr)
+{
+
+ *__ptr = __SIMPLELOCK_UNLOCKED;
+}
+
+#ifdef _HARDKERNEL
+
+#include <machine/cpufunc.h>
+
+void __cpu_simple_lock_init(__cpu_simple_lock_t *);
+void __cpu_simple_lock(__cpu_simple_lock_t *);
+int __cpu_simple_lock_try(__cpu_simple_lock_t *);
+void __cpu_simple_unlock(__cpu_simple_lock_t *);
+
+#define SPINLOCK_SPIN_HOOK /* nothing */
+
+#ifdef SPINLOCK_BACKOFF_HOOK
+#undef SPINLOCK_BACKOFF_HOOK
+#endif
+#define SPINLOCK_BACKOFF_HOOK x86_pause()
+
+#else
+
+static __inline void __cpu_simple_lock_init(__cpu_simple_lock_t *)
+ __unused;
+static __inline void __cpu_simple_lock(__cpu_simple_lock_t *)
+ __unused;
+static __inline int __cpu_simple_lock_try(__cpu_simple_lock_t *)
+ __unused;
+static __inline void __cpu_simple_unlock(__cpu_simple_lock_t *)
+ __unused;
+
+static __inline void
+__cpu_simple_lock_init(__cpu_simple_lock_t *lockp)
+{
+
+ *lockp = __SIMPLELOCK_UNLOCKED;
+ __insn_barrier();
+}
+
+static __inline int
+__cpu_simple_lock_try(__cpu_simple_lock_t *lockp)
+{
+ uint8_t val;
+
+ val = __SIMPLELOCK_LOCKED;
+ __asm volatile ("xchgb %0,(%2)" :
+ "=qQ" (val)
+ :"0" (val), "r" (lockp));
+ __insn_barrier();
+ return val == __SIMPLELOCK_UNLOCKED;
+}
+
+static __inline void
+__cpu_simple_lock(__cpu_simple_lock_t *lockp)
+{
+
+ while (!__cpu_simple_lock_try(lockp))
+ /* nothing */;
+ __insn_barrier();
+}
+
+/*
+ * Note on x86 memory ordering
+ *
+ * When releasing a lock we must ensure that no stores or loads from within
+ * the critical section are re-ordered by the CPU to occur outside of it:
+ * they must have completed and be visible to other processors once the lock
+ * has been released.
+ *
+ * NetBSD usually runs with the kernel mapped (via MTRR) in a WB (write
+ * back) memory region. In that case, memory ordering on x86 platforms
+ * looks like this:
+ *
+ * i386 All loads/stores occur in instruction sequence.
+ *
+ * i486 All loads/stores occur in instruction sequence. In
+ * Pentium exceptional circumstances, loads can be re-ordered around
+ * stores, but for the purposes of releasing a lock it does
+ * not matter. Stores may not be immediately visible to other
+ * processors as they can be buffered. However, since the
+ * stores are buffered in order the lock release will always be
+ * the last operation in the critical section that becomes
+ * visible to other CPUs.
+ *
+ * Pentium Pro The "Intel 64 and IA-32 Architectures Software Developer's
+ * onwards Manual" volume 3A (order number 248966) says that (1) "Reads
+ * can be carried out speculatively and in any order" and (2)
+ * "Reads can pass buffered stores, but the processor is
+ * self-consistent.". This would be a problem for the below,
+ * and would mandate a locked instruction cycle or load fence
+ * before releasing the simple lock.
+ *
+ * The "Intel Pentium 4 Processor Optimization" guide (order
+ * number 253668-022US) says: "Loads can be moved before stores
+ * that occurred earlier in the program if they are not
+ * predicted to load from the same linear address.". This is
+ * not a problem since the only loads that can be re-ordered
+ * take place once the lock has been released via a store.
+ *
+ * The above two documents seem to contradict each other,
+ * however with the exception of early steppings of the Pentium
+ * Pro, the second document is closer to the truth: a store
+ * will always act as a load fence for all loads that precede
+ * the store in instruction order.
+ *
+ * Again, note that stores can be buffered and will not always
+ * become immediately visible to other CPUs: they are however
+ * buffered in order.
+ *
+ * AMD64 Stores occur in order and are buffered. Loads can be
+ * reordered, however stores act as load fences, meaning that
+ * loads can not be reordered around stores.
+ */
+static __inline void
+__cpu_simple_unlock(__cpu_simple_lock_t *lockp)
+{
+
+ __insn_barrier();
+ *lockp = __SIMPLELOCK_UNLOCKED;
+}
+
+#endif /* _HARDKERNEL */
+
+#endif /* _X86_LOCK_H_ */
--- /dev/null
+/* $NetBSD: machdep.h,v 1.5 2010/10/21 11:17:54 yamt Exp $ */
+/*
+ * Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_MACHDEP_H_
+#define _X86_MACHDEP_H_
+
+extern phys_ram_seg_t mem_clusters[];
+extern int mem_cluster_cnt;
+
+struct btinfo_memmap;
+struct extent;
+
+void x86_cpu_idle_init(void);
+void x86_cpu_idle_get(void (**)(void), char *, size_t);
+void x86_cpu_idle_set(void (*)(void), const char *, bool);
+
+int initx86_parse_memmap(struct btinfo_memmap *, struct extent *);
+int initx86_fake_memmap(struct extent *);
+int initx86_load_memmap(paddr_t first_avail);
+
+void x86_startup(void);
+
+#endif /* _X86_MACHDEP_H_ */
--- /dev/null
+/* $NetBSD: mpacpi.h,v 1.9 2009/04/17 21:07:58 dyoung Exp $ */
+
+#ifndef _X86_MPACPI_H_
+#define _X86_MPACPI_H_
+
+struct pcibus_attach_args;
+
+int mpacpi_scan_apics(device_t, int *);
+int mpacpi_find_interrupts(void *);
+int mpacpi_pci_attach_hook(device_t, device_t,
+ struct pcibus_attach_args *);
+
+struct mp_intr_map;
+int mpacpi_findintr_linkdev(struct mp_intr_map *);
+
+extern struct mp_intr_map *mpacpi_sci_override;
+
+#endif /* _X86_MPACPI_H_ */
--- /dev/null
+/* $NetBSD: mpbiosreg.h,v 1.6 2010/04/18 23:47:51 jym Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_MPBIOSREG_H_
+#define _X86_MPBIOSREG_H_
+
+#define BIOS_BASE (0xf0000)
+#define BIOS_SIZE (0x10000)
+#define BIOS_COUNT (BIOS_SIZE)
+
+/*
+ * Multiprocessor config table entry types.
+ */
+
+#define MPS_MCT_CPU 0
+#define MPS_MCT_BUS 1
+#define MPS_MCT_IOAPIC 2
+#define MPS_MCT_IOINT 3
+#define MPS_MCT_LINT 4
+
+#define MPS_MCT_NTYPES 5
+
+/* MP Floating Pointer Structure */
+struct mpbios_fps {
+ uint32_t signature;
+/* string defined by the Intel MP Spec as identifying the MP table */
+#define MP_FP_SIG 0x5f504d5f /* _MP_ */
+
+ uint32_t pap;
+ uint8_t length;
+ uint8_t spec_rev;
+ uint8_t checksum;
+ uint8_t mpfb1; /* system configuration */
+ uint8_t mpfb2; /* flags */
+#define MPFPS_FLAG_IMCR 0x80 /* IMCR present */
+ uint8_t mpfb3; /* unused */
+ uint8_t mpfb4; /* unused */
+ uint8_t mpfb5; /* unused */
+};
+
+/* MP Configuration Table Header */
+struct mpbios_cth {
+ uint32_t signature;
+#define MP_CT_SIG 0x504d4350 /* PCMP */
+
+ uint16_t base_len;
+ uint8_t spec_rev;
+ uint8_t checksum;
+ uint8_t oem_id[8];
+ uint8_t product_id[12];
+ uint32_t oem_table_pointer;
+ uint16_t oem_table_size;
+ uint16_t entry_count;
+ uint32_t apic_address;
+ uint16_t ext_len;
+ uint8_t ext_cksum;
+ uint8_t reserved;
+};
+
+struct mpbios_proc {
+ uint8_t type;
+ uint8_t apic_id;
+ uint8_t apic_version;
+ uint8_t cpu_flags;
+#define PROCENTRY_FLAG_EN 0x01
+#define PROCENTRY_FLAG_BP 0x02
+ uint32_t reserved1;
+ uint32_t reserved2;
+};
+
+struct mpbios_bus {
+ uint8_t type;
+ uint8_t bus_id;
+ char bus_type[6];
+};
+
+struct mpbios_ioapic {
+ uint8_t type;
+ uint8_t apic_id;
+ uint8_t apic_version;
+ uint8_t apic_flags;
+#define IOAPICENTRY_FLAG_EN 0x01
+ uint32_t apic_address;
+};
+
+struct mpbios_int {
+ uint8_t type;
+ uint8_t int_type;
+ uint16_t int_flags;
+ uint8_t src_bus_id;
+ uint8_t src_bus_irq;
+ uint8_t dst_apic_id;
+#define MPS_ALL_APICS 0xff
+ uint8_t dst_apic_int;
+};
+
+
+#endif /* !_X86_MPBIOSREG_H_ */
--- /dev/null
+/* $NetBSD: mpbiosvar.h,v 1.8 2009/04/17 21:07:58 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _X86_MPBIOSVAR_H_
+#define _X86_MPBIOSVAR_H_
+
+#define MP_TRAMPOLINE (2 * PAGE_SIZE)
+
+#if !defined(_LOCORE)
+
+#include <machine/mpbiosreg.h>
+#include <machine/mpconfig.h>
+
+struct pcibus_attach_args;
+
+#if defined(_KERNEL)
+void mpbios_scan(device_t, int *);
+int mpbios_probe(device_t);
+int mpbios_pci_attach_hook(device_t, device_t,
+ struct pcibus_attach_args *);
+
+extern int mpbios_scanned;
+#endif
+
+#endif
+
+#endif /* !_X86_MPBIOSVAR_H_ */
--- /dev/null
+/* $NetBSD: mpconfig.h,v 1.14 2012/06/15 13:57:59 yamt Exp $ */
+
+/*
+ * Definitions originally from the mpbios code, but now used for ACPI
+ * MP config as well.
+ */
+
+#ifndef _X86_MPCONFIG_H_
+#define _X86_MPCONFIG_H_
+
+/*
+ * XXX
+ */
+#include <sys/bus.h>
+#include <dev/pci/pcivar.h>
+#include <machine/pci_machdep.h>
+
+/*
+ * Interrupt types
+ */
+#define MPS_INTTYPE_INT 0
+#define MPS_INTTYPE_NMI 1
+#define MPS_INTTYPE_SMI 2
+#define MPS_INTTYPE_ExtINT 3
+
+#define MPS_INTPO_DEF 0
+#define MPS_INTPO_ACTHI 1
+#define MPS_INTPO_ACTLO 3
+
+#define MPS_INTTR_DEF 0
+#define MPS_INTTR_EDGE 1
+#define MPS_INTTR_LEVEL 3
+
+#ifndef _LOCORE
+
+struct mpbios_int;
+
+struct mp_bus
+{
+ const char *mb_name; /* XXX bus name */
+ int mb_idx; /* XXX bus index */
+ void (*mb_intr_print)(int);
+ void (*mb_intr_cfg)(const struct mpbios_int *, uint32_t *);
+ struct mp_intr_map *mb_intrs;
+ uint32_t mb_data; /* random bus-specific datum. */
+ device_t mb_dev; /* has been autoconfigured if mb_dev != NULL */
+ pcitag_t *mb_pci_bridge_tag;
+ pci_chipset_tag_t mb_pci_chipset_tag;
+};
+
+struct mp_intr_map
+{
+ struct mp_intr_map *next;
+ struct mp_bus *bus;
+ /*
+ * encoding of bus_pin is mp_bus dependant.
+ * for pci, bus_pin = (pci_device_number << 2) | pin
+ * where pin is 0=INTA ... 3=INTD.
+ */
+ int bus_pin;
+ struct pic *ioapic; /* NULL for local apic */
+ int ioapic_pin;
+ int ioapic_ih; /* int handle, see i82093var.h for encoding */
+ int type; /* from mp spec intr record */
+ int flags; /* from mp spec intr record */
+ uint32_t redir;
+ uint32_t cpu_id;
+ int global_int; /* ACPI global interrupt number */
+ int sflags; /* other, software flags (see below) */
+ void *linkdev;
+ int sourceindex;
+};
+
+#define MPI_OVR 0x0001 /* Was overridden by an ACPI OVR */
+
+#if defined(_KERNEL)
+extern int mp_verbose;
+extern struct mp_bus *mp_busses;
+extern struct mp_intr_map *mp_intrs;
+extern int mp_nintr;
+extern int mp_isa_bus, mp_eisa_bus;
+extern int mp_nbus;
+int mp_pci_scan(device_t, struct pcibus_attach_args *, cfprint_t);
+void mp_pci_childdetached(device_t, device_t);
+#endif
+#endif
+
+#endif /* _X86_MPCONFIG_H_ */
--- /dev/null
+/* $NetBSD: mtrr.h,v 1.5 2011/12/15 09:38:21 abs Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_MTRR_H_
+#define _X86_MTRR_H_
+
+#define MTRR_I686_FIXED_IDX64K 0
+#define MTRR_I686_FIXED_IDX16K 1
+#define MTRR_I686_FIXED_IDX4K 3
+
+#define MTRR_I686_NVAR_MAX 16 /* could be upto 255? */
+
+#define MTRR_I686_64K_START 0x00000
+#define MTRR_I686_16K_START 0x80000
+#define MTRR_I686_4K_START 0xc0000
+
+#define MTRR_I686_NFIXED_64K 1
+#define MTRR_I686_NFIXED_16K 2
+#define MTRR_I686_NFIXED_4K 8
+#define MTRR_I686_NFIXED 11
+#define MTRR_I686_NFIXED_SOFT_64K (MTRR_I686_NFIXED_64K * 8)
+#define MTRR_I686_NFIXED_SOFT_16K (MTRR_I686_NFIXED_16K * 8)
+#define MTRR_I686_NFIXED_SOFT_4K (MTRR_I686_NFIXED_4K * 8)
+#define MTRR_I686_NFIXED_SOFT (MTRR_I686_NFIXED * 8)
+
+#define MTRR_I686_ENABLE_MASK 0x0800
+#define MTRR_I686_FIXED_ENABLE_MASK 0x0400
+
+#define MTRR_I686_CAP_VCNT_MASK 0x00ff
+#define MTRR_I686_CAP_FIX_MASK 0x0100
+#define MTRR_I686_CAP_WC_MASK 0x0400
+
+#define MTRR_TYPE_UC 0
+#define MTRR_TYPE_WC 1
+#define MTRR_TYPE_UNDEF1 2
+#define MTRR_TYPE_UNDEF2 3
+#define MTRR_TYPE_WT 4
+#define MTRR_TYPE_WP 5
+#define MTRR_TYPE_WB 6
+
+struct mtrr_state {
+ uint32_t msraddr;
+ uint64_t msrval;
+};
+
+#define MTRR_PRIVATE 0x0001 /* 'own' range, reset at exit */
+#define MTRR_FIXED 0x0002 /* use fixed range mtrr */
+#define MTRR_VALID 0x0004 /* entry is valid */
+
+#define MTRR_CANTSET MTRR_FIXED
+
+#define MTRR_I686_MASK_VALID (1 << 11)
+
+/*
+ * AMD K6 MTRRs.
+ *
+ * There are two of these MTRR-like registers in the UWCRR.
+ */
+
+#define MTRR_K6_ADDR_SHIFT 17
+#define MTRR_K6_ADDR (0x7fffU << MTRR_K6_ADDR_SHIFT)
+#define MTRR_K6_MASK_SHIFT 2
+#define MTRR_K6_MASK (0x7fffU << MTRR_K6_MASK_SHIFT)
+#define MTRR_K6_WC (1U << 1) /* write-combine */
+#define MTRR_K6_UC (1U << 0) /* uncached */
+
+#define MTRR_K6_NVAR 2
+
+#ifdef _KERNEL
+
+#define mtrr_base_value(mtrrp) \
+ (((uint64_t)(mtrrp)->base) | ((uint64_t)(mtrrp)->type))
+#define mtrr_mask_value(mtrrp) \
+ ((~((mtrrp)->len - 1) & 0x0000000ffffff000LL))
+
+
+#define mtrr_len(val) \
+ ((~((val) & 0x0000000ffffff000LL)+1) & 0x0000000ffffff000LL)
+#define mtrr_base(val) ((val) & 0x0000000ffffff000LL)
+#define mtrr_type(val) ((uint8_t)((val) & 0x00000000000000ffLL))
+#define mtrr_valid(val) (((val) & MTRR_I686_MASK_VALID) != 0)
+
+struct proc;
+struct mtrr;
+
+void i686_mtrr_init_first(void);
+void k6_mtrr_init_first(void);
+
+struct mtrr_funcs {
+ void (*init_cpu)(struct cpu_info *ci);
+ void (*reload_cpu)(struct cpu_info *ci);
+ void (*clean)(struct proc *p);
+ int (*set)(struct mtrr *, int *n, struct proc *p, int flags);
+ int (*get)(struct mtrr *, int *n, struct proc *p, int flags);
+ void (*commit)(void);
+ void (*dump)(const char *tag);
+};
+
+extern struct mtrr_funcs i686_mtrr_funcs;
+extern struct mtrr_funcs k6_mtrr_funcs;
+extern struct mtrr_funcs *mtrr_funcs;
+
+#define mtrr_init_cpu(ci) mtrr_funcs->init_cpu(ci)
+#define mtrr_reload_cpu(ci) mtrr_funcs->reload_cpu(ci)
+#define mtrr_clean(p) mtrr_funcs->clean(p)
+#define mtrr_set(mp,n,p,f) mtrr_funcs->set(mp,n,p,f)
+#define mtrr_get(mp,n,p,f) mtrr_funcs->get(mp,n,p,f)
+#define mtrr_dump(s) mtrr_funcs->dump(s)
+#define mtrr_commit() mtrr_funcs->commit()
+
+#define MTRR_GETSET_USER 0x0001
+#define MTRR_GETSET_KERNEL 0x0002
+
+#endif /* _KERNEL */
+
+struct mtrr {
+ uint64_t base; /* physical base address */
+ uint64_t len;
+ uint8_t type;
+ int flags;
+ pid_t owner; /* valid if MTRR_PRIVATE set in flags */
+};
+
+#endif /* _X86_MTRR_H_ */
--- /dev/null
+/* $Id: nmi.h,v 1.1 2009/02/24 06:03:54 yamt Exp $ */
+
+/*-
+ * Copyright (c)2009 YAMAMOTO Takashi,
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _X86_NMI_H_
+#define _X86_NMI_H_
+
+typedef struct nmi_handler nmi_handler_t;
+struct trapframe;
+
+nmi_handler_t *nmi_establish(int (*)(const struct trapframe *, void *), void *);
+void nmi_disestablish(nmi_handler_t *);
+int nmi_dispatch(const struct trapframe *);
+void nmi_init(void);
+
+#endif /* _X86_NMI_H_ */
--- /dev/null
+/* $NetBSD: pci_machdep.h,v 1.14 2010/03/14 20:19:06 dyoung Exp $ */
+
+/*
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Charles M. Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_PCI_MACHDEP_H_
+#define _X86_PCI_MACHDEP_H_
+
+/*
+ * Types provided to machine-independent PCI code
+ */
+typedef int pci_intr_handle_t;
+
+#include <x86/pci_machdep_common.h>
+
+#endif /* _X86_PCI_MACHDEP_H_ */
--- /dev/null
+/* $NetBSD: pci_machdep_common.h,v 1.9 2012/06/15 13:58:34 yamt Exp $ */
+
+/*
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Charles M. Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_PCI_MACHDEP_COMMON_H_
+#define _X86_PCI_MACHDEP_COMMON_H_
+
+/*
+ * Machine-specific definitions for PCI autoconfiguration.
+ */
+#define __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
+#ifndef XEN
+#define __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH
+#endif
+
+/*
+ * i386-specific PCI structure and type definitions.
+ * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
+ *
+ * Configuration tag; created from a {bus,device,function} triplet by
+ * pci_make_tag(), and passed to pci_conf_read() and pci_conf_write().
+ * We could instead always pass the {bus,device,function} triplet to
+ * the read and write routines, but this would cause extra overhead.
+ *
+ * Mode 2 is historical and deprecated by the Revision 2.0 specification.
+ *
+ *
+ * Mode 1 tag:
+ * 31 24 16 15 11 10 8
+ * +---------------------------------------------------------------+
+ * |1| 0 | BUS | DEV |FUNC | 0 |
+ * +---------------------------------------------------------------+
+ */
+union x86_pci_tag_u {
+ uint32_t mode1;
+ struct {
+ uint16_t port;
+ uint8_t enable;
+ uint8_t forward;
+ } mode2;
+};
+
+extern struct x86_bus_dma_tag pci_bus_dma_tag;
+#ifdef _LP64
+extern struct x86_bus_dma_tag pci_bus_dma64_tag;
+#endif
+
+struct pci_attach_args;
+struct pci_chipset_tag;
+
+/*
+ * Types provided to machine-independent PCI code
+ */
+typedef struct pci_chipset_tag *pci_chipset_tag_t;
+typedef union x86_pci_tag_u pcitag_t;
+
+struct pci_chipset_tag {
+ pci_chipset_tag_t pc_super;
+ uint64_t pc_present;
+ const struct pci_overrides *pc_ov;
+ void *pc_ctx;
+};
+
+/*
+ * i386-specific PCI variables and functions.
+ * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
+ */
+int pci_bus_flags(void);
+int pci_mode_detect(void);
+void pci_mode_set(int);
+
+/*
+ * Functions provided to machine-independent PCI code.
+ */
+void pci_attach_hook(device_t, device_t,
+ struct pcibus_attach_args *);
+int pci_bus_maxdevs(pci_chipset_tag_t, int);
+pcitag_t pci_make_tag(pci_chipset_tag_t, int, int, int);
+void pci_decompose_tag(pci_chipset_tag_t, pcitag_t,
+ int *, int *, int *);
+pcireg_t pci_conf_read(pci_chipset_tag_t, pcitag_t, int);
+void pci_conf_write(pci_chipset_tag_t, pcitag_t, int,
+ pcireg_t);
+int pci_intr_map(const struct pci_attach_args *,
+ pci_intr_handle_t *);
+const char *pci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
+const struct evcnt *pci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t);
+void *pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
+ int, int (*)(void *), void *);
+void pci_intr_disestablish(pci_chipset_tag_t, void *);
+
+/* experimental MSI support */
+void *pci_msi_establish(struct pci_attach_args *, int, int (*)(void *), void *);
+void pci_msi_disestablish(void *);
+
+/*
+ * ALL OF THE FOLLOWING ARE MACHINE-DEPENDENT, AND SHOULD NOT BE USED
+ * BY PORTABLE CODE.
+ */
+
+/* Extract Bus Number for a host bridge or -1 if unknown. */
+int pchb_get_bus_number(pci_chipset_tag_t, pcitag_t);
+
+/*
+ * Section 6.2.4, `Miscellaneous Functions' of the PCI Specification,
+ * says that 255 means `unknown' or `no connection' to the interrupt
+ * controller on a PC.
+ */
+#define X86_PCI_INTERRUPT_LINE_NO_CONNECTION 0xff
+
+void pci_device_foreach(pci_chipset_tag_t, int,
+ void (*)(pci_chipset_tag_t, pcitag_t, void*),
+ void *);
+
+void pci_device_foreach_min(pci_chipset_tag_t, int, int,
+ void (*)(pci_chipset_tag_t, pcitag_t, void*),
+ void *);
+
+void pci_bridge_foreach(pci_chipset_tag_t, int, int,
+ void (*) (pci_chipset_tag_t, pcitag_t, void *), void *);
+
+void pci_ranges_infer(pci_chipset_tag_t, int, int, bus_addr_t *,
+ bus_size_t *, bus_addr_t *, bus_size_t *);
+
+extern prop_dictionary_t pci_rsrc_dict;
+prop_dictionary_t pci_rsrc_filter(prop_dictionary_t,
+ bool (*)(void *, prop_dictionary_t), void *arg);
+
+#endif /* _X86_PCI_MACHDEP_COMMON_H_ */
--- /dev/null
+/* $NetBSD: pic.h,v 1.7 2009/04/19 14:11:37 ad Exp $ */
+
+#ifndef _X86_PIC_H
+#define _X86_PIC_H
+
+struct cpu_info;
+
+/*
+ * Structure common to all PIC softcs
+ */
+struct pic {
+ const char *pic_name;
+ int pic_type;
+ int pic_vecbase;
+ int pic_apicid;
+ __cpu_simple_lock_t pic_lock;
+ void (*pic_hwmask)(struct pic *, int);
+ void (*pic_hwunmask)(struct pic *, int);
+ void (*pic_addroute)(struct pic *, struct cpu_info *, int, int, int);
+ void (*pic_delroute)(struct pic *, struct cpu_info *, int, int, int);
+ bool (*pic_trymask)(struct pic *, int);
+ struct intrstub *pic_level_stubs;
+ struct intrstub *pic_edge_stubs;
+ struct ioapic_softc *pic_ioapic; /* if pic_type == PIC_IOAPIC */
+};
+
+/*
+ * PIC types.
+ */
+#define PIC_I8259 0
+#define PIC_IOAPIC 1
+#define PIC_LAPIC 2
+#define PIC_SOFT 3
+
+extern struct pic i8259_pic;
+extern struct pic local_pic;
+extern struct pic softintr_pic;
+#endif
--- /dev/null
+/* $NetBSD: pmap.h,v 1.52 2012/04/20 22:23:24 rmind Exp $ */
+
+/*
+ * Copyright (c) 1997 Charles D. Cranor and Washington University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Frank van der Linden for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * pmap.h: see pmap.c for the history of this pmap module.
+ */
+
+#ifndef _X86_PMAP_H_
+#define _X86_PMAP_H_
+
+/*
+ * pl*_pi: index in the ptp page for a pde mapping a VA.
+ * (pl*_i below is the index in the virtual array of all pdes per level)
+ */
+#define pl1_pi(VA) (((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT)
+#define pl2_pi(VA) (((VA_SIGN_POS(VA)) & L2_MASK) >> L2_SHIFT)
+#define pl3_pi(VA) (((VA_SIGN_POS(VA)) & L3_MASK) >> L3_SHIFT)
+#define pl4_pi(VA) (((VA_SIGN_POS(VA)) & L4_MASK) >> L4_SHIFT)
+
+/*
+ * pl*_i: generate index into pde/pte arrays in virtual space
+ *
+ * pl_i(va, X) == plX_i(va) <= pl_i_roundup(va, X)
+ */
+#define pl1_i(VA) (((VA_SIGN_POS(VA)) & L1_FRAME) >> L1_SHIFT)
+#define pl2_i(VA) (((VA_SIGN_POS(VA)) & L2_FRAME) >> L2_SHIFT)
+#define pl3_i(VA) (((VA_SIGN_POS(VA)) & L3_FRAME) >> L3_SHIFT)
+#define pl4_i(VA) (((VA_SIGN_POS(VA)) & L4_FRAME) >> L4_SHIFT)
+#define pl_i(va, lvl) \
+ (((VA_SIGN_POS(va)) & ptp_masks[(lvl)-1]) >> ptp_shifts[(lvl)-1])
+
+#define pl_i_roundup(va, lvl) pl_i((va)+ ~ptp_masks[(lvl)-1], (lvl))
+
+/*
+ * PTP macros:
+ * a PTP's index is the PD index of the PDE that points to it
+ * a PTP's offset is the byte-offset in the PTE space that this PTP is at
+ * a PTP's VA is the first VA mapped by that PTP
+ */
+
+#define ptp_va2o(va, lvl) (pl_i(va, (lvl)+1) * PAGE_SIZE)
+
+/* size of a PDP: usually one page, except for PAE */
+#ifdef PAE
+#define PDP_SIZE 4
+#else
+#define PDP_SIZE 1
+#endif
+
+
+#if defined(_KERNEL)
+#include <sys/kcpuset.h>
+
+/*
+ * pmap data structures: see pmap.c for details of locking.
+ */
+
+/*
+ * we maintain a list of all non-kernel pmaps
+ */
+
+LIST_HEAD(pmap_head, pmap); /* struct pmap_head: head of a pmap list */
+
+/*
+ * linked list of all non-kernel pmaps
+ */
+extern struct pmap_head pmaps;
+extern kmutex_t pmaps_lock; /* protects pmaps */
+
+/*
+ * pool_cache(9) that PDPs are allocated from
+ */
+extern struct pool_cache pmap_pdp_cache;
+
+/*
+ * the pmap structure
+ *
+ * note that the pm_obj contains the lock pointer, the reference count,
+ * page list, and number of PTPs within the pmap.
+ *
+ * pm_lock is the same as the lock for vm object 0. Changes to
+ * the other objects may only be made if that lock has been taken
+ * (the other object locks are only used when uvm_pagealloc is called)
+ *
+ * XXX If we ever support processor numbers higher than 31, we'll have
+ * XXX to rethink the CPU mask.
+ */
+
+struct pmap {
+ struct uvm_object pm_obj[PTP_LEVELS-1]; /* objects for lvl >= 1) */
+#define pm_lock pm_obj[0].vmobjlock
+ kmutex_t pm_obj_lock[PTP_LEVELS-1]; /* locks for pm_objs */
+ LIST_ENTRY(pmap) pm_list; /* list (lck by pm_list lock) */
+ pd_entry_t *pm_pdir; /* VA of PD (lck by object lock) */
+ paddr_t pm_pdirpa[PDP_SIZE]; /* PA of PDs (read-only after create) */
+ struct vm_page *pm_ptphint[PTP_LEVELS-1];
+ /* pointer to a PTP in our pmap */
+ struct pmap_statistics pm_stats; /* pmap stats (lck by object lock) */
+
+#if !defined(__x86_64__)
+ vaddr_t pm_hiexec; /* highest executable mapping */
+#endif /* !defined(__x86_64__) */
+ int pm_flags; /* see below */
+
+ union descriptor *pm_ldt; /* user-set LDT */
+ size_t pm_ldt_len; /* size of LDT in bytes */
+ int pm_ldt_sel; /* LDT selector */
+ kcpuset_t *pm_cpus; /* mask of CPUs using pmap */
+ kcpuset_t *pm_kernel_cpus; /* mask of CPUs using kernel part
+ of pmap */
+ kcpuset_t *pm_xen_ptp_cpus; /* mask of CPUs which have this pmap's
+ ptp mapped */
+ uint64_t pm_ncsw; /* for assertions */
+ struct vm_page *pm_gc_ptp; /* pages from pmap g/c */
+};
+
+/* macro to access pm_pdirpa slots */
+#ifdef PAE
+#define pmap_pdirpa(pmap, index) \
+ ((pmap)->pm_pdirpa[l2tol3(index)] + l2tol2(index) * sizeof(pd_entry_t))
+#else
+#define pmap_pdirpa(pmap, index) \
+ ((pmap)->pm_pdirpa[0] + (index) * sizeof(pd_entry_t))
+#endif
+
+/*
+ * flag to be used for kernel mappings: PG_u on Xen/amd64,
+ * 0 otherwise.
+ */
+#if defined(XEN) && defined(__x86_64__)
+#define PG_k PG_u
+#else
+#define PG_k 0
+#endif
+
+/*
+ * MD flags that we use for pmap_enter and pmap_kenter_pa:
+ */
+
+/*
+ * global kernel variables
+ */
+
+/*
+ * PDPpaddr is the physical address of the kernel's PDP.
+ * - i386 non-PAE and amd64: PDPpaddr corresponds directly to the %cr3
+ * value associated to the kernel process, proc0.
+ * - i386 PAE: it still represents the PA of the kernel's PDP (L2). Due to
+ * the L3 PD, it cannot be considered as the equivalent of a %cr3 any more.
+ * - Xen: it corresponds to the PFN of the kernel's PDP.
+ */
+extern u_long PDPpaddr;
+
+extern int pmap_pg_g; /* do we support PG_G? */
+extern long nkptp[PTP_LEVELS];
+
+/*
+ * macros
+ */
+
+#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
+#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
+
+#define pmap_clear_modify(pg) pmap_clear_attrs(pg, PG_M)
+#define pmap_clear_reference(pg) pmap_clear_attrs(pg, PG_U)
+#define pmap_copy(DP,SP,D,L,S)
+#define pmap_is_modified(pg) pmap_test_attrs(pg, PG_M)
+#define pmap_is_referenced(pg) pmap_test_attrs(pg, PG_U)
+#define pmap_move(DP,SP,D,L,S)
+#define pmap_phys_address(ppn) (x86_ptob(ppn) & ~X86_MMAP_FLAG_MASK)
+#define pmap_mmap_flags(ppn) x86_mmap_flags(ppn)
+#define pmap_valid_entry(E) ((E) & PG_V) /* is PDE or PTE valid? */
+
+#if defined(__x86_64__) || defined(PAE)
+#define X86_MMAP_FLAG_SHIFT (64 - PGSHIFT)
+#else
+#define X86_MMAP_FLAG_SHIFT (32 - PGSHIFT)
+#endif
+
+#define X86_MMAP_FLAG_MASK 0xf
+#define X86_MMAP_FLAG_PREFETCH 0x1
+
+/*
+ * prototypes
+ */
+
+void pmap_activate(struct lwp *);
+void pmap_bootstrap(vaddr_t);
+bool pmap_clear_attrs(struct vm_page *, unsigned);
+void pmap_deactivate(struct lwp *);
+void pmap_page_remove (struct vm_page *);
+void pmap_remove(struct pmap *, vaddr_t, vaddr_t);
+bool pmap_test_attrs(struct vm_page *, unsigned);
+void pmap_write_protect(struct pmap *, vaddr_t, vaddr_t, vm_prot_t);
+void pmap_load(void);
+paddr_t pmap_init_tmp_pgtbl(paddr_t);
+void pmap_remove_all(struct pmap *);
+void pmap_ldt_sync(struct pmap *);
+
+void pmap_emap_enter(vaddr_t, paddr_t, vm_prot_t);
+void pmap_emap_remove(vaddr_t, vsize_t);
+void pmap_emap_sync(bool);
+
+void pmap_map_ptes(struct pmap *, struct pmap **, pd_entry_t **,
+ pd_entry_t * const **);
+void pmap_unmap_ptes(struct pmap *, struct pmap *);
+
+int pmap_pdes_invalid(vaddr_t, pd_entry_t * const *, pd_entry_t *);
+
+u_int x86_mmap_flags(paddr_t);
+
+bool pmap_is_curpmap(struct pmap *);
+
+vaddr_t reserve_dumppages(vaddr_t); /* XXX: not a pmap fn */
+
+typedef enum tlbwhy {
+ TLBSHOOT_APTE,
+ TLBSHOOT_KENTER,
+ TLBSHOOT_KREMOVE,
+ TLBSHOOT_FREE_PTP1,
+ TLBSHOOT_FREE_PTP2,
+ TLBSHOOT_REMOVE_PTE,
+ TLBSHOOT_REMOVE_PTES,
+ TLBSHOOT_SYNC_PV1,
+ TLBSHOOT_SYNC_PV2,
+ TLBSHOOT_WRITE_PROTECT,
+ TLBSHOOT_ENTER,
+ TLBSHOOT_UPDATE,
+ TLBSHOOT_BUS_DMA,
+ TLBSHOOT_BUS_SPACE,
+ TLBSHOOT__MAX,
+} tlbwhy_t;
+
+void pmap_tlb_init(void);
+void pmap_tlb_cpu_init(struct cpu_info *);
+void pmap_tlb_shootdown(pmap_t, vaddr_t, pt_entry_t, tlbwhy_t);
+void pmap_tlb_shootnow(void);
+void pmap_tlb_intr(void);
+
+#define __HAVE_PMAP_EMAP
+
+#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */
+#define PMAP_FORK /* turn on pmap_fork interface */
+
+/*
+ * Do idle page zero'ing uncached to avoid polluting the cache.
+ */
+bool pmap_pageidlezero(paddr_t);
+#define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa))
+
+/*
+ * inline functions
+ */
+
+__inline static bool __unused
+pmap_pdes_valid(vaddr_t va, pd_entry_t * const *pdes, pd_entry_t *lastpde)
+{
+ return pmap_pdes_invalid(va, pdes, lastpde) == 0;
+}
+
+/*
+ * pmap_update_pg: flush one page from the TLB (or flush the whole thing
+ * if hardware doesn't support one-page flushing)
+ */
+
+__inline static void __unused
+pmap_update_pg(vaddr_t va)
+{
+ invlpg(va);
+}
+
+/*
+ * pmap_update_2pg: flush two pages from the TLB
+ */
+
+__inline static void __unused
+pmap_update_2pg(vaddr_t va, vaddr_t vb)
+{
+ invlpg(va);
+ invlpg(vb);
+}
+
+/*
+ * pmap_page_protect: change the protection of all recorded mappings
+ * of a managed page
+ *
+ * => this function is a frontend for pmap_page_remove/pmap_clear_attrs
+ * => we only have to worry about making the page more protected.
+ * unprotecting a page is done on-demand at fault time.
+ */
+
+__inline static void __unused
+pmap_page_protect(struct vm_page *pg, vm_prot_t prot)
+{
+ if ((prot & VM_PROT_WRITE) == 0) {
+ if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
+ (void) pmap_clear_attrs(pg, PG_RW);
+ } else {
+ pmap_page_remove(pg);
+ }
+ }
+}
+
+/*
+ * pmap_protect: change the protection of pages in a pmap
+ *
+ * => this function is a frontend for pmap_remove/pmap_write_protect
+ * => we only have to worry about making the page more protected.
+ * unprotecting a page is done on-demand at fault time.
+ */
+
+__inline static void __unused
+pmap_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
+{
+ if ((prot & VM_PROT_WRITE) == 0) {
+ if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
+ pmap_write_protect(pmap, sva, eva, prot);
+ } else {
+ pmap_remove(pmap, sva, eva);
+ }
+ }
+}
+
+/*
+ * various address inlines
+ *
+ * vtopte: return a pointer to the PTE mapping a VA, works only for
+ * user and PT addresses
+ *
+ * kvtopte: return a pointer to the PTE mapping a kernel VA
+ */
+
+#include <lib/libkern/libkern.h>
+
+static __inline pt_entry_t * __unused
+vtopte(vaddr_t va)
+{
+
+ KASSERT(va < VM_MIN_KERNEL_ADDRESS);
+
+ return (PTE_BASE + pl1_i(va));
+}
+
+static __inline pt_entry_t * __unused
+kvtopte(vaddr_t va)
+{
+ pd_entry_t *pde;
+
+ KASSERT(va >= VM_MIN_KERNEL_ADDRESS);
+
+ pde = L2_BASE + pl2_i(va);
+ if (*pde & PG_PS)
+ return ((pt_entry_t *)pde);
+
+ return (PTE_BASE + pl1_i(va));
+}
+
+paddr_t vtophys(vaddr_t);
+vaddr_t pmap_map(vaddr_t, paddr_t, paddr_t, vm_prot_t);
+void pmap_cpu_init_late(struct cpu_info *);
+bool sse2_idlezero_page(void *);
+
+#ifdef XEN
+#include <sys/bitops.h>
+
+#define XPTE_MASK L1_FRAME
+/* Selects the index of a PTE in (A)PTE_BASE */
+#define XPTE_SHIFT (L1_SHIFT - ilog2(sizeof(pt_entry_t)))
+
+/* PTE access inline fuctions */
+
+/*
+ * Get the machine address of the pointed pte
+ * We use hardware MMU to get value so works only for levels 1-3
+ */
+
+static __inline paddr_t
+xpmap_ptetomach(pt_entry_t *pte)
+{
+ pt_entry_t *up_pte;
+ vaddr_t va = (vaddr_t) pte;
+
+ va = ((va & XPTE_MASK) >> XPTE_SHIFT) | (vaddr_t) PTE_BASE;
+ up_pte = (pt_entry_t *) va;
+
+ return (paddr_t) (((*up_pte) & PG_FRAME) + (((vaddr_t) pte) & (~PG_FRAME & ~VA_SIGN_MASK)));
+}
+
+/* Xen helpers to change bits of a pte */
+#define XPMAP_UPDATE_DIRECT 1 /* Update direct map entry flags too */
+
+paddr_t vtomach(vaddr_t);
+#define vtomfn(va) (vtomach(va) >> PAGE_SHIFT)
+#endif /* XEN */
+
+/* pmap functions with machine addresses */
+void pmap_kenter_ma(vaddr_t, paddr_t, vm_prot_t, u_int);
+int pmap_enter_ma(struct pmap *, vaddr_t, paddr_t, paddr_t,
+ vm_prot_t, u_int, int);
+bool pmap_extract_ma(pmap_t, vaddr_t, paddr_t *);
+
+/*
+ * Hooks for the pool allocator.
+ */
+#define POOL_VTOPHYS(va) vtophys((vaddr_t) (va))
+
+#ifdef __HAVE_DIRECT_MAP
+
+#define L4_SLOT_DIRECT 509
+#define PDIR_SLOT_DIRECT L4_SLOT_DIRECT
+
+#define PMAP_DIRECT_BASE (VA_SIGN_NEG((L4_SLOT_DIRECT * NBPD_L4)))
+#define PMAP_DIRECT_END (VA_SIGN_NEG(((L4_SLOT_DIRECT + 1) * NBPD_L4)))
+
+#define PMAP_DIRECT_MAP(pa) ((vaddr_t)PMAP_DIRECT_BASE + (pa))
+#define PMAP_DIRECT_UNMAP(va) ((paddr_t)(va) - PMAP_DIRECT_BASE)
+
+/*
+ * Alternate mapping hooks for pool pages.
+ */
+#define PMAP_MAP_POOLPAGE(pa) PMAP_DIRECT_MAP((pa))
+#define PMAP_UNMAP_POOLPAGE(va) PMAP_DIRECT_UNMAP((va))
+
+void pagezero(vaddr_t);
+
+#endif /* __HAVE_DIRECT_MAP */
+
+#endif /* _KERNEL */
+
+#endif /* _X86_PMAP_H_ */
--- /dev/null
+/* $NetBSD: pmap_pv.h,v 1.3 2011/06/12 03:35:50 rmind Exp $ */
+
+/*-
+ * Copyright (c)2008 YAMAMOTO Takashi,
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _X86_PMAP_PV_H_
+#define _X86_PMAP_PV_H_
+
+#include <sys/mutex.h>
+#include <sys/queue.h>
+
+struct vm_page;
+
+/*
+ * structures to track P->V mapping
+ *
+ * this file is intended to be minimum as it's included by <machine/vmparam.h>.
+ */
+
+/*
+ * pv_pte: describe a pte
+ */
+
+struct pv_pte {
+ struct vm_page *pte_ptp; /* PTP; NULL for pmap_kernel() */
+ vaddr_t pte_va; /* VA */
+};
+
+/*
+ * pv_entry: plug pv_pte into lists.
+ */
+
+struct pv_entry {
+ struct pv_pte pve_pte; /* should be the first member */
+ LIST_ENTRY(pv_entry) pve_list; /* on pv_head::pvh_list */
+ SLIST_ENTRY(pv_entry) pve_hash;
+};
+#define pve_next pve_list.le_next
+
+/*
+ * pmap_page: a structure which is embedded in each vm_page.
+ */
+
+struct pmap_page {
+ union {
+ /* PP_EMBEDDED */
+ struct pv_pte u_pte;
+
+ /* !PP_EMBEDDED */
+ struct pv_head {
+ LIST_HEAD(, pv_entry) pvh_list;
+ } u_head;
+
+ /* PTPs */
+ struct vm_page *u_link;
+ } pp_u;
+#define pp_pte pp_u.u_pte
+#define pp_head pp_u.u_head
+#define pp_link pp_u.u_link
+ uint8_t pp_flags;
+ uint8_t pp_attrs; /* saved PG_M and PG_U */
+};
+
+/* pp_flags */
+#define PP_EMBEDDED 1
+
+#define PMAP_PAGE_INIT(pp) /* none */
+
+#endif /* !_X86_PMAP_PV_H_ */
--- /dev/null
+/* $NetBSD: powernow.h,v 1.13 2011/02/24 10:56:02 jruoho Exp $ */
+
+/*-
+ * Copyright (c) 2004 Martin Végiard.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2004-2005 Bruno Ducrot
+ * Copyright (c) 2004 FUKUDA Nobuhiko <nfukuda@spa.is.uec.ac.jp>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_POWERNOW_H
+#define _X86_POWERNOW_H
+
+#ifdef POWERNOW_DEBUG
+#define DPRINTF(x) do { printf x; } while (0)
+#else
+#define DPRINTF(x)
+#endif
+
+#define BIOS_START 0xe0000
+#define BIOS_LEN 0x20000
+#define BIOS_STEP 16
+
+/*
+ * MSRs and bits used by Powernow technology
+ */
+#define MSR_AMDK7_FIDVID_CTL 0xc0010041
+#define MSR_AMDK7_FIDVID_STATUS 0xc0010042
+#define AMD_PN_FID_VID 0x06
+#define AMD_ERRATA_A0_CPUSIG 0x660
+
+#define PN7_FLAG_ERRATA_A0 0x01
+#define PN7_FLAG_DESKTOP_VRM 0x02
+
+/* Bitfields used by K7 */
+#define PN7_PSB_VERSION 0x12
+#define PN7_CTR_FID(x) ((x) & 0x1f)
+#define PN7_CTR_VID(x) (((x) & 0x1f) << 8)
+#define PN7_CTR_FIDC 0x00010000
+#define PN7_CTR_VIDC 0x00020000
+#define PN7_CTR_FIDCHRATIO 0x00100000
+#define PN7_CTR_SGTC(x) (((uint64_t)(x) & 0x000fffff) << 32)
+
+#define PN7_STA_CFID(x) ((x) & 0x1f)
+#define PN7_STA_SFID(x) (((x) >> 8) & 0x1f)
+#define PN7_STA_MFID(x) (((x) >> 16) & 0x1f)
+#define PN7_STA_CVID(x) (((x) >> 32) & 0x1f)
+#define PN7_STA_SVID(x) (((x) >> 40) & 0x1f)
+#define PN7_STA_MVID(x) (((x) >> 48) & 0x1f)
+
+/* Bitfields used by K8 */
+#define PN8_CTR_FID(x) ((x) & 0x3f)
+#define PN8_CTR_VID(x) (((x) & 0x1f) << 8)
+#define PN8_CTR_PENDING(x) (((x) & 1) << 32)
+
+#define PN8_STA_CFID(x) ((x) & 0x3f)
+#define PN8_STA_SFID(x) (((x) >> 8) & 0x3f)
+#define PN8_STA_MFID(x) (((x) >> 16) & 0x3f)
+#define PN8_STA_PENDING(x) (((x) >> 31) & 0x01)
+#define PN8_STA_CVID(x) (((x) >> 32) & 0x1f)
+#define PN8_STA_SVID(x) (((x) >> 40) & 0x1f)
+#define PN8_STA_MVID(x) (((x) >> 48) & 0x1f)
+
+#define COUNT_OFF_IRT(irt) DELAY(10 * (1 << (irt)))
+#define COUNT_OFF_VST(vst) DELAY(20 * (vst))
+
+#define FID_TO_VCO_FID(fid) \
+ (((fid) < 8) ? (8 + ((fid) << 1)) : (fid))
+
+/* Reserved1 to powernow k8 configuration */
+#define PN8_PSB_TO_RVO(x) ((x) & 0x03)
+#define PN8_PSB_TO_IRT(x) (((x) >> 2) & 0x03)
+#define PN8_PSB_TO_MVS(x) (((x) >> 4) & 0x03)
+#define PN8_PSB_TO_BATT(x) (((x) >> 6) & 0x03)
+
+#define POWERNOW_MAX_STATES 16
+
+struct powernow_state {
+ int freq;
+ uint8_t fid;
+ uint8_t vid;
+};
+
+struct powernow_cpu_state {
+ struct powernow_state state_table[POWERNOW_MAX_STATES];
+ unsigned int fsb;
+ unsigned int n_states;
+ unsigned int sgtc;
+ unsigned int vst;
+ unsigned int mvs;
+ unsigned int pll;
+ unsigned int rvo;
+ unsigned int irt;
+ int low;
+};
+
+struct powernow_psb_s {
+ char signature[10]; /* AMDK7PNOW! */
+ uint8_t version;
+ uint8_t flags;
+ uint16_t ttime; /* Min settling time */
+ uint8_t reserved;
+ uint8_t n_pst;
+};
+
+struct powernow_pst_s {
+ uint32_t signature;
+ uint8_t pll;
+ uint8_t fid;
+ uint8_t vid;
+ uint8_t n_states;
+};
+
+#endif /* !_X86_POWERNOW_H */
--- /dev/null
+/* $NetBSD: psl.h,v 1.8 2012/10/04 21:23:45 dsl Exp $ */
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)psl.h 5.2 (Berkeley) 1/18/91
+ */
+
+#ifndef _X86_PSL_H_
+#define _X86_PSL_H_
+
+/*
+ * 386 processor status longword.
+ */
+#define PSL_C 0x00000001 /* carry flag */
+#define PSL_PF 0x00000004 /* parity flag */
+#define PSL_AF 0x00000010 /* auxiliary carry flag */
+#define PSL_Z 0x00000040 /* zero flag */
+#define PSL_N 0x00000080 /* sign flag */
+#define PSL_T 0x00000100 /* trap flag */
+#define PSL_I 0x00000200 /* interrupt enable flag */
+#define PSL_D 0x00000400 /* direction flag */
+#define PSL_V 0x00000800 /* overflow flag */
+#define PSL_IOPL 0x00003000 /* i/o privilege level */
+#define PSL_NT 0x00004000 /* nested task */
+#define PSL_RF 0x00010000 /* resume flag */
+#define PSL_VM 0x00020000 /* virtual 8086 mode */
+#define PSL_AC 0x00040000 /* alignment check flag */
+#define PSL_VIF 0x00080000 /* virtual interrupt enable flag */
+#define PSL_VIP 0x00100000 /* virtual interrupt pending flag */
+#define PSL_ID 0x00200000 /* identification flag */
+
+#define PSL_MBO 0x00000002 /* must be one bits */
+#define PSL_MBZ 0xffc08028 /* must be zero bits */
+
+#define PSL_USERSET (PSL_MBO | PSL_I)
+#ifdef i386
+#if defined(_KERNEL_OPT)
+#include "opt_vm86.h"
+#endif
+#endif
+#ifdef VM86
+#define PSL_USERSTATIC (PSL_MBO | PSL_MBZ | PSL_I | PSL_IOPL | PSL_NT | PSL_VIF | PSL_VIP)
+#else
+#define PSL_USERSTATIC (PSL_MBO | PSL_MBZ | PSL_I | PSL_IOPL | PSL_NT | PSL_VM | PSL_VIF | PSL_VIP)
+#endif
+#define PSL_USER (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | \
+ PSL_T | PSL_V | PSL_D | PSL_AC)
+#define PSL_CLEARSIG (PSL_T | PSL_VM | PSL_AC | PSL_D)
+
+
+/*
+ * ???
+ */
+#ifdef _KERNEL
+#include <machine/intr.h>
+#endif
+
+#endif /* !_X86_PSL_H_ */
--- /dev/null
+/* $NetBSD: pte.h,v 1.1 2010/07/06 20:50:35 cegger Exp $ */
+
+/*
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Christoph Egger.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_PTE_H
+#define _X86_PTE_H
+
+/* Cacheability bits when we are using PAT */
+#define PGC_WB 0 /* The default */
+#define PGC_WC PG_WT /* WT and CD is WC */
+#define PGC_UCMINUS PG_N /* UC but mtrr can override */
+#define PGC_UC (PG_WT | PG_N) /* hard UC */
+
+/*
+ * page protection exception bits
+ */
+
+#define PGEX_P 0x01 /* protection violation (vs. no mapping) */
+#define PGEX_W 0x02 /* exception during a write cycle */
+#define PGEX_U 0x04 /* exception while in user mode (upl) */
+#define PGEX_X 0x10 /* exception during instruction fetch */
+
+#endif /* _X86_PTE_H */
--- /dev/null
+/* $NetBSD: rtc.h,v 1.1 2009/06/16 21:05:34 bouyer Exp $ */
+
+#include <dev/clock_subr.h>
+
+void rtc_register(void);
+int rtc_get_ymdhms(todr_chip_handle_t, struct clock_ymdhms *);
+int rtc_set_ymdhms(todr_chip_handle_t, struct clock_ymdhms *);
--- /dev/null
+/* $NetBSD: smbiosvar.h,v 1.3 2008/04/16 16:06:51 cegger Exp $ */
+/*
+ * Copyright (c) 2006 Gordon Willem Klok <gklok@cogeco.ca>
+ * Copyright (c) 2005 Jordan Hargrave
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#ifndef _I386_SMBIOSVAR_
+#define _I386_SMBIOSVAR_
+
+#define SMBIOS_START 0xf0000
+#define SMBIOS_END 0xfffff
+
+#define SMBIOS_UUID_NPRESENT 0x1
+#define SMBIOS_UUID_NSET 0x2
+
+/*
+ * Section 3.5 of "UUIDs and GUIDs" found at
+ * http://www.opengroup.org/dce/info/draft-leach-uuids-guids-01.txt
+ * specifies the string repersentation of a UUID.
+ */
+#define SMBIOS_UUID_REP "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x"
+#define SMBIOS_UUID_REPLEN 37 /* 16 zero padded values, 4 hyphens, 1 null */
+
+struct smbios_entry {
+ uint8_t mjr;
+ uint8_t min;
+ uint8_t *addr;
+ uint16_t len;
+ uint16_t count;
+};
+
+struct smbhdr {
+ uint32_t sig; /* "_SM_" */
+ uint8_t checksum; /* Entry point checksum */
+ uint8_t len; /* Entry point structure length */
+ uint8_t majrev; /* Specification major revision */
+ uint8_t minrev; /* Specification minor revision */
+ uint16_t mss; /* Maximum Structure Size */
+ uint8_t epr; /* Entry Point Revision */
+ uint8_t fa[5]; /* value determined by EPR */
+ uint8_t sasig[5]; /* Secondary Anchor "_DMI_" */
+ uint8_t sachecksum; /* Secondary Checksum */
+ uint16_t size; /* Length of structure table in bytes */
+ uint32_t addr; /* Structure table address */
+ uint16_t count; /* Number of SMBIOS structures */
+ uint8_t rev; /* BCD revision */
+} __packed;
+
+struct smbtblhdr {
+ uint8_t type;
+ uint8_t size;
+ uint16_t handle;
+} __packed;
+
+struct smbtable {
+ struct smbtblhdr *hdr;
+ void *tblhdr;
+ uint32_t cookie;
+};
+
+#define SMBIOS_TYPE_BIOS 0
+#define SMBIOS_TYPE_SYSTEM 1
+#define SMBIOS_TYPE_BASEBOARD 2
+#define SMBIOS_TYPE_ENCLOSURE 3
+#define SMBIOS_TYPE_PROCESSOR 4
+#define SMBIOS_TYPE_MEMCTRL 5
+#define SMBIOS_TYPE_MEMMOD 6
+#define SMBIOS_TYPE_CACHE 7
+#define SMBIOS_TYPE_PORT 8
+#define SMBIOS_TYPE_SLOTS 9
+#define SMBIOS_TYPE_OBD 10
+#define SMBIOS_TYPE_OEM 11
+#define SMBIOS_TYPE_SYSCONFOPT 12
+#define SMBIOS_TYPE_BIOSLANG 13
+#define SMBIOS_TYPE_GROUPASSOC 14
+#define SMBIOS_TYPE_SYSEVENTLOG 15
+#define SMBIOS_TYPE_PHYMEM 16
+#define SMBIOS_TYPE_MEMDEV 17
+#define SMBIOS_TYPE_ECCINFO32 18
+#define SMBIOS_TYPE_MEMMAPARRAYADDR 19
+#define SMBIOS_TYPE_MEMMAPDEVADDR 20
+#define SMBIOS_TYPE_INBUILTPOINT 21
+#define SMBIOS_TYPE_PORTBATT 22
+#define SMBIOS_TYPE_SYSRESET 23
+#define SMBIOS_TYPE_HWSECUIRTY 24
+#define SMBIOS_TYPE_PWRCTRL 25
+#define SMBIOS_TYPE_VOLTPROBE 26
+#define SMBIOS_TYPE_COOLING 27
+#define SMBIOS_TYPE_TEMPPROBE 28
+#define SMBIOS_TYPE_CURRENTPROBE 29
+#define SMBIOS_TYPE_OOB_REMOTEACCESS 30
+#define SMBIOS_TYPE_BIS 31
+#define SMBIOS_TYPE_SBI 32
+#define SMBIOS_TYPE_ECCINFO64 33
+#define SMBIOS_TYPE_MGMTDEV 34
+#define SMBIOS_TYPE_MGTDEVCOMP 35
+#define SMBIOS_TYPE_MGTDEVTHRESH 36
+#define SMBIOS_TYPE_MEMCHANNEL 37
+#define SMBIOS_TYPE_IPMIDEV 38
+#define SMBIOS_TYPE_SPS 39
+#define SMBIOS_TYPE_INACTIVE 126
+#define SMBIOS_TYPE_EOT 127
+
+/*
+ * SMBIOS Structure Type 0 "BIOS Information"
+ * DMTF Specification DSP0134 Section: 3.3.1 p.g. 34
+ */
+struct smbios_struct_bios {
+ uint8_t vendor; /* string */
+ uint8_t version; /* string */
+ uint16_t startaddr;
+ uint8_t release; /* string */
+ uint8_t romsize;
+ uint64_t characteristics;
+ uint32_t charext;
+ uint8_t major_rel;
+ uint8_t minor_rel;
+ uint8_t ecf_mjr_rel; /* embedded controler firmware */
+ uint8_t ecf_min_rel; /* embedded controler firmware */
+} __packed;
+
+/*
+ * SMBIOS Structure Type 1 "System Information"
+ * DMTF Specification DSP0134 Section 3.3.2 p.g. 35
+ */
+
+struct smbios_sys {
+/* SMBIOS spec 2.0+ */
+ uint8_t vendor; /* string */
+ uint8_t product; /* string */
+ uint8_t version; /* string */
+ uint8_t serial; /* string */
+/* SMBIOS spec 2.1+ */
+ uint8_t uuid[16];
+ uint8_t wakeup;
+/* SMBIOS spec 2.4+ */
+ uint8_t sku; /* string */
+ uint8_t family; /* string */
+} __packed;
+
+/*
+ * SMBIOS Structure Type 2 "Base Board (Module) Information"
+ * DMTF Specification DSP0134 Section 3.3.3 p.g. 37
+ */
+struct smbios_board {
+ uint8_t vendor; /* string */
+ uint8_t product; /* string */
+ uint8_t version; /* string */
+ uint8_t serial; /* string */
+ uint8_t asset; /* stirng */
+ uint8_t feature; /* feature flags */
+ uint8_t location; /* location in chassis */
+ uint16_t handle; /* chassis handle */
+ uint8_t type; /* board type */
+ uint8_t noc; /* number of contained objects */
+} __packed;
+
+/*
+ * SMBIOS Structure Type 9 "Expansion slot"
+ */
+struct smbios_slot {
+ uint8_t designation;
+ uint8_t type;
+ uint8_t width;
+ uint8_t usage;
+ uint8_t length;
+ uint8_t slotid[2];
+ uint8_t characteristics[2];
+} __packed;
+
+#define SMBIOS_SLOT_ISA 0x03
+#define SMBIOS_SLOT_EISA 0x05
+
+/*
+ * SMBIOS Structure Type 38 "IPMI Information"
+ * DMTF Specification DSP0134 Section 3.3.39 p.g. 91
+ */
+struct smbios_ipmi {
+ uint8_t smipmi_if_type; /* IPMI Interface Type */
+ uint8_t smipmi_if_rev; /* BCD IPMI Revision */
+ uint8_t smipmi_i2c_address; /* I2C address of BMC */
+ uint8_t smipmi_nvram_address; /* I2C address of NVRAM
+ * storage */
+ uint64_t smipmi_base_address; /* Base address of BMC (BAR
+ * format */
+ uint8_t smipmi_base_flags; /* Flags field:
+ * bit 7:6 : register spacing
+ * 00 = byte
+ * 01 = dword
+ * 02 = word
+ * bit 4 : Lower bit BAR
+ * bit 3 : IRQ valid
+ * bit 2 : N/A
+ * bit 1 : Interrupt polarity
+ * bit 0 : Interrupt trigger */
+ uint8_t smipmi_irq; /* IRQ if applicable */
+} __packed;
+
+int smbios_find_table(uint8_t, struct smbtable *);
+char *smbios_get_string(struct smbtable *, uint8_t, char *, size_t);
+
+#endif
--- /dev/null
+/* $NetBSD: specialreg.h,v 1.59 2012/05/05 15:08:29 jym Exp $ */
+
+/*-
+ * Copyright (c) 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)specialreg.h 7.1 (Berkeley) 5/9/91
+ */
+
+/*
+ * Bits in 386 special registers:
+ */
+#define CR0_PE 0x00000001 /* Protected mode Enable */
+#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
+#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
+#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
+#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
+#define CR0_PG 0x80000000 /* PaGing enable */
+
+/*
+ * Bits in 486 special registers:
+ */
+#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
+#define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
+#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
+#define CR0_NW 0x20000000 /* Not Write-through */
+#define CR0_CD 0x40000000 /* Cache Disable */
+
+/*
+ * Cyrix 486 DLC special registers, accessible as IO ports.
+ */
+#define CCR0 0xc0 /* configuration control register 0 */
+#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
+#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
+#define CCR0_A20M 0x04 /* enables A20M# input pin */
+#define CCR0_KEN 0x08 /* enables KEN# input pin */
+#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
+#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
+#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
+#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
+
+#define CCR1 0xc1 /* configuration control register 1 */
+#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
+/* the remaining 7 bits of this register are reserved */
+
+/*
+ * bits in the %cr4 control register:
+ */
+#define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
+#define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
+#define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */
+#define CR4_DE 0x00000008 /* debugging extension */
+#define CR4_PSE 0x00000010 /* large (4MB) page size enable */
+#define CR4_PAE 0x00000020 /* physical address extension enable */
+#define CR4_MCE 0x00000040 /* machine check enable */
+#define CR4_PGE 0x00000080 /* page global enable */
+#define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
+#define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
+#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define CR4_VMXE 0x00002000 /* enable VMX operations */
+#define CR4_SMXE 0x00004000 /* enable SMX operations */
+#define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */
+#define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */
+#define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
+#define CR4_SMEP 0x00100000 /* enable SMEP support */
+
+
+/*
+ * CPUID "features" bits
+ */
+
+/* Fn00000001 %edx features */
+#define CPUID_FPU 0x00000001 /* processor has an FPU? */
+#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
+#define CPUID_DE 0x00000004 /* has debugging extension */
+#define CPUID_PSE 0x00000008 /* has page 4MB page size extension */
+#define CPUID_TSC 0x00000010 /* has time stamp counter */
+#define CPUID_MSR 0x00000020 /* has mode specific registers */
+#define CPUID_PAE 0x00000040 /* has phys address extension */
+#define CPUID_MCE 0x00000080 /* has machine check exception */
+#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
+#define CPUID_APIC 0x00000200 /* has enabled APIC */
+#define CPUID_B10 0x00000400 /* reserved, MTRR */
+#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
+#define CPUID_MTRR 0x00001000 /* has memory type range register */
+#define CPUID_PGE 0x00002000 /* has page global extension */
+#define CPUID_MCA 0x00004000 /* has machine check architecture */
+#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
+#define CPUID_PAT 0x00010000 /* Page Attribute Table */
+#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
+#define CPUID_PN 0x00040000 /* processor serial number */
+#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
+#define CPUID_B20 0x00100000 /* reserved */
+#define CPUID_DS 0x00200000 /* Debug Store */
+#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
+#define CPUID_MMX 0x00800000 /* MMX supported */
+#define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
+#define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
+#define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
+#define CPUID_SS 0x08000000 /* self-snoop */
+#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
+#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
+#define CPUID_IA64 0x40000000 /* IA-64 architecture */
+#define CPUID_SBF 0x80000000 /* signal break on FERR */
+
+#define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE\10MCE\11CX8" \
+ "\12APIC\13B10\14SEP\15MTRR\16PGE\17MCA\20CMOV" \
+ "\21PAT\22PSE36\23PN\24CFLUSH\25B20\26DS\27ACPI" \
+ "\30MMX\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM" \
+ "\37IA64\40SBF"
+
+/*
+ * Intel Digital Thermal Sensor and
+ * Power Management, Fn0000_0006 - %eax.
+ */
+#define CPUID_DSPM_DTS 0x00000001 /* Digital Thermal Sensor */
+#define CPUID_DSPM_IDA 0x00000002 /* Intel Dynamic Acceleration */
+#define CPUID_DSPM_ARAT 0x00000004 /* Always Running APIC Timer */
+#define CPUID_DSPM_PLN 0x00000010 /* Power Limit Notification */
+#define CPUID_DSPM_CME 0x00000020 /* Clock Modulation Extension */
+#define CPUID_DSPM_PLTM 0x00000040 /* Package Level Thermal Management */
+
+#define CPUID_DSPM_FLAGS "\20\1DTS\2IDA\3ARAT\5PLN\6CME\7PLTM"
+
+/*
+ * Intel Digital Thermal Sensor and
+ * Power Management, Fn0000_0006 - %ecx.
+ */
+#define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */
+
+#define CPUID_DSPM_FLAGS1 "\20\1HWF"
+
+/* Intel Fn80000001 extended features - %edx */
+#define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */
+#define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */
+#define CPUID_EM64T 0x20000000 /* Intel EM64T */
+
+#define CPUID_INTEL_EXT_FLAGS "\20\14SYSCALL/SYSRET\25XD\36EM64T"
+
+/* Intel Fn80000001 extended features - %ecx */
+#define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/
+
+#define CPUID_INTEL_FLAGS4 "\20\1LAHF\02B02\03B03"
+
+
+/* AMD/VIA Fn80000001 extended features - %edx */
+/* CPUID_SYSCALL SYSCALL/SYSRET */
+#define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
+#define CPUID_NOX 0x00100000 /* No Execute Page Protection */
+#define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
+#define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */
+#define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */
+#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
+/* CPUID_EM64T Long mode */
+#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
+#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
+
+#define CPUID_EXT_FLAGS "\20\14SYSCALL/SYSRET\24MPC\25NOX" \
+ "\27MXX\32FFXSR\33P1GB\34RDTSCP" \
+ "\36LONG\0373DNOW2\0403DNOW" \
+
+/* AMD Fn80000001 extended features - %ecx */
+/* CPUID_LAHF LAHF/SAHF instruction */
+#define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */
+#define CPUID_SVM 0x00000004 /* Secure Virtual Machine */
+#define CPUID_EAPIC 0x00000008 /* Extended APIC space */
+#define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */
+#define CPUID_LZCNT 0x00000020 /* LZCNT instruction */
+#define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */
+#define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */
+#define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */
+#define CPUID_OSVW 0x00000200 /* OS visible workarounds */
+#define CPUID_IBS 0x00000400 /* Instruction Based Sampling */
+#define CPUID_XOP 0x00000800 /* XOP instruction set */
+#define CPUID_SKINIT 0x00001000 /* SKINIT */
+#define CPUID_WDT 0x00002000 /* watchdog timer support */
+#define CPUID_LWP 0x00008000 /* Light Weight Profiling */
+#define CPUID_FMA4 0x00010000 /* FMA4 instructions */
+#define CPUID_NODEID 0x00080000 /* NodeID MSR available*/
+#define CPUID_TBM 0x00200000 /* TBM instructions */
+#define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */
+
+#define CPUID_AMD_FLAGS4 "\20\1LAHF\2CMPLEGACY\3SVM\4EAPIC\5ALTMOVCR0" \
+ "\6LZCNT\7SSE4A\10MISALIGNSSE" \
+ "\0113DNOWPREFETCH\12OSVW\13IBS" \
+ "\14XOP\15SKINIT\16WDT\20LWP" \
+ "\21FMA4\22B17\23B18\24NodeID\25B20\26TBM" \
+ "\27TopoExt\30B23\31B24" \
+ "\32B25\33B25\34B26" \
+ "\35B27\36B28\37B29\40B30\41B31\42B32"
+
+/* AMD Fn8000000a %edx features (SVM features) */
+#define CPUID_AMD_SVM_NP 0x00000001
+#define CPUID_AMD_SVM_LbrVirt 0x00000002
+#define CPUID_AMD_SVM_SVML 0x00000004
+#define CPUID_AMD_SVM_NRIPS 0x00000008
+#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
+#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
+#define CPUID_AMD_SVM_FlushByASID 0x00000040
+#define CPUID_AMD_SVM_DecodeAssist 0x00000080
+#define CPUID_AMD_SVM_PauseFilter 0x00000400
+#define CPUID_AMD_SVM_FLAGS "\20\1NP\2LbrVirt\3SVML\4NRIPS" \
+ "\5TSCRate\6VMCBCleanBits\7FlushByASID" \
+ "\10DecodeAssist\11B08" \
+ "\12B09\13PauseFilter" \
+ "\14B11\15B12" \
+ "\16B13\17B17\20B18\21B19"
+
+/*
+ * AMD Advanced Power Management
+ * CPUID Fn8000_0007 %edx
+ */
+#define CPUID_APM_TS 0x00000001 /* Temperature Sensor */
+#define CPUID_APM_FID 0x00000002 /* Frequency ID control */
+#define CPUID_APM_VID 0x00000004 /* Voltage ID control */
+#define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */
+#define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */
+#define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */
+#define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */
+#define CPUID_APM_HWP 0x00000080 /* HW P-State control */
+#define CPUID_APM_TSC 0x00000100 /* TSC invariant */
+#define CPUID_APM_CPB 0x00000200 /* Core performance boost */
+#define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */
+
+#define CPUID_APM_FLAGS "\20\1TS\2FID\3VID\4TTP\5HTC\6STC\007100" \
+ "\10HWP\11TSC\12CPB\13EffFreq\14B11\15B12"
+
+/*
+ * Centaur Extended Feature flags
+ */
+#define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */
+#define CPUID_VIA_DO_RNG 0x00000008
+#define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */
+#define CPUID_VIA_DO_ACE 0x00000080
+#define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */
+#define CPUID_VIA_DO_ACE2 0x00000200
+#define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */
+#define CPUID_VIA_DO_PHE 0x00000800
+#define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */
+#define CPUID_VIA_DO_PMM 0x00002000
+
+#define CPUID_FLAGS_PADLOCK "\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA"
+
+/*
+ * CPUID "features" bits in Fn00000001 %ecx
+ */
+
+#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
+#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
+#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
+#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
+#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
+#define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
+#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
+#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
+#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
+#define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */
+#define CPUID2_CID 0x00000400 /* Context ID */
+#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
+#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
+#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
+#define CPUID2_PCID 0x00020000 /* Process Context ID */
+#define CPUID2_DCA 0x00040000 /* Direct Cache Access */
+#define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
+#define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
+#define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
+#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
+#define CPUID2_AES 0x02000000 /* AES instructions */
+#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
+#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
+#define CPUID2_AVX 0x10000000 /* AVX instructions */
+#define CPUID2_F16C 0x20000000 /* half precision conversion */
+#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
+
+#define CPUID2_FLAGS1 "\20\1SSE3\2PCLMULQDQ\3DTES64\4MONITOR\5DS-CPL\6VMX\7SMX" \
+ "\10EST\11TM2\12SSSE3\13CID\14B11\15B12\16CX16" \
+ "\17xTPR\20PDCM\21B16\22PCID\23DCA\24SSE41\25SSE42" \
+ "\26X2APIC\27MOVBE\30POPCNT\31B24\32AES\33XSAVE" \
+ "\34OSXSAVE\35AVX\36F16C\37B30\40RAZ"
+
+#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)
+#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)
+#define CPUID2STEPPING(cpuid) ((cpuid) & 0xf)
+
+/* Extended family and model are defined on amd64 processors */
+#define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
+#define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
+
+/* Blacklists of CPUID flags - used to mask certain features */
+#ifdef XEN
+/* Not on Xen */
+#define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
+#else
+#define CPUID_FEAT_BLACKLIST 0
+#endif /* XEN */
+
+/*
+ * Model-specific registers for the i386 family
+ */
+#define MSR_P5_MC_ADDR 0x000 /* P5 only */
+#define MSR_P5_MC_TYPE 0x001 /* P5 only */
+#define MSR_TSC 0x010
+#define MSR_CESR 0x011 /* P5 only (trap on P6) */
+#define MSR_CTR0 0x012 /* P5 only (trap on P6) */
+#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
+#define MSR_APICBASE 0x01b
+#define MSR_EBL_CR_POWERON 0x02a
+#define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */
+#define MSR_TEST_CTL 0x033
+#define MSR_BIOS_UPDT_TRIG 0x079
+#define MSR_BBL_CR_D0 0x088 /* PII+ only */
+#define MSR_BBL_CR_D1 0x089 /* PII+ only */
+#define MSR_BBL_CR_D2 0x08a /* PII+ only */
+#define MSR_BIOS_SIGN 0x08b
+#define MSR_PERFCTR0 0x0c1
+#define MSR_PERFCTR1 0x0c2
+#define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */
+#define MSR_MPERF 0x0e7
+#define MSR_APERF 0x0e8
+#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
+#define MSR_MTRRcap 0x0fe
+#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
+#define MSR_BBL_CR_DECC 0x118 /* PII+ only */
+#define MSR_BBL_CR_CTL 0x119 /* PII+ only */
+#define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
+#define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
+#define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
+#define MSR_SYSENTER_CS 0x174 /* PII+ only */
+#define MSR_SYSENTER_ESP 0x175 /* PII+ only */
+#define MSR_SYSENTER_EIP 0x176 /* PII+ only */
+#define MSR_MCG_CAP 0x179
+#define MSR_MCG_STATUS 0x17a
+#define MSR_MCG_CTL 0x17b
+#define MSR_EVNTSEL0 0x186
+#define MSR_EVNTSEL1 0x187
+#define MSR_PERF_STATUS 0x198 /* Pentium M */
+#define MSR_PERF_CTL 0x199 /* Pentium M */
+#define MSR_THERM_CONTROL 0x19a
+#define MSR_THERM_INTERRUPT 0x19b
+#define MSR_THERM_STATUS 0x19c
+#define MSR_THERM2_CTL 0x19d /* Pentium M */
+#define MSR_MISC_ENABLE 0x1a0
+#define MSR_TEMPERATURE_TARGET 0x1a2
+#define MSR_DEBUGCTLMSR 0x1d9
+#define MSR_LASTBRANCHFROMIP 0x1db
+#define MSR_LASTBRANCHTOIP 0x1dc
+#define MSR_LASTINTFROMIP 0x1dd
+#define MSR_LASTINTTOIP 0x1de
+#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
+#define MSR_MTRRphysBase0 0x200
+#define MSR_MTRRphysMask0 0x201
+#define MSR_MTRRphysBase1 0x202
+#define MSR_MTRRphysMask1 0x203
+#define MSR_MTRRphysBase2 0x204
+#define MSR_MTRRphysMask2 0x205
+#define MSR_MTRRphysBase3 0x206
+#define MSR_MTRRphysMask3 0x207
+#define MSR_MTRRphysBase4 0x208
+#define MSR_MTRRphysMask4 0x209
+#define MSR_MTRRphysBase5 0x20a
+#define MSR_MTRRphysMask5 0x20b
+#define MSR_MTRRphysBase6 0x20c
+#define MSR_MTRRphysMask6 0x20d
+#define MSR_MTRRphysBase7 0x20e
+#define MSR_MTRRphysMask7 0x20f
+#define MSR_MTRRphysBase8 0x210
+#define MSR_MTRRphysMask8 0x211
+#define MSR_MTRRphysBase9 0x212
+#define MSR_MTRRphysMask9 0x213
+#define MSR_MTRRphysBase10 0x214
+#define MSR_MTRRphysMask10 0x215
+#define MSR_MTRRphysBase11 0x216
+#define MSR_MTRRphysMask11 0x217
+#define MSR_MTRRphysBase12 0x218
+#define MSR_MTRRphysMask12 0x219
+#define MSR_MTRRphysBase13 0x21a
+#define MSR_MTRRphysMask13 0x21b
+#define MSR_MTRRphysBase14 0x21c
+#define MSR_MTRRphysMask14 0x21d
+#define MSR_MTRRphysBase15 0x21e
+#define MSR_MTRRphysMask15 0x21f
+#define MSR_MTRRfix64K_00000 0x250
+#define MSR_MTRRfix16K_80000 0x258
+#define MSR_MTRRfix16K_A0000 0x259
+#define MSR_MTRRfix4K_C0000 0x268
+#define MSR_MTRRfix4K_C8000 0x269
+#define MSR_MTRRfix4K_D0000 0x26a
+#define MSR_MTRRfix4K_D8000 0x26b
+#define MSR_MTRRfix4K_E0000 0x26c
+#define MSR_MTRRfix4K_E8000 0x26d
+#define MSR_MTRRfix4K_F0000 0x26e
+#define MSR_MTRRfix4K_F8000 0x26f
+#define MSR_CR_PAT 0x277
+#define MSR_MTRRdefType 0x2ff
+#define MSR_MC0_CTL 0x400
+#define MSR_MC0_STATUS 0x401
+#define MSR_MC0_ADDR 0x402
+#define MSR_MC0_MISC 0x403
+#define MSR_MC1_CTL 0x404
+#define MSR_MC1_STATUS 0x405
+#define MSR_MC1_ADDR 0x406
+#define MSR_MC1_MISC 0x407
+#define MSR_MC2_CTL 0x408
+#define MSR_MC2_STATUS 0x409
+#define MSR_MC2_ADDR 0x40a
+#define MSR_MC2_MISC 0x40b
+#define MSR_MC4_CTL 0x40c
+#define MSR_MC4_STATUS 0x40d
+#define MSR_MC4_ADDR 0x40e
+#define MSR_MC4_MISC 0x40f
+#define MSR_MC3_CTL 0x410
+#define MSR_MC3_STATUS 0x411
+#define MSR_MC3_ADDR 0x412
+#define MSR_MC3_MISC 0x413
+ /* 0x480 - 0x490 VMX */
+
+/*
+ * VIA "Nehemiah" MSRs
+ */
+#define MSR_VIA_RNG 0x0000110b
+#define MSR_VIA_RNG_ENABLE 0x00000040
+#define MSR_VIA_RNG_NOISE_MASK 0x00000300
+#define MSR_VIA_RNG_NOISE_A 0x00000000
+#define MSR_VIA_RNG_NOISE_B 0x00000100
+#define MSR_VIA_RNG_2NOISE 0x00000300
+#define MSR_VIA_ACE 0x00001107
+#define MSR_VIA_ACE_ENABLE 0x10000000
+
+/*
+ * VIA "Eden" MSRs
+ */
+#define MSR_VIA_FCR MSR_VIA_ACE
+
+/*
+ * AMD K6/K7 MSRs.
+ */
+#define MSR_K6_UWCCR 0xc0000085
+#define MSR_K7_EVNTSEL0 0xc0010000
+#define MSR_K7_EVNTSEL1 0xc0010001
+#define MSR_K7_EVNTSEL2 0xc0010002
+#define MSR_K7_EVNTSEL3 0xc0010003
+#define MSR_K7_PERFCTR0 0xc0010004
+#define MSR_K7_PERFCTR1 0xc0010005
+#define MSR_K7_PERFCTR2 0xc0010006
+#define MSR_K7_PERFCTR3 0xc0010007
+
+/*
+ * AMD K8 (Opteron) MSRs.
+ */
+#define MSR_SYSCFG 0xc0000010
+
+#define MSR_EFER 0xc0000080 /* Extended feature enable */
+#define EFER_SCE 0x00000001 /* SYSCALL extension */
+#define EFER_LME 0x00000100 /* Long Mode Active */
+#define EFER_LMA 0x00000400 /* Long Mode Enabled */
+#define EFER_NXE 0x00000800 /* No-Execute Enabled */
+
+#define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
+#define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
+#define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */
+#define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */
+
+#define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */
+#define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */
+#define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */
+
+#define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */
+#define VMCR_DPD 0x00000001 /* Debug port disable */
+#define VMCR_RINIT 0x00000002 /* intercept init */
+#define VMCR_DISA20 0x00000004 /* Disable A20 masking */
+#define VMCR_LOCK 0x00000008 /* SVM Lock */
+#define VMCR_SVMED 0x00000010 /* SVME Disable */
+#define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */
+
+/*
+ * These require a 'passcode' for access. See cpufunc.h.
+ */
+#define MSR_HWCR 0xc0010015
+#define HWCR_TLBCACHEDIS 0x00000008
+#define HWCR_FFDIS 0x00000040
+
+#define MSR_NB_CFG 0xc001001f
+#define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL
+#define NB_CFG_DISDATMSK 0x0000001000000000ULL
+#define NB_CFG_INITAPICCPUIDLO (1ULL << 54)
+
+#define MSR_LS_CFG 0xc0011020
+#define LS_CFG_DIS_LS2_SQUISH 0x02000000
+
+#define MSR_IC_CFG 0xc0011021
+#define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
+
+#define MSR_DC_CFG 0xc0011022
+#define DC_CFG_DIS_CNV_WC_SSO 0x00000008
+#define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
+#define DC_CFG_ERRATA_261 0x01000000
+
+#define MSR_BU_CFG 0xc0011023
+#define BU_CFG_ERRATA_298 0x0000000000000002ULL
+#define BU_CFG_ERRATA_254 0x0000000000200000ULL
+#define BU_CFG_ERRATA_309 0x0000000000800000ULL
+#define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
+#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
+#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
+
+#define MSR_DE_CFG 0xc0011029
+#define DE_CFG_ERRATA_721 0x00000001
+
+/* AMD Family10h MSRs */
+#define MSR_OSVW_ID_LENGTH 0xc0010140
+#define MSR_OSVW_STATUS 0xc0010141
+#define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b
+#define MSR_UCODE_AMD_PATCHLOADER 0xc0010020
+
+/* X86 MSRs */
+#define MSR_RDTSCP_AUX 0xc0000103
+
+/*
+ * Constants related to MTRRs
+ */
+#define MTRR_N64K 8 /* numbers of fixed-size entries */
+#define MTRR_N16K 16
+#define MTRR_N4K 64
+
+/*
+ * the following four 3-byte registers control the non-cacheable regions.
+ * These registers must be written as three separate bytes.
+ *
+ * NCRx+0: A31-A24 of starting address
+ * NCRx+1: A23-A16 of starting address
+ * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
+ *
+ * The non-cacheable region's starting address must be aligned to the
+ * size indicated by the NCR_SIZE_xx field.
+ */
+#define NCR1 0xc4
+#define NCR2 0xc7
+#define NCR3 0xca
+#define NCR4 0xcd
+
+#define NCR_SIZE_0K 0
+#define NCR_SIZE_4K 1
+#define NCR_SIZE_8K 2
+#define NCR_SIZE_16K 3
+#define NCR_SIZE_32K 4
+#define NCR_SIZE_64K 5
+#define NCR_SIZE_128K 6
+#define NCR_SIZE_256K 7
+#define NCR_SIZE_512K 8
+#define NCR_SIZE_1M 9
+#define NCR_SIZE_2M 10
+#define NCR_SIZE_4M 11
+#define NCR_SIZE_8M 12
+#define NCR_SIZE_16M 13
+#define NCR_SIZE_32M 14
+#define NCR_SIZE_4G 15
+
+/*
+ * Performance monitor events.
+ *
+ * Note that 586-class and 686-class CPUs have different performance
+ * monitors available, and they are accessed differently:
+ *
+ * 686-class: `rdpmc' instruction
+ * 586-class: `rdmsr' instruction, CESR MSR
+ *
+ * The descriptions of these events are too lenghy to include here.
+ * See Appendix A of "Intel Architecture Software Developer's
+ * Manual, Volume 3: System Programming" for more information.
+ */
+
+/*
+ * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits
+ * is CTR1.
+ */
+
+#define PMC5_CESR_EVENT 0x003f
+#define PMC5_CESR_OS 0x0040
+#define PMC5_CESR_USR 0x0080
+#define PMC5_CESR_E 0x0100
+#define PMC5_CESR_P 0x0200
+
+#define PMC5_DATA_READ 0x00
+#define PMC5_DATA_WRITE 0x01
+#define PMC5_DATA_TLB_MISS 0x02
+#define PMC5_DATA_READ_MISS 0x03
+#define PMC5_DATA_WRITE_MISS 0x04
+#define PMC5_WRITE_M_E 0x05
+#define PMC5_DATA_LINES_WBACK 0x06
+#define PMC5_DATA_CACHE_SNOOP 0x07
+#define PMC5_DATA_CACHE_SNOOP_HIT 0x08
+#define PMC5_MEM_ACCESS_BOTH_PIPES 0x09
+#define PMC5_BANK_CONFLICTS 0x0a
+#define PMC5_MISALIGNED_DATA 0x0b
+#define PMC5_INST_READ 0x0c
+#define PMC5_INST_TLB_MISS 0x0d
+#define PMC5_INST_CACHE_MISS 0x0e
+#define PMC5_SEGMENT_REG_LOAD 0x0f
+#define PMC5_BRANCHES 0x12
+#define PMC5_BTB_HITS 0x13
+#define PMC5_BRANCH_TAKEN 0x14
+#define PMC5_PIPELINE_FLUSH 0x15
+#define PMC5_INST_EXECUTED 0x16
+#define PMC5_INST_EXECUTED_V_PIPE 0x17
+#define PMC5_BUS_UTILIZATION 0x18
+#define PMC5_WRITE_BACKUP_STALL 0x19
+#define PMC5_DATA_READ_STALL 0x1a
+#define PMC5_WRITE_E_M_STALL 0x1b
+#define PMC5_LOCKED_BUS 0x1c
+#define PMC5_IO_CYCLE 0x1d
+#define PMC5_NONCACHE_MEM_READ 0x1e
+#define PMC5_AGI_STALL 0x1f
+#define PMC5_FLOPS 0x22
+#define PMC5_BP0_MATCH 0x23
+#define PMC5_BP1_MATCH 0x24
+#define PMC5_BP2_MATCH 0x25
+#define PMC5_BP3_MATCH 0x26
+#define PMC5_HARDWARE_INTR 0x27
+#define PMC5_DATA_RW 0x28
+#define PMC5_DATA_RW_MISS 0x29
+
+/*
+ * 686-class Event Selector MSR format.
+ */
+
+#define PMC6_EVTSEL_EVENT 0x000000ff
+#define PMC6_EVTSEL_UNIT 0x0000ff00
+#define PMC6_EVTSEL_UNIT_SHIFT 8
+#define PMC6_EVTSEL_USR (1 << 16)
+#define PMC6_EVTSEL_OS (1 << 17)
+#define PMC6_EVTSEL_E (1 << 18)
+#define PMC6_EVTSEL_PC (1 << 19)
+#define PMC6_EVTSEL_INT (1 << 20)
+#define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
+#define PMC6_EVTSEL_INV (1 << 23)
+#define PMC6_EVTSEL_COUNTER_MASK 0xff000000
+#define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
+
+/* Data Cache Unit */
+#define PMC6_DATA_MEM_REFS 0x43
+#define PMC6_DCU_LINES_IN 0x45
+#define PMC6_DCU_M_LINES_IN 0x46
+#define PMC6_DCU_M_LINES_OUT 0x47
+#define PMC6_DCU_MISS_OUTSTANDING 0x48
+
+/* Instruction Fetch Unit */
+#define PMC6_IFU_IFETCH 0x80
+#define PMC6_IFU_IFETCH_MISS 0x81
+#define PMC6_ITLB_MISS 0x85
+#define PMC6_IFU_MEM_STALL 0x86
+#define PMC6_ILD_STALL 0x87
+
+/* L2 Cache */
+#define PMC6_L2_IFETCH 0x28
+#define PMC6_L2_LD 0x29
+#define PMC6_L2_ST 0x2a
+#define PMC6_L2_LINES_IN 0x24
+#define PMC6_L2_LINES_OUT 0x26
+#define PMC6_L2_M_LINES_INM 0x25
+#define PMC6_L2_M_LINES_OUTM 0x27
+#define PMC6_L2_RQSTS 0x2e
+#define PMC6_L2_ADS 0x21
+#define PMC6_L2_DBUS_BUSY 0x22
+#define PMC6_L2_DBUS_BUSY_RD 0x23
+
+/* External Bus Logic */
+#define PMC6_BUS_DRDY_CLOCKS 0x62
+#define PMC6_BUS_LOCK_CLOCKS 0x63
+#define PMC6_BUS_REQ_OUTSTANDING 0x60
+#define PMC6_BUS_TRAN_BRD 0x65
+#define PMC6_BUS_TRAN_RFO 0x66
+#define PMC6_BUS_TRANS_WB 0x67
+#define PMC6_BUS_TRAN_IFETCH 0x68
+#define PMC6_BUS_TRAN_INVAL 0x69
+#define PMC6_BUS_TRAN_PWR 0x6a
+#define PMC6_BUS_TRANS_P 0x6b
+#define PMC6_BUS_TRANS_IO 0x6c
+#define PMC6_BUS_TRAN_DEF 0x6d
+#define PMC6_BUS_TRAN_BURST 0x6e
+#define PMC6_BUS_TRAN_ANY 0x70
+#define PMC6_BUS_TRAN_MEM 0x6f
+#define PMC6_BUS_DATA_RCV 0x64
+#define PMC6_BUS_BNR_DRV 0x61
+#define PMC6_BUS_HIT_DRV 0x7a
+#define PMC6_BUS_HITM_DRDV 0x7b
+#define PMC6_BUS_SNOOP_STALL 0x7e
+
+/* Floating Point Unit */
+#define PMC6_FLOPS 0xc1
+#define PMC6_FP_COMP_OPS_EXE 0x10
+#define PMC6_FP_ASSIST 0x11
+#define PMC6_MUL 0x12
+#define PMC6_DIV 0x12
+#define PMC6_CYCLES_DIV_BUSY 0x14
+
+/* Memory Ordering */
+#define PMC6_LD_BLOCKS 0x03
+#define PMC6_SB_DRAINS 0x04
+#define PMC6_MISALIGN_MEM_REF 0x05
+#define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
+#define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
+
+/* Instruction Decoding and Retirement */
+#define PMC6_INST_RETIRED 0xc0
+#define PMC6_UOPS_RETIRED 0xc2
+#define PMC6_INST_DECODED 0xd0
+#define PMC6_EMON_KNI_INST_RETIRED 0xd8
+#define PMC6_EMON_KNI_COMP_INST_RET 0xd9
+
+/* Interrupts */
+#define PMC6_HW_INT_RX 0xc8
+#define PMC6_CYCLES_INT_MASKED 0xc6
+#define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
+
+/* Branches */
+#define PMC6_BR_INST_RETIRED 0xc4
+#define PMC6_BR_MISS_PRED_RETIRED 0xc5
+#define PMC6_BR_TAKEN_RETIRED 0xc9
+#define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
+#define PMC6_BR_INST_DECODED 0xe0
+#define PMC6_BTB_MISSES 0xe2
+#define PMC6_BR_BOGUS 0xe4
+#define PMC6_BACLEARS 0xe6
+
+/* Stalls */
+#define PMC6_RESOURCE_STALLS 0xa2
+#define PMC6_PARTIAL_RAT_STALLS 0xd2
+
+/* Segment Register Loads */
+#define PMC6_SEGMENT_REG_LOADS 0x06
+
+/* Clocks */
+#define PMC6_CPU_CLK_UNHALTED 0x79
+
+/* MMX Unit */
+#define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
+#define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
+#define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
+#define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
+#define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
+#define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
+#define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
+
+/* Segment Register Renaming */
+#define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
+#define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
+#define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
+
+/*
+ * AMD K7 Event Selector MSR format.
+ */
+
+#define K7_EVTSEL_EVENT 0x000000ff
+#define K7_EVTSEL_UNIT 0x0000ff00
+#define K7_EVTSEL_UNIT_SHIFT 8
+#define K7_EVTSEL_USR (1 << 16)
+#define K7_EVTSEL_OS (1 << 17)
+#define K7_EVTSEL_E (1 << 18)
+#define K7_EVTSEL_PC (1 << 19)
+#define K7_EVTSEL_INT (1 << 20)
+#define K7_EVTSEL_EN (1 << 22)
+#define K7_EVTSEL_INV (1 << 23)
+#define K7_EVTSEL_COUNTER_MASK 0xff000000
+#define K7_EVTSEL_COUNTER_MASK_SHIFT 24
+
+/* Segment Register Loads */
+#define K7_SEGMENT_REG_LOADS 0x20
+
+#define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
+
+/* Data Cache Unit */
+#define K7_DATA_CACHE_ACCESS 0x40
+#define K7_DATA_CACHE_MISS 0x41
+#define K7_DATA_CACHE_REFILL 0x42
+#define K7_DATA_CACHE_REFILL_SYSTEM 0x43
+#define K7_DATA_CACHE_WBACK 0x44
+#define K7_L2_DTLB_HIT 0x45
+#define K7_L2_DTLB_MISS 0x46
+#define K7_MISALIGNED_DATA_REF 0x47
+#define K7_SYSTEM_REQUEST 0x64
+#define K7_SYSTEM_REQUEST_TYPE 0x65
+
+#define K7_SNOOP_HIT 0x73
+#define K7_SINGLE_BIT_ECC_ERROR 0x74
+#define K7_CACHE_LINE_INVAL 0x75
+#define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76
+#define K7_L2_REQUEST 0x79
+#define K7_L2_REQUEST_BUSY 0x7a
+
+/* Instruction Fetch Unit */
+#define K7_IFU_IFETCH 0x80
+#define K7_IFU_IFETCH_MISS 0x81
+#define K7_IFU_REFILL_FROM_L2 0x82
+#define K7_IFU_REFILL_FROM_SYSTEM 0x83
+#define K7_ITLB_L1_MISS 0x84
+#define K7_ITLB_L2_MISS 0x85
+#define K7_SNOOP_RESYNC 0x86
+#define K7_IFU_STALL 0x87
+
+#define K7_RETURN_STACK_HITS 0x88
+#define K7_RETURN_STACK_OVERFLOW 0x89
+
+/* Retired */
+#define K7_RETIRED_INST 0xc0
+#define K7_RETIRED_OPS 0xc1
+#define K7_RETIRED_BRANCHES 0xc2
+#define K7_RETIRED_BRANCH_MISPREDICTED 0xc3
+#define K7_RETIRED_TAKEN_BRANCH 0xc4
+#define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5
+#define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
+#define K7_RETIRED_RESYNC_BRANCH 0xc7
+#define K7_RETIRED_NEAR_RETURNS 0xc8
+#define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9
+#define K7_RETIRED_INDIRECT_MISPREDICTED 0xca
+
+/* Interrupts */
+#define K7_CYCLES_INT_MASKED 0xcd
+#define K7_CYCLES_INT_PENDING_AND_MASKED 0xce
+#define K7_HW_INTR_RECV 0xcf
+
+#define K7_INSTRUCTION_DECODER_EMPTY 0xd0
+#define K7_DISPATCH_STALLS 0xd1
+#define K7_BRANCH_ABORTS_TO_RETIRE 0xd2
+#define K7_SERIALIZE 0xd3
+#define K7_SEGMENT_LOAD_STALL 0xd4
+#define K7_ICU_FULL 0xd5
+#define K7_RESERVATION_STATIONS_FULL 0xd6
+#define K7_FPU_FULL 0xd7
+#define K7_LS_FULL 0xd8
+#define K7_ALL_QUIET_STALL 0xd9
+#define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda
+
+#define K7_BP0_MATCH 0xdc
+#define K7_BP1_MATCH 0xdd
+#define K7_BP2_MATCH 0xde
+#define K7_BP3_MATCH 0xdf
--- /dev/null
+/* $NetBSD: sysarch.h,v 1.9 2010/07/07 01:14:53 chs Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Andrew Doran.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_SYSARCH_H_
+#define _X86_SYSARCH_H_
+
+#define X86_GET_LDT 0
+#define X86_SET_LDT 1
+#define X86_IOPL 2
+#define X86_GET_IOPERM 3
+#define X86_SET_IOPERM 4
+#define X86_OLD_VM86 5
+#define X86_PMC_INFO 8
+#define X86_PMC_STARTSTOP 9
+#define X86_PMC_READ 10
+#define X86_GET_MTRR 11
+#define X86_SET_MTRR 12
+#define X86_VM86 13
+#define X86_GET_GSBASE 14
+#define X86_GET_FSBASE 15
+#define X86_SET_GSBASE 16
+#define X86_SET_FSBASE 17
+
+#ifdef _KERNEL
+#define _X86_SYSARCH_L(x) x86_##x
+#define _X86_SYSARCH_U(x) X86_##x
+#elif defined(__i386__)
+#define _X86_SYSARCH_L(x) i386_##x
+#define _X86_SYSARCH_U(x) I386_##x
+#define I386_GET_LDT X86_GET_LDT
+#define I386_SET_LDT X86_SET_LDT
+#define I386_IOPL X86_IOPL
+#define I386_GET_IOPERM X86_GET_IOPERM
+#define I386_SET_IOPERM X86_SET_IOPERM
+#define I386_OLD_VM86 X86_OLD_VM86
+#define I386_PMC_INFO X86_PMC_INFO
+#define I386_PMC_STARTSTOP X86_PMC_STARTSTOP
+#define I386_PMC_READ X86_PMC_READ
+#define I386_GET_MTRR X86_GET_MTRR
+#define I386_SET_MTRR X86_SET_MTRR
+#define I386_VM86 X86_VM86
+#define I386_GET_GSBASE X86_GET_GSBASE
+#define I386_GET_FSBASE X86_GET_FSBASE
+#define I386_SET_GSBASE X86_SET_GSBASE
+#define I386_SET_FSBASE X86_SET_FSBASE
+#else
+#define _X86_SYSARCH_L(x) x86_64_##x
+#define _X86_SYSARCH_U(x) X86_64_##x
+#define X86_64_GET_LDT X86_GET_LDT
+#define X86_64_SET_LDT X86_SET_LDT
+#define X86_64_IOPL X86_IOPL
+#define X86_64_GET_IOPERM X86_GET_IOPERM
+#define X86_64_SET_IOPERM X86_SET_IOPERM
+#define X86_64_OLD_VM86 X86_OLD_VM86
+#define X86_64_PMC_INFO X86_PMC_INFO
+#define X86_64_PMC_STARTSTOP X86_PMC_STARTSTOP
+#define X86_64_PMC_READ X86_PMC_READ
+#define X86_64_GET_MTRR X86_GET_MTRR
+#define X86_64_SET_MTRR X86_SET_MTRR
+#define X86_64_VM86 X86_VM86
+#define X86_64_GET_GSBASE X86_GET_GSBASE
+#define X86_64_GET_FSBASE X86_GET_FSBASE
+#define X86_64_SET_GSBASE X86_SET_GSBASE
+#define X86_64_SET_FSBASE X86_SET_FSBASE
+#endif
+
+/*
+ * Architecture specific syscalls (x86)
+ */
+
+struct _X86_SYSARCH_L(get_ldt_args) {
+ int start;
+ union descriptor *desc;
+ int num;
+};
+
+struct _X86_SYSARCH_L(set_ldt_args) {
+ int start;
+ union descriptor *desc;
+ int num;
+};
+
+struct _X86_SYSARCH_L(get_mtrr_args) {
+ struct mtrr *mtrrp;
+ int *n;
+};
+
+struct _X86_SYSARCH_L(set_mtrr_args) {
+ struct mtrr *mtrrp;
+ int *n;
+};
+
+struct _X86_SYSARCH_L(iopl_args) {
+ int iopl;
+};
+
+struct _X86_SYSARCH_L(get_ioperm_args) {
+ u_long *iomap;
+};
+
+struct _X86_SYSARCH_L(set_ioperm_args) {
+ u_long *iomap;
+};
+
+struct _X86_SYSARCH_L(pmc_info_args) {
+ int type;
+ int flags;
+};
+
+#define PMC_TYPE_NONE 0
+#define PMC_TYPE_I586 1
+#define PMC_TYPE_I686 2
+#define PMC_TYPE_K7 3
+
+#define PMC_INFO_HASTSC 0x01
+
+#ifdef __i386__
+#define PMC_NCOUNTERS 4
+#else
+#define PMC_NCOUNTERS 2
+#endif
+
+struct _X86_SYSARCH_L(pmc_startstop_args) {
+ int counter;
+ uint64_t val;
+ uint8_t event;
+ uint8_t unit;
+ uint8_t compare;
+ uint8_t flags;
+};
+
+#define PMC_SETUP_KERNEL 0x01
+#define PMC_SETUP_USER 0x02
+#define PMC_SETUP_EDGE 0x04
+#define PMC_SETUP_INV 0x08
+
+struct _X86_SYSARCH_L(pmc_read_args) {
+ int counter;
+ uint64_t val;
+ uint64_t time;
+};
+
+struct mtrr;
+
+#ifdef _KERNEL
+int x86_iopl(struct lwp *, void *, register_t *);
+int x86_get_mtrr(struct lwp *, void *, register_t *);
+int x86_set_mtrr(struct lwp *, void *, register_t *);
+int x86_get_ldt(struct lwp *, void *, register_t *);
+int x86_get_ldt1(struct lwp *, struct x86_get_ldt_args *, union descriptor *);
+int x86_set_ldt(struct lwp *, void *, register_t *);
+int x86_set_ldt1(struct lwp *, struct x86_set_ldt_args *, union descriptor *);
+int x86_set_sdbase(void *, char, lwp_t *, bool);
+int x86_get_sdbase(void *, char);
+#else
+#include <sys/cdefs.h>
+__BEGIN_DECLS
+int _X86_SYSARCH_L(get_ldt)(int, union descriptor *, int);
+int _X86_SYSARCH_L(set_ldt)(int, union descriptor *, int);
+int _X86_SYSARCH_L(iopl)(int);
+int _X86_SYSARCH_L(pmc_info)(struct _X86_SYSARCH_L(pmc_info_args *));
+int _X86_SYSARCH_L(pmc_startstop)(struct _X86_SYSARCH_L(pmc_startstop_args *));
+int _X86_SYSARCH_L(pmc_read)(struct _X86_SYSARCH_L(pmc_read_args *));
+int _X86_SYSARCH_L(set_mtrr)(struct mtrr *, int *);
+int _X86_SYSARCH_L(get_mtrr)(struct mtrr *, int *);
+int sysarch(int, void *);
+__END_DECLS
+#endif
+
+#endif /* !_X86_SYSARCH_H_ */
--- /dev/null
+/* $NetBSD: tprof.h,v 1.2 2009/02/24 06:03:54 yamt Exp $ */
+
+/*-
+ * Copyright (c)2008 YAMAMOTO Takashi,
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _X86_TPROF_H_
+#define _X86_TPROF_H_
+
+/* XXX nothing */
+
+#endif /* _X86_TPROF_H_ */
--- /dev/null
+/* $NetBSD: trap.h,v 1.2 2003/08/07 16:30:33 agc Exp $ */
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)trap.h 5.4 (Berkeley) 5/9/91
+ */
+
+/*
+ * Trap type values
+ * also known in trap.c for name strings
+ */
+
+#define T_PRIVINFLT 0 /* privileged instruction */
+#define T_BPTFLT 1 /* breakpoint trap */
+#define T_ARITHTRAP 2 /* arithmetic trap */
+#define T_ASTFLT 3 /* asynchronous system trap */
+#define T_PROTFLT 4 /* protection fault */
+#define T_TRCTRAP 5 /* trace trap */
+#define T_PAGEFLT 6 /* page fault */
+#define T_ALIGNFLT 7 /* alignment fault */
+#define T_DIVIDE 8 /* integer divide fault */
+#define T_NMI 9 /* non-maskable interrupt */
+#define T_OFLOW 10 /* overflow trap */
+#define T_BOUND 11 /* bounds check fault */
+#define T_DNA 12 /* device not available fault */
+#define T_DOUBLEFLT 13 /* double fault */
+#define T_FPOPFLT 14 /* fp coprocessor operand fetch fault */
+#define T_TSSFLT 15 /* invalid tss fault */
+#define T_SEGNPFLT 16 /* segment not present fault */
+#define T_STKFLT 17 /* stack fault */
+#define T_MCA 18 /* machine check */
+#define T_XMM 19 /* SSE FP exception */
+#define T_RESERVED 20 /* reserved fault base */
+
+/* Trap's coming from user mode */
+#define T_USER 0x100
+
+/* Flags kludged into the trap code */
+
+#define TC_TSS 0x80000000
+#define TC_FLAGMASK (TC_TSS)
--- /dev/null
+/* $NetBSD: vga_post.h,v 1.3 2009/08/24 11:33:49 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2007 Joerg Sonnenberger <joerg@NetBSD.org>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _X86_VGA_POST_H_
+#define _X86_VGA_POST_H_
+
+#ifdef _KERNEL
+struct vga_post;
+
+struct vga_post *vga_post_init(int, int, int);
+void vga_post_free(struct vga_post *);
+void vga_post_call(struct vga_post *);
+void vga_post_set_vbe(struct vga_post *, uint16_t);
+#endif
+#endif
--- /dev/null
+/* $NetBSD: via_padlock.h,v 1.7 2011/11/19 22:51:21 tls Exp $ */
+
+/*-
+ * Copyright (c) 2003 Jason Wright
+ * Copyright (c) 2003, 2004 Theo de Raadt
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _X86_VIA_PADLOCK_H_
+#define _X86_VIA_PADLOCK_H_
+
+#if defined(_KERNEL)
+
+#include <sys/rnd.h>
+#include <sys/callout.h>
+#include <crypto/rijndael/rijndael.h>
+
+/* VIA C3 xcrypt-* instruction context control options */
+#define C3_CRYPT_CWLO_ROUND_M 0x0000000f
+#define C3_CRYPT_CWLO_ALG_M 0x00000070
+#define C3_CRYPT_CWLO_ALG_AES 0x00000000
+#define C3_CRYPT_CWLO_KEYGEN_M 0x00000080
+#define C3_CRYPT_CWLO_KEYGEN_HW 0x00000000
+#define C3_CRYPT_CWLO_KEYGEN_SW 0x00000080
+#define C3_CRYPT_CWLO_NORMAL 0x00000000
+#define C3_CRYPT_CWLO_INTERMEDIATE 0x00000100
+#define C3_CRYPT_CWLO_ENCRYPT 0x00000000
+#define C3_CRYPT_CWLO_DECRYPT 0x00000200
+#define C3_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
+#define C3_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
+#define C3_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
+
+struct via_padlock_session {
+ uint32_t ses_ekey[4 * (RIJNDAEL_MAXNR + 1) + 4]; /* 128 bit aligned */
+ uint32_t ses_dkey[4 * (RIJNDAEL_MAXNR + 1) + 4]; /* 128 bit aligned */
+ uint8_t ses_iv[16]; /* 128 bit aligned */
+ uint32_t ses_cw0;
+ struct swcr_data *swd;
+ int ses_klen;
+ int ses_used;
+};
+
+struct via_padlock_softc {
+ device_t sc_dev;
+
+ uint32_t op_cw[4]; /* 128 bit aligned */
+ uint8_t op_iv[16]; /* 128 bit aligned */
+ void *op_buf;
+
+ int sc_rnd_hz;
+ struct callout sc_rnd_co;
+ krndsource_t sc_rnd_source;
+ bool sc_rnd_attached;
+
+ /* normal softc stuff */
+ int32_t sc_cid;
+ bool sc_cid_attached;
+ int sc_nsessions;
+ struct via_padlock_session *sc_sessions;
+};
+
+#define VIAC3_SESSION(sid) ((sid) & 0x0fffffff)
+#define VIAC3_SID(crd,ses) (((crd) << 28) | ((ses) & 0x0fffffff))
+
+#define VIAC3_RNG_BUFSIZ 16
+
+#endif /* _KERNEL */
+
+#if defined(_KERNEL) || defined(_KMEMUSER)
+struct cpu_info;
+
+struct via_padlock {
+ struct cpu_info *vp_ci;
+ int vp_freq;
+};
+
+#endif /* _KERNEL || _KMEMUSER */
+#endif /* _X86_VIA_PADLOCK_H_ */