]> Zhao Yanbai Git Server - acecode.git/commit
SysClk手动设置为72MHz,时钟切为外部高速时钟HSE
authorAceVest <zhaoyanbai@126.com>
Sat, 1 Jun 2019 08:03:10 +0000 (16:03 +0800)
committerAceVest <zhaoyanbai@126.com>
Sat, 1 Jun 2019 08:03:10 +0000 (16:03 +0800)
commitfb85e70368a47ebaa1b6bcdf7459d91d929d9bf4
tree1817658837145cf5346f4cc6298ba113a0e9a15e
parent175f14d8d96be06b781de94c8cfb55c5abab6f47
SysClk手动设置为72MHz,时钟切为外部高速时钟HSE
learn/stm32/F103HAL/Src/System.c
learn/stm32/F103HAL/Src/main.c