#include <wait.h>
#include <string.h>
-DECLARE_MUTEX(mutex);
-void ide_cmd_out(dev_t dev, u32 sect_cnt, u64 sect_nr, u32 cmd);
-
-unsigned int HD_CHL0_CMD_BASE = 0x1F0;
-unsigned int HD_CHL1_CMD_BASE = 0x170;
-
-unsigned int HD_CHL0_CTL_BASE = 0x3F6;
-unsigned int HD_CHL1_CTL_BASE = 0x376;
-
typedef struct _ide_drv
{
pci_device_t *pci;
part_t part[MAX_SUPPORT_PARTITION_CNT];
} ide_drive_t;
-ide_drive_t drv;
-
typedef struct prd
{
unsigned int addr;
wait_queue_head_t wait;
} ide_request_t;
+typedef void (*ide_intr_func_t)();
+
+void ide_default_intr();
+
+ide_drive_t drv;
+DECLARE_MUTEX(mutex);
ide_request_t ide_request;
+ide_intr_func_t ide_intr_func = ide_default_intr;
+
+unsigned char *dma_data = 0;
+
+unsigned int HD_CHL0_CMD_BASE = 0x1F0;
+unsigned int HD_CHL1_CMD_BASE = 0x170;
+
+unsigned int HD_CHL0_CTL_BASE = 0x3F6;
+unsigned int HD_CHL1_CTL_BASE = 0x376;
+
+void ide_printd()
+{
+ printd(MPL_IDE, "ide pio_cnt %d dma_cnt %d irq_cnt %d", drv.pio_cnt, drv.dma_cnt, drv.irq_cnt);
+}
+
+void ide_cmd_out(dev_t dev, u32 sect_cnt, u64 sect_nr, u32 cmd)
+{
+ drv.pio_cnt++;
+ drv.read_mode = cmd;
+
+ ide_printd();
+
+ outb(0x00, REG_CTL(dev));
+ outb(0x40|0x00, REG_DEVSEL(dev));
+
+ outb((u8)((sect_cnt>>8)&0xFF), REG_NSECTOR(dev)); // High
+ outb((u8)((sect_nr>>24)&0xFF), REG_LBAL(dev));
+ outb((u8)((sect_nr>>32)&0xFF), REG_LBAM(dev));
+ outb((u8)((sect_nr>>40)&0xFF), REG_LBAH(dev));
+
+ outb((u8)((sect_cnt>>0)&0xFF), REG_NSECTOR(dev)); // Low
+ outb((u8)((sect_nr>> 0)&0xFF), REG_LBAL(dev));
+ outb((u8)((sect_nr>> 8)&0xFF), REG_LBAM(dev));
+ outb((u8)((sect_nr>>16)&0xFF), REG_LBAH(dev));
+
+ outb(cmd, REG_CMD(dev));
+}
+
void ide_do_read(u64_t lba, u32_t scnt, char *buf)
{
bool finish = false;
del_wait_queue(&r->wait, &wait);
}
-unsigned char *data = 0;
unsigned int sys_clock();
-bool ide_init_inted = false;
-
void ide_pci_init(pci_device_t *pci)
{
unsigned int v;
}
-void ide_printd()
-{
- printd(MPL_IDE, "ide pio_cnt %d dma_cnt %d irq_cnt %d", drv.pio_cnt, drv.dma_cnt, drv.irq_cnt);
-}
-
-void ide_cmd_out(dev_t dev, u32 sect_cnt, u64 sect_nr, u32 cmd)
-{
- ide_init_inted = false;
-
- drv.pio_cnt++;
- drv.read_mode = cmd;
-
- ide_printd();
-
- outb(0x00, REG_CTL(dev));
- outb(0x40|0x00, REG_DEVSEL(dev));
-
- outb((u8)((sect_cnt>>8)&0xFF), REG_NSECTOR(dev)); // High
- outb((u8)((sect_nr>>24)&0xFF), REG_LBAL(dev));
- outb((u8)((sect_nr>>32)&0xFF), REG_LBAM(dev));
- outb((u8)((sect_nr>>40)&0xFF), REG_LBAH(dev));
-
- outb((u8)((sect_cnt>>0)&0xFF), REG_NSECTOR(dev)); // Low
- outb((u8)((sect_nr>> 0)&0xFF), REG_LBAL(dev));
- outb((u8)((sect_nr>> 8)&0xFF), REG_LBAM(dev));
- outb((u8)((sect_nr>>16)&0xFF), REG_LBAH(dev));
-
- outb(cmd, REG_CMD(dev));
-}
-
-void ide_wait_ready()
-{
- u32 retires = 100;
-
- do
- {
- int drq_retires = 100000;
- while(!hd_drq(dev) && --drq_retires)
- /* do nothing */;
-
- if(drq_retires != 0)
- break;
- }while(--retires);
-
- if(retires == 0)
- panic("hard disk is not ready");
-}
-
-
-void dump_pci_ide();
-
void ide_status()
{
u8_t idest = inb(REG_STATUS(0));
printk(" ide status %02x pci status %02x\n", idest, pcist);
}
-
void ide_debug()
{
u32 device;
u32 nsect = 1;
u32 retires = 100;
- u32 sect_nr = 0;
+ u64 sect_nr = 0;
int count=SECT_SIZE;
nsect = (count + SECT_SIZE -1)/SECT_SIZE;
if(drv.read_mode == HD_CMD_READ_EXT)
{
insl(REG_DATA(0), ide_request.buf, ((ide_request.scnt*SECT_SIZE)>>2));
+ sig = *((u16_t *) (ide_request.buf+510));
}
if(drv.read_mode == HD_CMD_READ_DMA)
{
- sig = *((u16_t *) (data+510));
+ sig = *((u16_t *) (dma_data+510));
}
ide_printd();
up(&mutex);
}
-typedef void (*ide_intr_func_t)();
-ide_intr_func_t ide_intr_func = ide_default_intr;
void ide_irq()
{
void ide_dma_pci_lba48()
{
- ide_init_inted = false;
drv.dma_cnt ++;
drv.read_mode = HD_CMD_READ_DMA;
#if 1
memset((void *)&prd, 0, sizeof(prd));
unsigned long addr = alloc_one_page(0);
- data = (char *) addr;
- memset(data, 0xBB, 512);
+ dma_data = (char *) addr;
+ memset(dma_data, 0xBB, 512);
prd.addr = va2pa(addr);
prd.cnt = 512;
prd.eot = 1;
outb((offset)&0xFF, VGA_CRTC_DATA);
}
-int bvga = 0;
-void vga_init()
-{
- unsigned int i;
- for(i=1; i<VGA_MAX_SCREEN_CNT; ++i)
- {
- memset(vga_screen + i, 0, sizeof(vga_screen_t));
- vga_screen[i].id = i;
- vga_screen[i].base = (vga_char_t *) (VIDEO_ADDR + i*MAX_LINES_PER_SCREEN*BYTES_PER_LINE);
- memset(vga_screen[i].base, 0, MAX_LINES_PER_SCREEN*BYTES_PER_LINE);
- }
- bvga = 1;
-}
-
void vga_switch(unsigned int nr)
{
if(nr >= VGA_MAX_SCREEN_CNT)
__vga_switch(offset);
}
+unsigned char vga_dbg_color = 0x1F;
+
+void vga_dbg_clear()
+{
+ int i;
+ int line;
+ for(line=0; line<MAX_LINES_PER_SCREEN; ++line)
+ {
+ vga_char_t * const pv = (vga_char_t * const) (VIDEO_ADDR + (VIDEO_DBG_LINE + line) * BYTES_PER_LINE);
+ for(i=0; i<CHARS_PER_LINE; ++i)
+ pv[i] = vga_char(0, vga_dbg_color);
+ }
+}
-void vga_dbg_puts(unsigned int line, const char *buf, unsigned char color)
+void vga_dbg_puts(unsigned int line, const char *buf)
{
int i;
char *p = (char *) buf;
vga_char_t * const pv = (vga_char_t * const) (VIDEO_ADDR + (VIDEO_DBG_LINE + line) * BYTES_PER_LINE);
for(i=0; i<CHARS_PER_LINE; ++i)
- pv[i] = vga_char(0, color);
+ pv[i] = vga_char(0, vga_dbg_color);
for(i=0; *p; ++i, ++p)
{
- color = 0x1F;
- pv[i] = vga_char(*p, color);
+ pv[i] = vga_char(*p, vga_dbg_color);
+ }
+}
+
+void vga_init()
+{
+ unsigned int i;
+ for(i=1; i<VGA_MAX_SCREEN_CNT; ++i)
+ {
+ memset(vga_screen + i, 0, sizeof(vga_screen_t));
+ vga_screen[i].id = i;
+ vga_screen[i].base = (vga_char_t *) (VIDEO_ADDR + i*MAX_LINES_PER_SCREEN*BYTES_PER_LINE);
+ memset(vga_screen[i].base, 0, MAX_LINES_PER_SCREEN*BYTES_PER_LINE);
}
+
+ vga_dbg_clear();
}
+