--- /dev/null
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--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>F103</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
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+ <triggers>clean,full,incremental,</triggers>
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+ <nature>fr.ac6.mcu.ide.core.MCUSingleCoreProjectNature</nature>
+ </natures>
+</projectDescription>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.496812091" name="Debug">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
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+ <language-scope id="org.eclipse.cdt.core.g++"/>
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+ </configuration>
+ <configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.release.531280813" name="Release">
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+ </extension>
+ </configuration>
+</project>
--- /dev/null
+# This is an OneNetMini board with a single STM32F103C8Tx chip\r
+#\r
+# Generated by System Workbench for STM32\r
+# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)\r
+\r
+source [find interface/stlink.cfg]\r
+\r
+set WORKAREASIZE 0x5000\r
+\r
+transport select "hla_swd"\r
+\r
+set CHIPNAME STM32F103C8Tx\r
+set BOARDNAME OneNetMini\r
+\r
+# CHIPNAMES state\r
+set CHIPNAME_CPU0_ACTIVATED 1\r
+\r
+# Enable debug when in low power modes\r
+set ENABLE_LOW_POWER 1\r
+\r
+# Stop Watchdog counters when halt\r
+set STOP_WATCHDOG 1\r
+\r
+# STlink Debug clock frequency\r
+set CLOCK_FREQ 4000\r
+\r
+# use software system reset\r
+reset_config none\r
+set CONNECT_UNDER_RESET 0\r
+\r
+# BCTM CPU variables\r
+\r
+\r
+\r
+source [find target/stm32f1x.cfg]\r
--- /dev/null
+/*\r
+******************************************************************************\r
+**\r
+** File : LinkerScript.ld\r
+**\r
+** Author : Auto-generated by Ac6 System Workbench\r
+**\r
+** Abstract : Linker script for STM32F103C8Tx Device from STM32F1 series\r
+** 20Kbytes RAM
+** 64Kbytes ROM\r
+**\r
+** Set heap size, stack size and stack location according\r
+** to application requirements.\r
+**\r
+** Set memory bank area and size if external memory is used.\r
+**\r
+** Target : STMicroelectronics STM32\r
+**\r
+** Distribution: The file is distributed �as is,� without any warranty\r
+** of any kind.\r
+**\r
+*****************************************************************************\r
+** @attention\r
+**\r
+** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>\r
+**\r
+** Redistribution and use in source and binary forms, with or without modification,\r
+** are permitted provided that the following conditions are met:\r
+** 1. Redistributions of source code must retain the above copyright notice,\r
+** this list of conditions and the following disclaimer.\r
+** 2. Redistributions in binary form must reproduce the above copyright notice,\r
+** this list of conditions and the following disclaimer in the documentation\r
+** and/or other materials provided with the distribution.\r
+** 3. Neither the name of Ac6 nor the names of its contributors\r
+** may be used to endorse or promote products derived from this software\r
+** without specific prior written permission.\r
+**\r
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+**\r
+*****************************************************************************\r
+*/\r
+\r
+/* Entry Point */\r
+ENTRY(Reset_Handler)\r
+\r
+/* Highest address of the user mode stack */\r
+_estack = 0x20005000; /* end of RAM */\r
+\r
+_Min_Heap_Size = 0; /* required amount of heap */\r
+_Min_Stack_Size = 0x400; /* required amount of stack */\r
+\r
+/* Memories definition */\r
+MEMORY\r
+{\r
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
+ ROM (rx) : ORIGIN = 0x8000000, LENGTH = 64K\r
+}\r
+\r
+/* Sections */\r
+SECTIONS\r
+{\r
+ /* The startup code into ROM memory */\r
+ .isr_vector :\r
+ {\r
+ . = ALIGN(4);\r
+ KEEP(*(.isr_vector)) /* Startup code */\r
+ . = ALIGN(4);\r
+ } >ROM\r
+\r
+ /* The program code and other data into ROM memory */\r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.text) /* .text sections (code) */\r
+ *(.text*) /* .text* sections (code) */\r
+ *(.glue_7) /* glue arm to thumb code */\r
+ *(.glue_7t) /* glue thumb to arm code */\r
+ *(.eh_frame)\r
+\r
+ KEEP (*(.init))\r
+ KEEP (*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ _etext = .; /* define a global symbols at end of code */\r
+ } >ROM\r
+\r
+ /* Constant data into ROM memory*/\r
+ .rodata :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */\r
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */\r
+ . = ALIGN(4);\r
+ } >ROM\r
+\r
+ .ARM.extab : { \r
+ . = ALIGN(4);\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ . = ALIGN(4);\r
+ } >ROM\r
+ \r
+ .ARM : {\r
+ . = ALIGN(4);\r
+ __exidx_start = .;\r
+ *(.ARM.exidx*)\r
+ __exidx_end = .;\r
+ . = ALIGN(4);\r
+ } >ROM\r
+\r
+ .preinit_array :\r
+ {\r
+ . = ALIGN(4);\r
+ PROVIDE_HIDDEN (__preinit_array_start = .);\r
+ KEEP (*(.preinit_array*))\r
+ PROVIDE_HIDDEN (__preinit_array_end = .);\r
+ . = ALIGN(4);\r
+ } >ROM\r
+ \r
+ .init_array :\r
+ {\r
+ . = ALIGN(4);\r
+ PROVIDE_HIDDEN (__init_array_start = .);\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array*))\r
+ PROVIDE_HIDDEN (__init_array_end = .);\r
+ . = ALIGN(4);\r
+ } >ROM\r
+ \r
+ .fini_array :\r
+ {\r
+ . = ALIGN(4);\r
+ PROVIDE_HIDDEN (__fini_array_start = .);\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ KEEP (*(.fini_array*))\r
+ PROVIDE_HIDDEN (__fini_array_end = .);\r
+ . = ALIGN(4);\r
+ } >ROM\r
+\r
+ /* Used by the startup to initialize data */\r
+ _sidata = LOADADDR(.data);\r
+\r
+ /* Initialized data sections into RAM memory */\r
+ .data : \r
+ {\r
+ . = ALIGN(4);\r
+ _sdata = .; /* create a global symbol at data start */\r
+ *(.data) /* .data sections */\r
+ *(.data*) /* .data* sections */\r
+\r
+ . = ALIGN(4);\r
+ _edata = .; /* define a global symbol at data end */\r
+ } >RAM AT> ROM\r
+\r
+ \r
+ /* Uninitialized data section into RAM memory */\r
+ . = ALIGN(4);\r
+ .bss :\r
+ {\r
+ /* This is used by the startup in order to initialize the .bss secion */\r
+ _sbss = .; /* define a global symbol at bss start */\r
+ __bss_start__ = _sbss;\r
+ *(.bss)\r
+ *(.bss*)\r
+ *(COMMON)\r
+\r
+ . = ALIGN(4);\r
+ _ebss = .; /* define a global symbol at bss end */\r
+ __bss_end__ = _ebss;\r
+ } >RAM\r
+\r
+ /* User_heap_stack section, used to check that there is enough RAM left */\r
+ ._user_heap_stack :\r
+ {\r
+ . = ALIGN(8);\r
+ PROVIDE ( end = . );\r
+ PROVIDE ( _end = . );\r
+ . = . + _Min_Heap_Size;\r
+ . = . + _Min_Stack_Size;\r
+ . = ALIGN(8);\r
+ } >RAM\r
+\r
+ \r
+\r
+ /* Remove information from the compiler libraries */\r
+ /DISCARD/ :\r
+ {\r
+ libc.a ( * )\r
+ libm.a ( * )\r
+ libgcc.a ( * )\r
+ }\r
+\r
+ .ARM.attributes 0 : { *(.ARM.attributes) }\r
+}\r
--- /dev/null
+/*
+ * debug.h
+ *
+ * Created on: May 24, 2019
+ * Author: ace
+ */
+
+#ifndef DEBUG_H_
+#define DEBUG_H_
+
+
+
+#endif /* DEBUG_H_ */
--- /dev/null
+/*
+ * gpio.c
+ *
+ * Created on: May 24, 2019
+ * Author: ace
+ */
+
+#include "gpio.h"
+
+
+
+void GPIOSetOutput(GPIO_t *gpio, uint32_t pin, GPIOOutputMode_t mode, GPIOOutputSpeed_t speed) {
+ uint32_t *CR = pin < 8 ? &gpio->CRL : &gpio->CRH;
+ uint32_t n = (pin < 8 ? pin : pin - 8) * 4;
+
+ uint32_t mask = 0x0FU;
+ *CR &= ~mask << n; // 清除CNF、MODE的比特位
+ *CR |= (mode|speed) << n; // 设置为相应的输出模块+相应的速度
+}
+
+
+void GPIOToggle(GPIO_t *gpio, uint32_t pin) {
+ gpio->ODR ^= 1 << pin;
+}
+
+
+
+void GPIOWrite(GPIO_t *gpio, uint32_t pin, uint32_t level) {
+ if(level == LOW) {
+ gpio->BRR |= 1 << pin;
+ } else {
+ gpio->BSRR |= 1 << pin;
+ }
+}
--- /dev/null
+/*
+ * gpio.h
+ *
+ * Created on: May 24, 2019
+ * Author: ace
+ */
+
+#ifndef GPIO_H_
+#define GPIO_H_
+
+#include "stm32f103.h"
+
+
+typedef struct {
+ uint32_t CRL;
+ uint32_t CRH;
+ uint32_t IDR;
+ uint32_t ODR;
+ uint32_t BSRR; // Bit Set Reset Register
+ uint32_t BRR; // Bit Reset Register
+ uint32_t LCKR;
+} GPIO_t;
+
+#define GPIOA ((GPIO_t*)GPIOA_BASE)
+#define GPIOB ((GPIO_t*)GPIOB_BASE)
+#define GPIOC ((GPIO_t*)GPIOC_BASE)
+#define GPIOD ((GPIO_t*)GPIOD_BASE)
+#define GPIOE ((GPIO_t*)GPIOE_BASE)
+
+
+typedef enum {
+ GPIO_OUTPUT_MODE_GP_PP = 0x00,
+ GPIO_OUTPUT_MODE_GP_OD = 0x01,
+ GPIO_OUTPUT_MODE_AF_PP = 0x02,
+ GPIO_OUTPUT_MODE_AF_OD = 0x03,
+} GPIOOutputMode_t;
+
+
+typedef enum {
+ GPIO_OUTPUT_SPEED_10MHZ = 0x01,
+ GPIO_OUTPUT_SPEED_20MHZ = 0x02,
+ GPIO_OUTPUT_SPEED_50MHZ = 0x03,
+} GPIOOutputSpeed_t;
+
+#define HIGH 1
+#define LOW 0
+
+
+
+void GPIOSetOutput(GPIO_t *gpio, uint32_t pin, GPIOOutputMode_t mode, GPIOOutputSpeed_t speed);
+
+void GPIOToggle(GPIO_t *gpio, uint32_t pin);
+void GPIOWrite(GPIO_t *gpio, uint32_t pin, uint32_t level);
+
+
+#endif /* GPIO_H_ */
--- /dev/null
+/*
+ * main.c
+ *
+ * Created on: May 24, 2019
+ * Author: ace
+ */
+
+
+#include "stm32f103.h"
+
+
+#include "gpio.h"
+#include "rcc.h"
+
+#define APB2ENR (*(unsigned int*)(RCC_BASE+0x18))
+
+unsigned int pin = 8;
+
+
+void SystemInit() {
+ // 使能时钟
+ RCCEnableGPIOBClock();
+
+ GPIOSetOutput(GPIOB, pin, GPIO_OUTPUT_MODE_GP_PP, GPIO_OUTPUT_SPEED_50MHZ);
+}
+
+void delay() {
+ int i=65536;
+ while(i--);
+}
+
+int main() {
+
+ while(1) {
+ GPIOWrite(GPIOB, pin, HIGH);
+ delay();
+ GPIOWrite(GPIOB, pin, LOW);
+ delay();
+ continue;
+ GPIOToggle(GPIOB, pin);
+ delay();
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * rcc.c
+ *
+ * Created on: May 24, 2019
+ * Author: ace
+ */
+
+#include "rcc.h"
+
+void __RCCEnableAPB2(uint32_t en) {
+ RCC->APB2ENR |= en;
+}
--- /dev/null
+/*
+ * rcc.h
+ *
+ * Created on: May 24, 2019
+ * Author: ace
+ */
+
+#ifndef RCC_H_
+#define RCC_H_
+
+#include "stm32f103.h"
+
+typedef struct {
+ uint32_t CR;
+ uint32_t CFGR;
+ uint32_t CIR;
+ uint32_t APB2RSTR;
+ uint32_t APB1RSTR;
+ uint32_t AHBENR;
+ uint32_t APB2ENR;
+ uint32_t APB1ENR;
+ uint32_t BDCR;
+ uint32_t CSR;
+} RCC_t;
+
+#define RCC ((RCC_t*) RCC_BASE)
+
+#define RCC_APB2ENR_IOPAEN 0x00000004
+#define RCC_APB2ENR_IOPBEN 0x00000008
+#define RCC_APB2ENR_IOPCEN 0x00000010
+#define RCC_APB2ENR_IOPDEN 0x00000020
+#define RCC_APB2ENR_IOPEEN 0x00000040
+
+
+
+void __RCCEnableAPB2(uint32_t en);
+
+#define RCCEnableGPIOAClock() __RCCEnableAPB2(RCC_APB2ENR_IOPAEN)
+#define RCCEnableGPIOBClock() __RCCEnableAPB2(RCC_APB2ENR_IOPBEN)
+#define RCCEnableGPIOCClock() __RCCEnableAPB2(RCC_APB2ENR_IOPCEN)
+#define RCCEnableGPIODClock() __RCCEnableAPB2(RCC_APB2ENR_IOPDEN)
+#define RCCEnableGPIOEClock() __RCCEnableAPB2(RCC_APB2ENR_IOPEEN)
+
+#endif /* RCC_H_ */
--- /dev/null
+/*
+ * registers.h
+ *
+ * Created on: May 24, 2019
+ * Author: ace
+ */
+
+#ifndef STM32F103_H_
+#define STM32F103_H_
+
+
+#include <stdint.h>
+
+
+#define PERIPH_BASE 0x40000000
+#define APB1PERIPH_BASE (PERIPH_BASE+0x00000)
+#define APB2PERIPH_BASE (PERIPH_BASE+0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE+0x20000)
+
+
+#define GPIOA_BASE (APB2PERIPH_BASE+0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE+0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE+0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE+0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE+0x1800)
+
+#define RCC_BASE (AHBPERIPH_BASE+0x1000)
+
+
+
+#endif /* STM32F103_H_ */
--- /dev/null
+/**
+ ******************************************************************************
+ * @file startup_stm32.s dedicated to STM32F103C8Tx device
+ * @author Ac6
+ * @version V1.0.0
+ * @date 2019-05-24
+ ******************************************************************************
+ */
+
+
+.syntax unified
+.cpu cortex-m3
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The STM32F103C8Tx vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_IRQHandler /* PVD through EXTI line detection interrupt */
+ .word TAMPER_IRQHandler /* Tamper interrupt */
+ .word RTC_IRQHandler /* RTC global interrupt */
+ .word FLASH_IRQHandler /* Flash global interrupt */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI Line0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI Line1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI Line2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI Line3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI Line4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel1 global interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 Channel2 global interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 Channel3 global interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 Channel4 global interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 Channel5 global interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 Channel6 global interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 Channel7 global interrupt */
+ .word ADC1_2_IRQHandler /* ADC1 and ADC2 global interrupt */
+ .word USB_HP_CAN_TX_IRQHandler /* USB High Priority or CAN TX interrupts */
+ .word USB_LP_CAN_RX0_IRQHandler /* USB Low Priority or CAN RX0 interrupts */
+ .word CAN_RX1_IRQHandler /* CAN RX1 interrupt */
+ .word CAN_SCE_IRQHandler /* CAN SCE interrupt */
+ .word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupts */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM3_IRQHandler /* TIM3 global interrupt */
+ .word TIM4_IRQHandler /* TIM4 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 error interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 event interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word USART3_IRQHandler /* USART3 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
+ .word RTCAlarm_IRQHandler /* RTC Alarms through EXTI line interrupt */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_IRQHandler /* TIM8 Break interrupt */
+ .word TIM8_UP_IRQHandler /* TIM8 Update interrupt */
+ .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation interrupts */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare interrupt */
+ .word ADC3_IRQHandler /* ADC3 global interrupt */
+ .word FSMC_IRQHandler /* FSMC global interrupt */
+ .word SDIO_IRQHandler /* SDIO global interrupt */
+ .word TIM5_IRQHandler /* TIM5 global interrupt */
+ .word SPI3_IRQHandler /* SPI3 global interrupt */
+ .word UART4_IRQHandler /* UART4 global interrupt */
+ .word UART5_IRQHandler /* UART5 global interrupt */
+ .word TIM6_IRQHandler /* TIM6 global interrupt */
+ .word TIM7_IRQHandler /* TIM7 global interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 global interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 global interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 global interrupt */
+ .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 and DMA2 Channel5 global interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN_TX_IRQHandler
+ .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN_RX0_IRQHandler
+ .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FSMC_IRQHandler
+ .thumb_set FSMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_5_IRQHandler
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+ .weak SystemInit
+
+/************************ (C) COPYRIGHT Ac6 *****END OF FILE****/
--- /dev/null
+/**\r
+*****************************************************************************\r
+**\r
+** File : sysmem.c\r
+**\r
+** Author : Ac6\r
+**\r
+** Abstract : System Workbench Minimal System Memory calls file\r
+**\r
+** For more information about which c-functions\r
+** need which of these lowlevel functions\r
+** please consult the Newlib libc-manual\r
+**\r
+** Environment : System Workbench for MCU\r
+**\r
+** Distribution: The file is distributed \93as is,\94 without any warranty\r
+** of any kind.\r
+**\r
+*****************************************************************************\r
+**\r
+** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>\r
+**\r
+** Redistribution and use in source and binary forms, with or without modification,\r
+** are permitted provided that the following conditions are met:\r
+** 1. Redistributions of source code must retain the above copyright notice,\r
+** this list of conditions and the following disclaimer.\r
+** 2. Redistributions in binary form must reproduce the above copyright notice,\r
+** this list of conditions and the following disclaimer in the documentation\r
+** and/or other materials provided with the distribution.\r
+** 3. Neither the name of Ac6 nor the names of its contributors\r
+** may be used to endorse or promote products derived from this software\r
+** without specific prior written permission.\r
+**\r
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+**\r
+*****************************************************************************\r
+*/\r
+\r
+/* Includes */\r
+#include <errno.h>\r
+#include <stdio.h>\r
+\r
+/* Variables */\r
+extern int errno;\r
+register char * stack_ptr asm("sp");\r
+\r
+/* Functions */\r
+\r
+/**\r
+ _sbrk\r
+ Increase program data space. Malloc and related functions depend on this\r
+**/\r
+caddr_t _sbrk(int incr)\r
+{\r
+ extern char end asm("end");\r
+ static char *heap_end;\r
+ char *prev_heap_end;\r
+\r
+ if (heap_end == 0)\r
+ heap_end = &end;\r
+\r
+ prev_heap_end = heap_end;\r
+ if (heap_end + incr > stack_ptr)\r
+ {\r
+ errno = ENOMEM;\r
+ return (caddr_t) -1;\r
+ }\r
+\r
+ heap_end += incr;\r
+\r
+ return (caddr_t) prev_heap_end;\r
+}\r
+\r