]> Zhao Yanbai Git Server - minix.git/commitdiff
arm am335x: disable watchdog timer on bootup 27/2727/3
authorBen Gras <ben@minix3.org>
Fri, 22 Aug 2014 12:06:57 +0000 (14:06 +0200)
committerBen Gras <beng@shrike-systems.com>
Fri, 22 Aug 2014 12:30:49 +0000 (14:30 +0200)
. for new uboot (specifically beaglebone black rev c) compliance

Change-Id: I28fd0ca15f5365e14bf2bb9407f266e3e570b6d9

minix/kernel/arch/earm/bsp/include/bsp_reset.h
minix/kernel/arch/earm/bsp/ti/omap_init.c
minix/kernel/arch/earm/bsp/ti/omap_reset.c
minix/kernel/arch/earm/bsp/ti/omap_timer_registers.h

index 6158a8f844562067d9cb45fb0011bcc3cb5ca9a2..7f91da13c62eade287365b1b129d3194ae86cdb4 100644 (file)
@@ -4,5 +4,6 @@
 void bsp_reset_init(void);
 void bsp_reset(void);
 void bsp_poweroff(void);
+void bsp_disable_watchdog(void);
 
 #endif /* _BSP_RESET_H_ */
index 1d54bfecaa671e2ae0748a8afe72c7c8555f4eab..99a47b765fb8dab9123390cd505c9eae426d76e6 100644 (file)
@@ -15,4 +15,7 @@ bsp_init()
 
        /* map memory for reset control */
        bsp_reset_init();
+
+       /* disable watchdog */
+       bsp_disable_watchdog();
 }
index 13daa5a59330ea3ec4459aae5cb0018826a3666d..db85626571e3cf3a4e5a17f168046cc9293b77a1 100644 (file)
@@ -12,6 +12,7 @@
 #include "arch_proto.h"
 #include "bsp_reset.h"
 
+#include "omap_timer_registers.h"
 #include "omap_rtc.h"
 
 #define AM335X_CM_BASE 0x44E00000
@@ -86,3 +87,14 @@ bsp_poweroff(void)
                while (1);
        }
 }
+
+void bsp_disable_watchdog(void)
+{
+        if(BOARD_IS_BB(machine.board_id)) {
+               mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0xAAAA);
+               while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
+               mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0x5555);
+               while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
+       }
+}
+
index 619272da82ed296ec5eebfba6fdddc56c4a215c5..b127e48edaf03fa7bffbcb99324bd4324b6b0f61 100644 (file)
@@ -65,7 +65,9 @@
 #define AM335X_TIMER_TSICR     0x054 /* Control posted mode and functional SW reset */
 #define AM335X_TIMER_TCAR2     0x058 /* Second captured value of counter register */
 
-
+#define AM335X_WDT_BASE                0x44E35000      /* watchdog timer */
+#define AM335X_WDT_WWPS                0x34            /* command posted status */
+#define AM335X_WDT_WSPR                0x48            /* activate/deactivate sequence */
 
 /* Interrupt status register fields */
 #define OMAP3_TISR_MAT_IT_FLAG  (1 << 0) /* Pending match interrupt status */