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(parent: 2830a5a) | patch
arm:caching access the l1 pages over cacheable memory. 49/849/2
authorKees Jongenburger <kees.jongenburger@gmail.com>
Wed, 25 Sep 2013 08:30:18 +0000 (10:30 +0200)
committerKees Jongenburger <kees.jongenburger@gmail.com>
Thu, 26 Sep 2013 09:57:44 +0000 (11:57 +0200)
commitd77debb5b7d72ccd6d999252b3a1ac8e053d6e41
treeafaf4e25a4f8c3fa11f80a5cbe4a181a39ef6ed7tree | snapshot
parent2830a5af5c11b366adad8f9d7f872d68c44dd947commit | diff
arm:caching access the l1 pages over cacheable memory.

When we start using a new pagetable (for a new process)
the last part is to ensure the pagetable itself can be
accessed by VM. This is done in pt_bind by updating
the "pagetable of pagetables" and we want this mapping
to match other mappings to the l1 pagetable.

Change-Id: I7b506fd75553917fdc1abd25b55e4b2f25ccbf8d
servers/vm/arch/i386/pagetable.c diff | blob | history
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