export PATH=$PATH:/Applications/Arduino.app/Contents/Java/hardware/tools/avr/bin/
export PATH=$PATH:$HOME/Library/Arduino15/packages/arduino/tools/avrdude/6.0.1-arduino5/bin
export PATH=$PATH:/usr/local/opt/go/libexec/bin
+export PATH=$PATH:/Users/ace/sys/riscv-none-gcc/8.2.0-2.2-20190521-0004/bin
#多个GOPATH用';'分隔 go get会å˜åˆ°ç¬¬ä¸€ä¸ªç›®å½•
export GOPATH=$HOME/workspace/go:$HOME/workspace/web/qossvr/
export RTOS_PATH=$HOME/workspace/acecode/rtos/
+++ /dev/null
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+++ /dev/null
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+++ /dev/null
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+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f103xe.h\r
- * @author MCD Application Team\r
- * @version V4.2.0\r
- * @date 31-March-2017\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
- * This file contains all the peripheral register's definitions, bits \r
- * definitions and memory mapping for STM32F1xx devices. \r
- * \r
- * This file contains:\r
- * - Data structures and the address mapping for all peripherals\r
- * - Peripheral's registers declarations and bits definition\r
- * - Macros to access peripheral\92s registers hardware\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f103xe\r
- * @{\r
- */\r
- \r
-#ifndef __STM32F103xE_H\r
-#define __STM32F103xE_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/** @addtogroup Configuration_section_for_CMSIS\r
- * @{\r
- */\r
-/**\r
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals \r
- */\r
-#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */\r
- #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */\r
-#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */\r
-#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Peripheral_interrupt_number_definition\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief STM32F10x Interrupt Number Definition, according to the selected device \r
- * in @ref Library_configuration_section \r
- */\r
-\r
- /*!< Interrupt Number Definition */\r
-typedef enum\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** STM32 specific Interrupt Numbers *********************************************************/\r
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
- TAMPER_IRQn = 2, /*!< Tamper Interrupt */\r
- RTC_IRQn = 3, /*!< RTC global Interrupt */\r
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
- RCC_IRQn = 5, /*!< RCC global Interrupt */\r
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
- TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */\r
- TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */\r
- TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */\r
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */\r
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
- UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
- UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
- TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
- DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
-} IRQn_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#include "core_cm3.h"\r
-#include "system_stm32f1xx.h"\r
-#include <stdint.h>\r
-\r
-/** @addtogroup Peripheral_registers_structures\r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief Analog to Digital Converter \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t SR;\r
- __IO uint32_t CR1;\r
- __IO uint32_t CR2;\r
- __IO uint32_t SMPR1;\r
- __IO uint32_t SMPR2;\r
- __IO uint32_t JOFR1;\r
- __IO uint32_t JOFR2;\r
- __IO uint32_t JOFR3;\r
- __IO uint32_t JOFR4;\r
- __IO uint32_t HTR;\r
- __IO uint32_t LTR;\r
- __IO uint32_t SQR1;\r
- __IO uint32_t SQR2;\r
- __IO uint32_t SQR3;\r
- __IO uint32_t JSQR;\r
- __IO uint32_t JDR1;\r
- __IO uint32_t JDR2;\r
- __IO uint32_t JDR3;\r
- __IO uint32_t JDR4;\r
- __IO uint32_t DR;\r
-} ADC_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */\r
- __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */\r
- __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */\r
- uint32_t RESERVED[16];\r
- __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */\r
-} ADC_Common_TypeDef;\r
-\r
-/** \r
- * @brief Backup Registers \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __IO uint32_t DR1;\r
- __IO uint32_t DR2;\r
- __IO uint32_t DR3;\r
- __IO uint32_t DR4;\r
- __IO uint32_t DR5;\r
- __IO uint32_t DR6;\r
- __IO uint32_t DR7;\r
- __IO uint32_t DR8;\r
- __IO uint32_t DR9;\r
- __IO uint32_t DR10;\r
- __IO uint32_t RTCCR;\r
- __IO uint32_t CR;\r
- __IO uint32_t CSR;\r
- uint32_t RESERVED13[2];\r
- __IO uint32_t DR11;\r
- __IO uint32_t DR12;\r
- __IO uint32_t DR13;\r
- __IO uint32_t DR14;\r
- __IO uint32_t DR15;\r
- __IO uint32_t DR16;\r
- __IO uint32_t DR17;\r
- __IO uint32_t DR18;\r
- __IO uint32_t DR19;\r
- __IO uint32_t DR20;\r
- __IO uint32_t DR21;\r
- __IO uint32_t DR22;\r
- __IO uint32_t DR23;\r
- __IO uint32_t DR24;\r
- __IO uint32_t DR25;\r
- __IO uint32_t DR26;\r
- __IO uint32_t DR27;\r
- __IO uint32_t DR28;\r
- __IO uint32_t DR29;\r
- __IO uint32_t DR30;\r
- __IO uint32_t DR31;\r
- __IO uint32_t DR32;\r
- __IO uint32_t DR33;\r
- __IO uint32_t DR34;\r
- __IO uint32_t DR35;\r
- __IO uint32_t DR36;\r
- __IO uint32_t DR37;\r
- __IO uint32_t DR38;\r
- __IO uint32_t DR39;\r
- __IO uint32_t DR40;\r
- __IO uint32_t DR41;\r
- __IO uint32_t DR42;\r
-} BKP_TypeDef;\r
- \r
-/** \r
- * @brief Controller Area Network TxMailBox \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t TIR;\r
- __IO uint32_t TDTR;\r
- __IO uint32_t TDLR;\r
- __IO uint32_t TDHR;\r
-} CAN_TxMailBox_TypeDef;\r
-\r
-/** \r
- * @brief Controller Area Network FIFOMailBox \r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t RIR;\r
- __IO uint32_t RDTR;\r
- __IO uint32_t RDLR;\r
- __IO uint32_t RDHR;\r
-} CAN_FIFOMailBox_TypeDef;\r
-\r
-/** \r
- * @brief Controller Area Network FilterRegister \r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t FR1;\r
- __IO uint32_t FR2;\r
-} CAN_FilterRegister_TypeDef;\r
-\r
-/** \r
- * @brief Controller Area Network \r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t MCR;\r
- __IO uint32_t MSR;\r
- __IO uint32_t TSR;\r
- __IO uint32_t RF0R;\r
- __IO uint32_t RF1R;\r
- __IO uint32_t IER;\r
- __IO uint32_t ESR;\r
- __IO uint32_t BTR;\r
- uint32_t RESERVED0[88];\r
- CAN_TxMailBox_TypeDef sTxMailBox[3];\r
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];\r
- uint32_t RESERVED1[12];\r
- __IO uint32_t FMR;\r
- __IO uint32_t FM1R;\r
- uint32_t RESERVED2;\r
- __IO uint32_t FS1R;\r
- uint32_t RESERVED3;\r
- __IO uint32_t FFA1R;\r
- uint32_t RESERVED4;\r
- __IO uint32_t FA1R;\r
- uint32_t RESERVED5[8];\r
- CAN_FilterRegister_TypeDef sFilterRegister[14];\r
-} CAN_TypeDef;\r
-\r
-/** \r
- * @brief CRC calculation unit \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
- uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */\r
- uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ \r
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ \r
-} CRC_TypeDef;\r
-\r
-/** \r
- * @brief Digital to Analog Converter\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t SWTRIGR;\r
- __IO uint32_t DHR12R1;\r
- __IO uint32_t DHR12L1;\r
- __IO uint32_t DHR8R1;\r
- __IO uint32_t DHR12R2;\r
- __IO uint32_t DHR12L2;\r
- __IO uint32_t DHR8R2;\r
- __IO uint32_t DHR12RD;\r
- __IO uint32_t DHR12LD;\r
- __IO uint32_t DHR8RD;\r
- __IO uint32_t DOR1;\r
- __IO uint32_t DOR2;\r
-} DAC_TypeDef;\r
-\r
-/** \r
- * @brief Debug MCU\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t IDCODE;\r
- __IO uint32_t CR;\r
-}DBGMCU_TypeDef;\r
-\r
-/** \r
- * @brief DMA Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CCR;\r
- __IO uint32_t CNDTR;\r
- __IO uint32_t CPAR;\r
- __IO uint32_t CMAR;\r
-} DMA_Channel_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t ISR;\r
- __IO uint32_t IFCR;\r
-} DMA_TypeDef;\r
-\r
-\r
-\r
-/** \r
- * @brief External Interrupt/Event Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t IMR;\r
- __IO uint32_t EMR;\r
- __IO uint32_t RTSR;\r
- __IO uint32_t FTSR;\r
- __IO uint32_t SWIER;\r
- __IO uint32_t PR;\r
-} EXTI_TypeDef;\r
-\r
-/** \r
- * @brief FLASH Registers\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t ACR;\r
- __IO uint32_t KEYR;\r
- __IO uint32_t OPTKEYR;\r
- __IO uint32_t SR;\r
- __IO uint32_t CR;\r
- __IO uint32_t AR;\r
- __IO uint32_t RESERVED;\r
- __IO uint32_t OBR;\r
- __IO uint32_t WRPR;\r
-} FLASH_TypeDef;\r
-\r
-/** \r
- * @brief Option Bytes Registers\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint16_t RDP;\r
- __IO uint16_t USER;\r
- __IO uint16_t Data0;\r
- __IO uint16_t Data1;\r
- __IO uint16_t WRP0;\r
- __IO uint16_t WRP1;\r
- __IO uint16_t WRP2;\r
- __IO uint16_t WRP3;\r
-} OB_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Static Memory Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t BTCR[8]; \r
-} FSMC_Bank1_TypeDef; \r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank1E\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t BWTR[7];\r
-} FSMC_Bank1E_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank2\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */\r
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */\r
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */\r
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r
- uint32_t RESERVED0; /*!< Reserved, 0x70 */\r
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */\r
- uint32_t RESERVED1; /*!< Reserved, 0x78 */\r
- uint32_t RESERVED2; /*!< Reserved, 0x7C */\r
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */\r
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */\r
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */\r
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r
- uint32_t RESERVED3; /*!< Reserved, 0x90 */\r
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */\r
-} FSMC_Bank2_3_TypeDef; \r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank4\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR4;\r
- __IO uint32_t SR4;\r
- __IO uint32_t PMEM4;\r
- __IO uint32_t PATT4;\r
- __IO uint32_t PIO4; \r
-} FSMC_Bank4_TypeDef; \r
-\r
-/** \r
- * @brief General Purpose I/O\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CRL;\r
- __IO uint32_t CRH;\r
- __IO uint32_t IDR;\r
- __IO uint32_t ODR;\r
- __IO uint32_t BSRR;\r
- __IO uint32_t BRR;\r
- __IO uint32_t LCKR;\r
-} GPIO_TypeDef;\r
-\r
-/** \r
- * @brief Alternate Function I/O\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t EVCR;\r
- __IO uint32_t MAPR;\r
- __IO uint32_t EXTICR[4];\r
- uint32_t RESERVED0;\r
- __IO uint32_t MAPR2; \r
-} AFIO_TypeDef;\r
-/** \r
- * @brief Inter Integrated Circuit Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR1;\r
- __IO uint32_t CR2;\r
- __IO uint32_t OAR1;\r
- __IO uint32_t OAR2;\r
- __IO uint32_t DR;\r
- __IO uint32_t SR1;\r
- __IO uint32_t SR2;\r
- __IO uint32_t CCR;\r
- __IO uint32_t TRISE;\r
-} I2C_TypeDef;\r
-\r
-/** \r
- * @brief Independent WATCHDOG\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */\r
- __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */\r
- __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */\r
- __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */\r
-} IWDG_TypeDef;\r
-\r
-/** \r
- * @brief Power Control\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t CSR;\r
-} PWR_TypeDef;\r
-\r
-/** \r
- * @brief Reset and Clock Control\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR;\r
- __IO uint32_t CFGR;\r
- __IO uint32_t CIR;\r
- __IO uint32_t APB2RSTR;\r
- __IO uint32_t APB1RSTR;\r
- __IO uint32_t AHBENR;\r
- __IO uint32_t APB2ENR;\r
- __IO uint32_t APB1ENR;\r
- __IO uint32_t BDCR;\r
- __IO uint32_t CSR;\r
-\r
-\r
-} RCC_TypeDef;\r
-\r
-/** \r
- * @brief Real-Time Clock\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CRH;\r
- __IO uint32_t CRL;\r
- __IO uint32_t PRLH;\r
- __IO uint32_t PRLL;\r
- __IO uint32_t DIVH;\r
- __IO uint32_t DIVL;\r
- __IO uint32_t CNTH;\r
- __IO uint32_t CNTL;\r
- __IO uint32_t ALRH;\r
- __IO uint32_t ALRL;\r
-} RTC_TypeDef;\r
-\r
-/** \r
- * @brief SD host Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t POWER;\r
- __IO uint32_t CLKCR;\r
- __IO uint32_t ARG;\r
- __IO uint32_t CMD;\r
- __I uint32_t RESPCMD;\r
- __I uint32_t RESP1;\r
- __I uint32_t RESP2;\r
- __I uint32_t RESP3;\r
- __I uint32_t RESP4;\r
- __IO uint32_t DTIMER;\r
- __IO uint32_t DLEN;\r
- __IO uint32_t DCTRL;\r
- __I uint32_t DCOUNT;\r
- __I uint32_t STA;\r
- __IO uint32_t ICR;\r
- __IO uint32_t MASK;\r
- uint32_t RESERVED0[2];\r
- __I uint32_t FIFOCNT;\r
- uint32_t RESERVED1[13];\r
- __IO uint32_t FIFO;\r
-} SDIO_TypeDef;\r
-\r
-/** \r
- * @brief Serial Peripheral Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR1;\r
- __IO uint32_t CR2;\r
- __IO uint32_t SR;\r
- __IO uint32_t DR;\r
- __IO uint32_t CRCPR;\r
- __IO uint32_t RXCRCR;\r
- __IO uint32_t TXCRCR;\r
- __IO uint32_t I2SCFGR;\r
- __IO uint32_t I2SPR;\r
-} SPI_TypeDef;\r
-\r
-/**\r
- * @brief TIM Timers\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
- __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */\r
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\r
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
- __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */\r
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
- __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
- __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
- __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */\r
- __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */\r
-}TIM_TypeDef;\r
-\r
-\r
-/** \r
- * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */\r
- __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */\r
- __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */\r
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */\r
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */\r
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */\r
- __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */\r
-} USART_TypeDef;\r
-\r
-/** \r
- * @brief Universal Serial Bus Full Speed Device\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ \r
- __IO uint16_t RESERVED0; /*!< Reserved */ \r
- __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */\r
- __IO uint16_t RESERVED1; /*!< Reserved */ \r
- __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */\r
- __IO uint16_t RESERVED2; /*!< Reserved */ \r
- __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ \r
- __IO uint16_t RESERVED3; /*!< Reserved */ \r
- __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */\r
- __IO uint16_t RESERVED4; /*!< Reserved */ \r
- __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */\r
- __IO uint16_t RESERVED5; /*!< Reserved */ \r
- __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */\r
- __IO uint16_t RESERVED6; /*!< Reserved */ \r
- __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */\r
- __IO uint16_t RESERVED7[17]; /*!< Reserved */ \r
- __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */\r
- __IO uint16_t RESERVED8; /*!< Reserved */ \r
- __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */\r
- __IO uint16_t RESERVED9; /*!< Reserved */ \r
- __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */\r
- __IO uint16_t RESERVEDA; /*!< Reserved */ \r
- __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */\r
- __IO uint16_t RESERVEDB; /*!< Reserved */ \r
- __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */\r
- __IO uint16_t RESERVEDC; /*!< Reserved */ \r
-} USB_TypeDef;\r
-\r
-\r
-/** \r
- * @brief Window WATCHDOG\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
-} WWDG_TypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @addtogroup Peripheral_memory_map\r
- * @{\r
- */\r
-\r
-\r
-#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */\r
-#define FLASH_BANK1_END 0x0807FFFFU /*!< FLASH END address of bank1 */\r
-#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */\r
-#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */\r
-\r
-#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */\r
-#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */\r
-\r
-#define FSMC_BASE 0x60000000U /*!< FSMC base address */\r
-#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */\r
-\r
-/*!< Peripheral memory map */\r
-#define APB1PERIPH_BASE PERIPH_BASE\r
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)\r
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)\r
-\r
-#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)\r
-#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)\r
-#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)\r
-#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)\r
-#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)\r
-#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)\r
-#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)\r
-#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)\r
-#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)\r
-#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)\r
-#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)\r
-#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)\r
-#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)\r
-#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)\r
-#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)\r
-#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)\r
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
-#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)\r
-#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)\r
-#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)\r
-#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)\r
-#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)\r
-#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)\r
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)\r
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)\r
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)\r
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)\r
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)\r
-#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00U)\r
-#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000U)\r
-#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)\r
-#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)\r
-#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)\r
-#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)\r
-#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400U)\r
-#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)\r
-#define ADC3_BASE (APB2PERIPH_BASE + 0x00003C00U)\r
-\r
-#define SDIO_BASE (PERIPH_BASE + 0x00018000U)\r
-\r
-#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)\r
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)\r
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)\r
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)\r
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)\r
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)\r
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)\r
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)\r
-#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U)\r
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)\r
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)\r
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)\r
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)\r
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)\r
-#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)\r
-#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)\r
-\r
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */\r
-#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */\r
-#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */\r
-#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */\r
-\r
-\r
-#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */\r
-#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */\r
-#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */\r
-#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */\r
-#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */\r
-\r
-#define FSMC_BANK2 (FSMC_BASE + 0x10000000U) /*!< FSMC Bank2 base address */\r
-#define FSMC_BANK3 (FSMC_BASE + 0x20000000U) /*!< FSMC Bank3 base address */\r
-#define FSMC_BANK4 (FSMC_BASE + 0x30000000U) /*!< FSMC Bank4 base address */\r
-\r
-#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000U) /*!< FSMC Bank1 registers base address */\r
-#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104U) /*!< FSMC Bank1E registers base address */\r
-#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060U) /*!< FSMC Bank2/Bank3 registers base address */\r
-#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0U) /*!< FSMC Bank4 registers base address */\r
-\r
-#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */\r
-\r
-/* USB device FS */\r
-#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */\r
-#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */\r
-\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @addtogroup Peripheral_declaration\r
- * @{\r
- */ \r
-\r
-#define TIM2 ((TIM_TypeDef *)TIM2_BASE)\r
-#define TIM3 ((TIM_TypeDef *)TIM3_BASE)\r
-#define TIM4 ((TIM_TypeDef *)TIM4_BASE)\r
-#define TIM5 ((TIM_TypeDef *)TIM5_BASE)\r
-#define TIM6 ((TIM_TypeDef *)TIM6_BASE)\r
-#define TIM7 ((TIM_TypeDef *)TIM7_BASE)\r
-#define RTC ((RTC_TypeDef *)RTC_BASE)\r
-#define WWDG ((WWDG_TypeDef *)WWDG_BASE)\r
-#define IWDG ((IWDG_TypeDef *)IWDG_BASE)\r
-#define SPI2 ((SPI_TypeDef *)SPI2_BASE)\r
-#define SPI3 ((SPI_TypeDef *)SPI3_BASE)\r
-#define USART2 ((USART_TypeDef *)USART2_BASE)\r
-#define USART3 ((USART_TypeDef *)USART3_BASE)\r
-#define UART4 ((USART_TypeDef *)UART4_BASE)\r
-#define UART5 ((USART_TypeDef *)UART5_BASE)\r
-#define I2C1 ((I2C_TypeDef *)I2C1_BASE)\r
-#define I2C2 ((I2C_TypeDef *)I2C2_BASE)\r
-#define USB ((USB_TypeDef *)USB_BASE)\r
-#define CAN1 ((CAN_TypeDef *)CAN1_BASE)\r
-#define BKP ((BKP_TypeDef *)BKP_BASE)\r
-#define PWR ((PWR_TypeDef *)PWR_BASE)\r
-#define DAC1 ((DAC_TypeDef *)DAC_BASE)\r
-#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */\r
-#define AFIO ((AFIO_TypeDef *)AFIO_BASE)\r
-#define EXTI ((EXTI_TypeDef *)EXTI_BASE)\r
-#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)\r
-#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)\r
-#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)\r
-#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)\r
-#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)\r
-#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)\r
-#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)\r
-#define ADC1 ((ADC_TypeDef *)ADC1_BASE)\r
-#define ADC2 ((ADC_TypeDef *)ADC2_BASE)\r
-#define ADC3 ((ADC_TypeDef *)ADC3_BASE)\r
-#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)\r
-#define TIM1 ((TIM_TypeDef *)TIM1_BASE)\r
-#define SPI1 ((SPI_TypeDef *)SPI1_BASE)\r
-#define TIM8 ((TIM_TypeDef *)TIM8_BASE)\r
-#define USART1 ((USART_TypeDef *)USART1_BASE)\r
-#define SDIO ((SDIO_TypeDef *)SDIO_BASE)\r
-#define DMA1 ((DMA_TypeDef *)DMA1_BASE)\r
-#define DMA2 ((DMA_TypeDef *)DMA2_BASE)\r
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)\r
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)\r
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)\r
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)\r
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)\r
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)\r
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)\r
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)\r
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)\r
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)\r
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)\r
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)\r
-#define RCC ((RCC_TypeDef *)RCC_BASE)\r
-#define CRC ((CRC_TypeDef *)CRC_BASE)\r
-#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)\r
-#define OB ((OB_TypeDef *)OB_BASE)\r
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)\r
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)\r
-#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)\r
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)\r
-#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Exported_constants\r
- * @{\r
- */\r
- \r
- /** @addtogroup Peripheral_Registers_Bits_Definition\r
- * @{\r
- */\r
- \r
-/******************************************************************************/\r
-/* Peripheral Registers_Bits_Definition */\r
-/******************************************************************************/\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* CRC calculation unit (CRC) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for CRC_DR register *********************/\r
-#define CRC_DR_DR_Pos (0U) \r
-#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */\r
-#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */\r
-\r
-/******************* Bit definition for CRC_IDR register ********************/\r
-#define CRC_IDR_IDR_Pos (0U) \r
-#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */\r
-#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */\r
-\r
-/******************** Bit definition for CRC_CR register ********************/\r
-#define CRC_CR_RESET_Pos (0U) \r
-#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */\r
-#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Power Control */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for PWR_CR register ********************/\r
-#define PWR_CR_LPDS_Pos (0U) \r
-#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */\r
-#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */\r
-#define PWR_CR_PDDS_Pos (1U) \r
-#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */\r
-#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */\r
-#define PWR_CR_CWUF_Pos (2U) \r
-#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */\r
-#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */\r
-#define PWR_CR_CSBF_Pos (3U) \r
-#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */\r
-#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */\r
-#define PWR_CR_PVDE_Pos (4U) \r
-#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */\r
-#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */\r
-\r
-#define PWR_CR_PLS_Pos (5U) \r
-#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */\r
-#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */\r
-#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */\r
-#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */\r
-#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */\r
-\r
-/*!< PVD level configuration */\r
-#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */\r
-#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */\r
-#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */\r
-#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */\r
-#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */\r
-#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */\r
-#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */\r
-#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */\r
-\r
-/* Legacy defines */\r
-#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0\r
-#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1\r
-#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2\r
-#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3\r
-#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4\r
-#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5\r
-#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6\r
-#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7\r
-\r
-#define PWR_CR_DBP_Pos (8U) \r
-#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */\r
-#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */\r
-\r
-\r
-/******************* Bit definition for PWR_CSR register ********************/\r
-#define PWR_CSR_WUF_Pos (0U) \r
-#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */\r
-#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */\r
-#define PWR_CSR_SBF_Pos (1U) \r
-#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */\r
-#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */\r
-#define PWR_CSR_PVDO_Pos (2U) \r
-#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */\r
-#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */\r
-#define PWR_CSR_EWUP_Pos (8U) \r
-#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */\r
-#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Backup registers */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for BKP_DR1 register ********************/\r
-#define BKP_DR1_D_Pos (0U) \r
-#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR2 register ********************/\r
-#define BKP_DR2_D_Pos (0U) \r
-#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR3 register ********************/\r
-#define BKP_DR3_D_Pos (0U) \r
-#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR4 register ********************/\r
-#define BKP_DR4_D_Pos (0U) \r
-#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR5 register ********************/\r
-#define BKP_DR5_D_Pos (0U) \r
-#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR6 register ********************/\r
-#define BKP_DR6_D_Pos (0U) \r
-#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR7 register ********************/\r
-#define BKP_DR7_D_Pos (0U) \r
-#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR8 register ********************/\r
-#define BKP_DR8_D_Pos (0U) \r
-#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR9 register ********************/\r
-#define BKP_DR9_D_Pos (0U) \r
-#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR10 register *******************/\r
-#define BKP_DR10_D_Pos (0U) \r
-#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR11 register *******************/\r
-#define BKP_DR11_D_Pos (0U) \r
-#define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR12 register *******************/\r
-#define BKP_DR12_D_Pos (0U) \r
-#define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR13 register *******************/\r
-#define BKP_DR13_D_Pos (0U) \r
-#define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR14 register *******************/\r
-#define BKP_DR14_D_Pos (0U) \r
-#define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR15 register *******************/\r
-#define BKP_DR15_D_Pos (0U) \r
-#define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR16 register *******************/\r
-#define BKP_DR16_D_Pos (0U) \r
-#define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR17 register *******************/\r
-#define BKP_DR17_D_Pos (0U) \r
-#define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */\r
-\r
-/****************** Bit definition for BKP_DR18 register ********************/\r
-#define BKP_DR18_D_Pos (0U) \r
-#define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR19 register *******************/\r
-#define BKP_DR19_D_Pos (0U) \r
-#define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR20 register *******************/\r
-#define BKP_DR20_D_Pos (0U) \r
-#define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR21 register *******************/\r
-#define BKP_DR21_D_Pos (0U) \r
-#define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR22 register *******************/\r
-#define BKP_DR22_D_Pos (0U) \r
-#define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR23 register *******************/\r
-#define BKP_DR23_D_Pos (0U) \r
-#define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR24 register *******************/\r
-#define BKP_DR24_D_Pos (0U) \r
-#define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR25 register *******************/\r
-#define BKP_DR25_D_Pos (0U) \r
-#define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR26 register *******************/\r
-#define BKP_DR26_D_Pos (0U) \r
-#define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR27 register *******************/\r
-#define BKP_DR27_D_Pos (0U) \r
-#define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR28 register *******************/\r
-#define BKP_DR28_D_Pos (0U) \r
-#define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR29 register *******************/\r
-#define BKP_DR29_D_Pos (0U) \r
-#define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR30 register *******************/\r
-#define BKP_DR30_D_Pos (0U) \r
-#define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR31 register *******************/\r
-#define BKP_DR31_D_Pos (0U) \r
-#define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR32 register *******************/\r
-#define BKP_DR32_D_Pos (0U) \r
-#define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR33 register *******************/\r
-#define BKP_DR33_D_Pos (0U) \r
-#define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR34 register *******************/\r
-#define BKP_DR34_D_Pos (0U) \r
-#define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR35 register *******************/\r
-#define BKP_DR35_D_Pos (0U) \r
-#define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR36 register *******************/\r
-#define BKP_DR36_D_Pos (0U) \r
-#define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR37 register *******************/\r
-#define BKP_DR37_D_Pos (0U) \r
-#define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR38 register *******************/\r
-#define BKP_DR38_D_Pos (0U) \r
-#define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR39 register *******************/\r
-#define BKP_DR39_D_Pos (0U) \r
-#define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR40 register *******************/\r
-#define BKP_DR40_D_Pos (0U) \r
-#define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR41 register *******************/\r
-#define BKP_DR41_D_Pos (0U) \r
-#define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */\r
-\r
-/******************* Bit definition for BKP_DR42 register *******************/\r
-#define BKP_DR42_D_Pos (0U) \r
-#define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /*!< 0x0000FFFF */\r
-#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */\r
-\r
-#define RTC_BKP_NUMBER 42\r
-\r
-/****************** Bit definition for BKP_RTCCR register *******************/\r
-#define BKP_RTCCR_CAL_Pos (0U) \r
-#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */\r
-#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */\r
-#define BKP_RTCCR_CCO_Pos (7U) \r
-#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */\r
-#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */\r
-#define BKP_RTCCR_ASOE_Pos (8U) \r
-#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */\r
-#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */\r
-#define BKP_RTCCR_ASOS_Pos (9U) \r
-#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */\r
-#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */\r
-\r
-/******************** Bit definition for BKP_CR register ********************/\r
-#define BKP_CR_TPE_Pos (0U) \r
-#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */\r
-#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */\r
-#define BKP_CR_TPAL_Pos (1U) \r
-#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */\r
-#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */\r
-\r
-/******************* Bit definition for BKP_CSR register ********************/\r
-#define BKP_CSR_CTE_Pos (0U) \r
-#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */\r
-#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */\r
-#define BKP_CSR_CTI_Pos (1U) \r
-#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */\r
-#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */\r
-#define BKP_CSR_TPIE_Pos (2U) \r
-#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */\r
-#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */\r
-#define BKP_CSR_TEF_Pos (8U) \r
-#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */\r
-#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */\r
-#define BKP_CSR_TIF_Pos (9U) \r
-#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */\r
-#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Reset and Clock Control */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for RCC_CR register ********************/\r
-#define RCC_CR_HSION_Pos (0U) \r
-#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */\r
-#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */\r
-#define RCC_CR_HSIRDY_Pos (1U) \r
-#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */\r
-#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */\r
-#define RCC_CR_HSITRIM_Pos (3U) \r
-#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */\r
-#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */\r
-#define RCC_CR_HSICAL_Pos (8U) \r
-#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */\r
-#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */\r
-#define RCC_CR_HSEON_Pos (16U) \r
-#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */\r
-#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */\r
-#define RCC_CR_HSERDY_Pos (17U) \r
-#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */\r
-#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */\r
-#define RCC_CR_HSEBYP_Pos (18U) \r
-#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */\r
-#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */\r
-#define RCC_CR_CSSON_Pos (19U) \r
-#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */\r
-#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */\r
-#define RCC_CR_PLLON_Pos (24U) \r
-#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */\r
-#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */\r
-#define RCC_CR_PLLRDY_Pos (25U) \r
-#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */\r
-#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */\r
-\r
-\r
-/******************* Bit definition for RCC_CFGR register *******************/\r
-/*!< SW configuration */\r
-#define RCC_CFGR_SW_Pos (0U) \r
-#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */\r
-#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */\r
-#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */\r
-#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */\r
-\r
-#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */\r
-#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */\r
-#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */\r
-\r
-/*!< SWS configuration */\r
-#define RCC_CFGR_SWS_Pos (2U) \r
-#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */\r
-#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */\r
-#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */\r
-#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */\r
-\r
-#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */\r
-#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */\r
-#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */\r
-\r
-/*!< HPRE configuration */\r
-#define RCC_CFGR_HPRE_Pos (4U) \r
-#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */\r
-#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */\r
-#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */\r
-#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */\r
-#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */\r
-#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */\r
-\r
-#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */\r
-#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */\r
-#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */\r
-#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */\r
-#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */\r
-#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */\r
-#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */\r
-#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */\r
-#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */\r
-\r
-/*!< PPRE1 configuration */\r
-#define RCC_CFGR_PPRE1_Pos (8U) \r
-#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */\r
-#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */\r
-#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */\r
-#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */\r
-#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */\r
-\r
-#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */\r
-\r
-/*!< PPRE2 configuration */\r
-#define RCC_CFGR_PPRE2_Pos (11U) \r
-#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */\r
-#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */\r
-#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */\r
-#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */\r
-#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */\r
-\r
-#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */\r
-\r
-/*!< ADCPPRE configuration */\r
-#define RCC_CFGR_ADCPRE_Pos (14U) \r
-#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */\r
-#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */\r
-#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */\r
-#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */\r
-\r
-#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */\r
-#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */\r
-#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */\r
-#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */\r
-\r
-#define RCC_CFGR_PLLSRC_Pos (16U) \r
-#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */\r
-#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */\r
-\r
-#define RCC_CFGR_PLLXTPRE_Pos (17U) \r
-#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */\r
-#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */\r
-\r
-/*!< PLLMUL configuration */\r
-#define RCC_CFGR_PLLMULL_Pos (18U) \r
-#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */\r
-#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
-#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */\r
-#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */\r
-#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */\r
-#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */\r
-\r
-#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */\r
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */\r
-\r
-#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */\r
-#define RCC_CFGR_PLLMULL3_Pos (18U) \r
-#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */\r
-#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */\r
-#define RCC_CFGR_PLLMULL4_Pos (19U) \r
-#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */\r
-#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */\r
-#define RCC_CFGR_PLLMULL5_Pos (18U) \r
-#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */\r
-#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */\r
-#define RCC_CFGR_PLLMULL6_Pos (20U) \r
-#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */\r
-#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */\r
-#define RCC_CFGR_PLLMULL7_Pos (18U) \r
-#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */\r
-#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */\r
-#define RCC_CFGR_PLLMULL8_Pos (19U) \r
-#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */\r
-#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */\r
-#define RCC_CFGR_PLLMULL9_Pos (18U) \r
-#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */\r
-#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */\r
-#define RCC_CFGR_PLLMULL10_Pos (21U) \r
-#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */\r
-#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */\r
-#define RCC_CFGR_PLLMULL11_Pos (18U) \r
-#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */\r
-#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */\r
-#define RCC_CFGR_PLLMULL12_Pos (19U) \r
-#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */\r
-#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */\r
-#define RCC_CFGR_PLLMULL13_Pos (18U) \r
-#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */\r
-#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */\r
-#define RCC_CFGR_PLLMULL14_Pos (20U) \r
-#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */\r
-#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */\r
-#define RCC_CFGR_PLLMULL15_Pos (18U) \r
-#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */\r
-#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */\r
-#define RCC_CFGR_PLLMULL16_Pos (19U) \r
-#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */\r
-#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */\r
-#define RCC_CFGR_USBPRE_Pos (22U) \r
-#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */\r
-#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */\r
-\r
-/*!< MCO configuration */\r
-#define RCC_CFGR_MCO_Pos (24U) \r
-#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */\r
-#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
-#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */\r
-#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */\r
-#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */\r
-\r
-#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */\r
-#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */\r
-#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */\r
-#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */\r
-#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */\r
-\r
- /* Reference defines */\r
- #define RCC_CFGR_MCOSEL RCC_CFGR_MCO\r
- #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0\r
- #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1\r
- #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2\r
- #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK\r
- #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK\r
- #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI\r
- #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE\r
- #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2\r
-\r
-/*!<****************** Bit definition for RCC_CIR register ********************/\r
-#define RCC_CIR_LSIRDYF_Pos (0U) \r
-#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */\r
-#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */\r
-#define RCC_CIR_LSERDYF_Pos (1U) \r
-#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */\r
-#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */\r
-#define RCC_CIR_HSIRDYF_Pos (2U) \r
-#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */\r
-#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */\r
-#define RCC_CIR_HSERDYF_Pos (3U) \r
-#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */\r
-#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */\r
-#define RCC_CIR_PLLRDYF_Pos (4U) \r
-#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */\r
-#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */\r
-#define RCC_CIR_CSSF_Pos (7U) \r
-#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */\r
-#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */\r
-#define RCC_CIR_LSIRDYIE_Pos (8U) \r
-#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */\r
-#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */\r
-#define RCC_CIR_LSERDYIE_Pos (9U) \r
-#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */\r
-#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */\r
-#define RCC_CIR_HSIRDYIE_Pos (10U) \r
-#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */\r
-#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */\r
-#define RCC_CIR_HSERDYIE_Pos (11U) \r
-#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */\r
-#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */\r
-#define RCC_CIR_PLLRDYIE_Pos (12U) \r
-#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */\r
-#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */\r
-#define RCC_CIR_LSIRDYC_Pos (16U) \r
-#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */\r
-#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */\r
-#define RCC_CIR_LSERDYC_Pos (17U) \r
-#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */\r
-#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */\r
-#define RCC_CIR_HSIRDYC_Pos (18U) \r
-#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */\r
-#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */\r
-#define RCC_CIR_HSERDYC_Pos (19U) \r
-#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */\r
-#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */\r
-#define RCC_CIR_PLLRDYC_Pos (20U) \r
-#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */\r
-#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */\r
-#define RCC_CIR_CSSC_Pos (23U) \r
-#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */\r
-#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */\r
-\r
-\r
-/***************** Bit definition for RCC_APB2RSTR register *****************/\r
-#define RCC_APB2RSTR_AFIORST_Pos (0U) \r
-#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */\r
-#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */\r
-#define RCC_APB2RSTR_IOPARST_Pos (2U) \r
-#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */\r
-#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */\r
-#define RCC_APB2RSTR_IOPBRST_Pos (3U) \r
-#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */\r
-#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */\r
-#define RCC_APB2RSTR_IOPCRST_Pos (4U) \r
-#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */\r
-#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */\r
-#define RCC_APB2RSTR_IOPDRST_Pos (5U) \r
-#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */\r
-#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */\r
-#define RCC_APB2RSTR_ADC1RST_Pos (9U) \r
-#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */\r
-#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */\r
-\r
-#define RCC_APB2RSTR_ADC2RST_Pos (10U) \r
-#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */\r
-#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */\r
-\r
-#define RCC_APB2RSTR_TIM1RST_Pos (11U) \r
-#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */\r
-#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */\r
-#define RCC_APB2RSTR_SPI1RST_Pos (12U) \r
-#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\r
-#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */\r
-#define RCC_APB2RSTR_USART1RST_Pos (14U) \r
-#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */\r
-#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */\r
-\r
-\r
-#define RCC_APB2RSTR_IOPERST_Pos (6U) \r
-#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */\r
-#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */\r
-\r
-#define RCC_APB2RSTR_IOPFRST_Pos (7U) \r
-#define RCC_APB2RSTR_IOPFRST_Msk (0x1U << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */\r
-#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /*!< I/O port F reset */\r
-#define RCC_APB2RSTR_IOPGRST_Pos (8U) \r
-#define RCC_APB2RSTR_IOPGRST_Msk (0x1U << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */\r
-#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /*!< I/O port G reset */\r
-#define RCC_APB2RSTR_TIM8RST_Pos (13U) \r
-#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */\r
-#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 Timer reset */\r
-#define RCC_APB2RSTR_ADC3RST_Pos (15U) \r
-#define RCC_APB2RSTR_ADC3RST_Msk (0x1U << RCC_APB2RSTR_ADC3RST_Pos) /*!< 0x00008000 */\r
-#define RCC_APB2RSTR_ADC3RST RCC_APB2RSTR_ADC3RST_Msk /*!< ADC3 interface reset */\r
-\r
-\r
-\r
-/***************** Bit definition for RCC_APB1RSTR register *****************/\r
-#define RCC_APB1RSTR_TIM2RST_Pos (0U) \r
-#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */\r
-#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */\r
-#define RCC_APB1RSTR_TIM3RST_Pos (1U) \r
-#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */\r
-#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */\r
-#define RCC_APB1RSTR_WWDGRST_Pos (11U) \r
-#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */\r
-#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */\r
-#define RCC_APB1RSTR_USART2RST_Pos (17U) \r
-#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\r
-#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */\r
-#define RCC_APB1RSTR_I2C1RST_Pos (21U) \r
-#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */\r
-#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */\r
-\r
-#define RCC_APB1RSTR_CAN1RST_Pos (25U) \r
-#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */\r
-#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */\r
-\r
-#define RCC_APB1RSTR_BKPRST_Pos (27U) \r
-#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */\r
-#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */\r
-#define RCC_APB1RSTR_PWRRST_Pos (28U) \r
-#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */\r
-#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */\r
-\r
-#define RCC_APB1RSTR_TIM4RST_Pos (2U) \r
-#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */\r
-#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */\r
-#define RCC_APB1RSTR_SPI2RST_Pos (14U) \r
-#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */\r
-#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */\r
-#define RCC_APB1RSTR_USART3RST_Pos (18U) \r
-#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\r
-#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */\r
-#define RCC_APB1RSTR_I2C2RST_Pos (22U) \r
-#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */\r
-#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */\r
-\r
-#define RCC_APB1RSTR_USBRST_Pos (23U) \r
-#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */\r
-#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */\r
-\r
-#define RCC_APB1RSTR_TIM5RST_Pos (3U) \r
-#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */\r
-#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */\r
-#define RCC_APB1RSTR_TIM6RST_Pos (4U) \r
-#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */\r
-#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */\r
-#define RCC_APB1RSTR_TIM7RST_Pos (5U) \r
-#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */\r
-#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */\r
-#define RCC_APB1RSTR_SPI3RST_Pos (15U) \r
-#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */\r
-#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */\r
-#define RCC_APB1RSTR_UART4RST_Pos (19U) \r
-#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\r
-#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */\r
-#define RCC_APB1RSTR_UART5RST_Pos (20U) \r
-#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\r
-#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */\r
-\r
-\r
-\r
-\r
-#define RCC_APB1RSTR_DACRST_Pos (29U) \r
-#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */\r
-#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */\r
-\r
-/****************** Bit definition for RCC_AHBENR register ******************/\r
-#define RCC_AHBENR_DMA1EN_Pos (0U) \r
-#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */\r
-#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */\r
-#define RCC_AHBENR_SRAMEN_Pos (2U) \r
-#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */\r
-#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */\r
-#define RCC_AHBENR_FLITFEN_Pos (4U) \r
-#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */\r
-#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */\r
-#define RCC_AHBENR_CRCEN_Pos (6U) \r
-#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */\r
-#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */\r
-\r
-#define RCC_AHBENR_DMA2EN_Pos (1U) \r
-#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */\r
-#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */\r
-\r
-#define RCC_AHBENR_FSMCEN_Pos (8U) \r
-#define RCC_AHBENR_FSMCEN_Msk (0x1U << RCC_AHBENR_FSMCEN_Pos) /*!< 0x00000100 */\r
-#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */\r
-#define RCC_AHBENR_SDIOEN_Pos (10U) \r
-#define RCC_AHBENR_SDIOEN_Msk (0x1U << RCC_AHBENR_SDIOEN_Pos) /*!< 0x00000400 */\r
-#define RCC_AHBENR_SDIOEN RCC_AHBENR_SDIOEN_Msk /*!< SDIO clock enable */\r
-\r
-\r
-/****************** Bit definition for RCC_APB2ENR register *****************/\r
-#define RCC_APB2ENR_AFIOEN_Pos (0U) \r
-#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */\r
-#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */\r
-#define RCC_APB2ENR_IOPAEN_Pos (2U) \r
-#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */\r
-#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */\r
-#define RCC_APB2ENR_IOPBEN_Pos (3U) \r
-#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */\r
-#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */\r
-#define RCC_APB2ENR_IOPCEN_Pos (4U) \r
-#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */\r
-#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */\r
-#define RCC_APB2ENR_IOPDEN_Pos (5U) \r
-#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */\r
-#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */\r
-#define RCC_APB2ENR_ADC1EN_Pos (9U) \r
-#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */\r
-#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */\r
-\r
-#define RCC_APB2ENR_ADC2EN_Pos (10U) \r
-#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */\r
-#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */\r
-\r
-#define RCC_APB2ENR_TIM1EN_Pos (11U) \r
-#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */\r
-#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */\r
-#define RCC_APB2ENR_SPI1EN_Pos (12U) \r
-#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\r
-#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */\r
-#define RCC_APB2ENR_USART1EN_Pos (14U) \r
-#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */\r
-#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */\r
-\r
-\r
-#define RCC_APB2ENR_IOPEEN_Pos (6U) \r
-#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */\r
-#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */\r
-\r
-#define RCC_APB2ENR_IOPFEN_Pos (7U) \r
-#define RCC_APB2ENR_IOPFEN_Msk (0x1U << RCC_APB2ENR_IOPFEN_Pos) /*!< 0x00000080 */\r
-#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /*!< I/O port F clock enable */\r
-#define RCC_APB2ENR_IOPGEN_Pos (8U) \r
-#define RCC_APB2ENR_IOPGEN_Msk (0x1U << RCC_APB2ENR_IOPGEN_Pos) /*!< 0x00000100 */\r
-#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /*!< I/O port G clock enable */\r
-#define RCC_APB2ENR_TIM8EN_Pos (13U) \r
-#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */\r
-#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 Timer clock enable */\r
-#define RCC_APB2ENR_ADC3EN_Pos (15U) \r
-#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00008000 */\r
-#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk /*!< DMA1 clock enable */\r
-\r
-\r
-\r
-/***************** Bit definition for RCC_APB1ENR register ******************/\r
-#define RCC_APB1ENR_TIM2EN_Pos (0U) \r
-#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */\r
-#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/\r
-#define RCC_APB1ENR_TIM3EN_Pos (1U) \r
-#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */\r
-#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */\r
-#define RCC_APB1ENR_WWDGEN_Pos (11U) \r
-#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */\r
-#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */\r
-#define RCC_APB1ENR_USART2EN_Pos (17U) \r
-#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */\r
-#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */\r
-#define RCC_APB1ENR_I2C1EN_Pos (21U) \r
-#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */\r
-#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */\r
-\r
-#define RCC_APB1ENR_CAN1EN_Pos (25U) \r
-#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */\r
-#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */\r
-\r
-#define RCC_APB1ENR_BKPEN_Pos (27U) \r
-#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */\r
-#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */\r
-#define RCC_APB1ENR_PWREN_Pos (28U) \r
-#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */\r
-#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */\r
-\r
-#define RCC_APB1ENR_TIM4EN_Pos (2U) \r
-#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */\r
-#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */\r
-#define RCC_APB1ENR_SPI2EN_Pos (14U) \r
-#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */\r
-#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */\r
-#define RCC_APB1ENR_USART3EN_Pos (18U) \r
-#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */\r
-#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */\r
-#define RCC_APB1ENR_I2C2EN_Pos (22U) \r
-#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */\r
-#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */\r
-\r
-#define RCC_APB1ENR_USBEN_Pos (23U) \r
-#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */\r
-#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */\r
-\r
-#define RCC_APB1ENR_TIM5EN_Pos (3U) \r
-#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */\r
-#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */\r
-#define RCC_APB1ENR_TIM6EN_Pos (4U) \r
-#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */\r
-#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */\r
-#define RCC_APB1ENR_TIM7EN_Pos (5U) \r
-#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */\r
-#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */\r
-#define RCC_APB1ENR_SPI3EN_Pos (15U) \r
-#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */\r
-#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */\r
-#define RCC_APB1ENR_UART4EN_Pos (19U) \r
-#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */\r
-#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */\r
-#define RCC_APB1ENR_UART5EN_Pos (20U) \r
-#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */\r
-#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */\r
-\r
-\r
-\r
-\r
-#define RCC_APB1ENR_DACEN_Pos (29U) \r
-#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */\r
-#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */\r
-\r
-/******************* Bit definition for RCC_BDCR register *******************/\r
-#define RCC_BDCR_LSEON_Pos (0U) \r
-#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */\r
-#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */\r
-#define RCC_BDCR_LSERDY_Pos (1U) \r
-#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */\r
-#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */\r
-#define RCC_BDCR_LSEBYP_Pos (2U) \r
-#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */\r
-#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */\r
-\r
-#define RCC_BDCR_RTCSEL_Pos (8U) \r
-#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */\r
-#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
-#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */\r
-#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */\r
-\r
-/*!< RTC congiguration */\r
-#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */\r
-#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */\r
-#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */\r
-#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */\r
-\r
-#define RCC_BDCR_RTCEN_Pos (15U) \r
-#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */\r
-#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */\r
-#define RCC_BDCR_BDRST_Pos (16U) \r
-#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */\r
-#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */\r
-\r
-/******************* Bit definition for RCC_CSR register ********************/ \r
-#define RCC_CSR_LSION_Pos (0U) \r
-#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */\r
-#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */\r
-#define RCC_CSR_LSIRDY_Pos (1U) \r
-#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */\r
-#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */\r
-#define RCC_CSR_RMVF_Pos (24U) \r
-#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */\r
-#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */\r
-#define RCC_CSR_PINRSTF_Pos (26U) \r
-#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */\r
-#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */\r
-#define RCC_CSR_PORRSTF_Pos (27U) \r
-#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */\r
-#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */\r
-#define RCC_CSR_SFTRSTF_Pos (28U) \r
-#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */\r
-#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */\r
-#define RCC_CSR_IWDGRSTF_Pos (29U) \r
-#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */\r
-#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */\r
-#define RCC_CSR_WWDGRSTF_Pos (30U) \r
-#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */\r
-#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */\r
-#define RCC_CSR_LPWRRSTF_Pos (31U) \r
-#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */\r
-#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */\r
-\r
-\r
- \r
-/******************************************************************************/\r
-/* */\r
-/* General Purpose and Alternate Function I/O */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for GPIO_CRL register *******************/\r
-#define GPIO_CRL_MODE_Pos (0U) \r
-#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */\r
-#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */\r
-\r
-#define GPIO_CRL_MODE0_Pos (0U) \r
-#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */\r
-#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */\r
-#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */\r
-#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */\r
-\r
-#define GPIO_CRL_MODE1_Pos (4U) \r
-#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */\r
-#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */\r
-#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */\r
-#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */\r
-\r
-#define GPIO_CRL_MODE2_Pos (8U) \r
-#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */\r
-#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */\r
-#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */\r
-#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */\r
-\r
-#define GPIO_CRL_MODE3_Pos (12U) \r
-#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */\r
-#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */\r
-#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */\r
-#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */\r
-\r
-#define GPIO_CRL_MODE4_Pos (16U) \r
-#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */\r
-#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */\r
-#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */\r
-#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */\r
-\r
-#define GPIO_CRL_MODE5_Pos (20U) \r
-#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */\r
-#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */\r
-#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */\r
-#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */\r
-\r
-#define GPIO_CRL_MODE6_Pos (24U) \r
-#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */\r
-#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */\r
-#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */\r
-#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */\r
-\r
-#define GPIO_CRL_MODE7_Pos (28U) \r
-#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */\r
-#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */\r
-#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */\r
-#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */\r
-\r
-#define GPIO_CRL_CNF_Pos (2U) \r
-#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */\r
-#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */\r
-\r
-#define GPIO_CRL_CNF0_Pos (2U) \r
-#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */\r
-#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */\r
-#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */\r
-#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */\r
-\r
-#define GPIO_CRL_CNF1_Pos (6U) \r
-#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */\r
-#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */\r
-#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */\r
-#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */\r
-\r
-#define GPIO_CRL_CNF2_Pos (10U) \r
-#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */\r
-#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */\r
-#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */\r
-#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */\r
-\r
-#define GPIO_CRL_CNF3_Pos (14U) \r
-#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */\r
-#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */\r
-#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */\r
-#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */\r
-\r
-#define GPIO_CRL_CNF4_Pos (18U) \r
-#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */\r
-#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */\r
-#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */\r
-#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */\r
-\r
-#define GPIO_CRL_CNF5_Pos (22U) \r
-#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */\r
-#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */\r
-#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */\r
-#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */\r
-\r
-#define GPIO_CRL_CNF6_Pos (26U) \r
-#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */\r
-#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */\r
-#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */\r
-#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */\r
-\r
-#define GPIO_CRL_CNF7_Pos (30U) \r
-#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */\r
-#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */\r
-#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */\r
-#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */\r
-\r
-/******************* Bit definition for GPIO_CRH register *******************/\r
-#define GPIO_CRH_MODE_Pos (0U) \r
-#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */\r
-#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */\r
-\r
-#define GPIO_CRH_MODE8_Pos (0U) \r
-#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */\r
-#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */\r
-#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */\r
-#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */\r
-\r
-#define GPIO_CRH_MODE9_Pos (4U) \r
-#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */\r
-#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */\r
-#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */\r
-#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */\r
-\r
-#define GPIO_CRH_MODE10_Pos (8U) \r
-#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */\r
-#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */\r
-#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */\r
-#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */\r
-\r
-#define GPIO_CRH_MODE11_Pos (12U) \r
-#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */\r
-#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */\r
-#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */\r
-#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */\r
-\r
-#define GPIO_CRH_MODE12_Pos (16U) \r
-#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */\r
-#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */\r
-#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */\r
-#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */\r
-\r
-#define GPIO_CRH_MODE13_Pos (20U) \r
-#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */\r
-#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */\r
-#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */\r
-#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */\r
-\r
-#define GPIO_CRH_MODE14_Pos (24U) \r
-#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */\r
-#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */\r
-#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */\r
-#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */\r
-\r
-#define GPIO_CRH_MODE15_Pos (28U) \r
-#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */\r
-#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */\r
-#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */\r
-#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */\r
-\r
-#define GPIO_CRH_CNF_Pos (2U) \r
-#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */\r
-#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */\r
-\r
-#define GPIO_CRH_CNF8_Pos (2U) \r
-#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */\r
-#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */\r
-#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */\r
-#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */\r
-\r
-#define GPIO_CRH_CNF9_Pos (6U) \r
-#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */\r
-#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */\r
-#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */\r
-#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */\r
-\r
-#define GPIO_CRH_CNF10_Pos (10U) \r
-#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */\r
-#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */\r
-#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */\r
-#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */\r
-\r
-#define GPIO_CRH_CNF11_Pos (14U) \r
-#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */\r
-#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */\r
-#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */\r
-#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */\r
-\r
-#define GPIO_CRH_CNF12_Pos (18U) \r
-#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */\r
-#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */\r
-#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */\r
-#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */\r
-\r
-#define GPIO_CRH_CNF13_Pos (22U) \r
-#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */\r
-#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */\r
-#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */\r
-#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */\r
-\r
-#define GPIO_CRH_CNF14_Pos (26U) \r
-#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */\r
-#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */\r
-#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */\r
-#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */\r
-\r
-#define GPIO_CRH_CNF15_Pos (30U) \r
-#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */\r
-#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */\r
-#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */\r
-#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */\r
-\r
-/*!<****************** Bit definition for GPIO_IDR register *******************/\r
-#define GPIO_IDR_IDR0_Pos (0U) \r
-#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */\r
-#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */\r
-#define GPIO_IDR_IDR1_Pos (1U) \r
-#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */\r
-#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */\r
-#define GPIO_IDR_IDR2_Pos (2U) \r
-#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */\r
-#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */\r
-#define GPIO_IDR_IDR3_Pos (3U) \r
-#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */\r
-#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */\r
-#define GPIO_IDR_IDR4_Pos (4U) \r
-#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */\r
-#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */\r
-#define GPIO_IDR_IDR5_Pos (5U) \r
-#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */\r
-#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */\r
-#define GPIO_IDR_IDR6_Pos (6U) \r
-#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */\r
-#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */\r
-#define GPIO_IDR_IDR7_Pos (7U) \r
-#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */\r
-#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */\r
-#define GPIO_IDR_IDR8_Pos (8U) \r
-#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */\r
-#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */\r
-#define GPIO_IDR_IDR9_Pos (9U) \r
-#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */\r
-#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */\r
-#define GPIO_IDR_IDR10_Pos (10U) \r
-#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */\r
-#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */\r
-#define GPIO_IDR_IDR11_Pos (11U) \r
-#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */\r
-#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */\r
-#define GPIO_IDR_IDR12_Pos (12U) \r
-#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */\r
-#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */\r
-#define GPIO_IDR_IDR13_Pos (13U) \r
-#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */\r
-#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */\r
-#define GPIO_IDR_IDR14_Pos (14U) \r
-#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */\r
-#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */\r
-#define GPIO_IDR_IDR15_Pos (15U) \r
-#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */\r
-#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */\r
-\r
-/******************* Bit definition for GPIO_ODR register *******************/\r
-#define GPIO_ODR_ODR0_Pos (0U) \r
-#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */\r
-#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */\r
-#define GPIO_ODR_ODR1_Pos (1U) \r
-#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */\r
-#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */\r
-#define GPIO_ODR_ODR2_Pos (2U) \r
-#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */\r
-#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */\r
-#define GPIO_ODR_ODR3_Pos (3U) \r
-#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */\r
-#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */\r
-#define GPIO_ODR_ODR4_Pos (4U) \r
-#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */\r
-#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */\r
-#define GPIO_ODR_ODR5_Pos (5U) \r
-#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */\r
-#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */\r
-#define GPIO_ODR_ODR6_Pos (6U) \r
-#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */\r
-#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */\r
-#define GPIO_ODR_ODR7_Pos (7U) \r
-#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */\r
-#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */\r
-#define GPIO_ODR_ODR8_Pos (8U) \r
-#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */\r
-#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */\r
-#define GPIO_ODR_ODR9_Pos (9U) \r
-#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */\r
-#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */\r
-#define GPIO_ODR_ODR10_Pos (10U) \r
-#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */\r
-#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */\r
-#define GPIO_ODR_ODR11_Pos (11U) \r
-#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */\r
-#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */\r
-#define GPIO_ODR_ODR12_Pos (12U) \r
-#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */\r
-#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */\r
-#define GPIO_ODR_ODR13_Pos (13U) \r
-#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */\r
-#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */\r
-#define GPIO_ODR_ODR14_Pos (14U) \r
-#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */\r
-#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */\r
-#define GPIO_ODR_ODR15_Pos (15U) \r
-#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */\r
-#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */\r
-\r
-/****************** Bit definition for GPIO_BSRR register *******************/\r
-#define GPIO_BSRR_BS0_Pos (0U) \r
-#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */\r
-#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */\r
-#define GPIO_BSRR_BS1_Pos (1U) \r
-#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */\r
-#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */\r
-#define GPIO_BSRR_BS2_Pos (2U) \r
-#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */\r
-#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */\r
-#define GPIO_BSRR_BS3_Pos (3U) \r
-#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */\r
-#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */\r
-#define GPIO_BSRR_BS4_Pos (4U) \r
-#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */\r
-#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */\r
-#define GPIO_BSRR_BS5_Pos (5U) \r
-#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */\r
-#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */\r
-#define GPIO_BSRR_BS6_Pos (6U) \r
-#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */\r
-#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */\r
-#define GPIO_BSRR_BS7_Pos (7U) \r
-#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */\r
-#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */\r
-#define GPIO_BSRR_BS8_Pos (8U) \r
-#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */\r
-#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */\r
-#define GPIO_BSRR_BS9_Pos (9U) \r
-#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */\r
-#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */\r
-#define GPIO_BSRR_BS10_Pos (10U) \r
-#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */\r
-#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */\r
-#define GPIO_BSRR_BS11_Pos (11U) \r
-#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */\r
-#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */\r
-#define GPIO_BSRR_BS12_Pos (12U) \r
-#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */\r
-#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */\r
-#define GPIO_BSRR_BS13_Pos (13U) \r
-#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */\r
-#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */\r
-#define GPIO_BSRR_BS14_Pos (14U) \r
-#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */\r
-#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */\r
-#define GPIO_BSRR_BS15_Pos (15U) \r
-#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */\r
-#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */\r
-\r
-#define GPIO_BSRR_BR0_Pos (16U) \r
-#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */\r
-#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */\r
-#define GPIO_BSRR_BR1_Pos (17U) \r
-#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */\r
-#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */\r
-#define GPIO_BSRR_BR2_Pos (18U) \r
-#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */\r
-#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */\r
-#define GPIO_BSRR_BR3_Pos (19U) \r
-#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */\r
-#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */\r
-#define GPIO_BSRR_BR4_Pos (20U) \r
-#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */\r
-#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */\r
-#define GPIO_BSRR_BR5_Pos (21U) \r
-#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */\r
-#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */\r
-#define GPIO_BSRR_BR6_Pos (22U) \r
-#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */\r
-#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */\r
-#define GPIO_BSRR_BR7_Pos (23U) \r
-#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */\r
-#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */\r
-#define GPIO_BSRR_BR8_Pos (24U) \r
-#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */\r
-#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */\r
-#define GPIO_BSRR_BR9_Pos (25U) \r
-#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */\r
-#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */\r
-#define GPIO_BSRR_BR10_Pos (26U) \r
-#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */\r
-#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */\r
-#define GPIO_BSRR_BR11_Pos (27U) \r
-#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */\r
-#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */\r
-#define GPIO_BSRR_BR12_Pos (28U) \r
-#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */\r
-#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */\r
-#define GPIO_BSRR_BR13_Pos (29U) \r
-#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */\r
-#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */\r
-#define GPIO_BSRR_BR14_Pos (30U) \r
-#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */\r
-#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */\r
-#define GPIO_BSRR_BR15_Pos (31U) \r
-#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */\r
-#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */\r
-\r
-/******************* Bit definition for GPIO_BRR register *******************/\r
-#define GPIO_BRR_BR0_Pos (0U) \r
-#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */\r
-#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */\r
-#define GPIO_BRR_BR1_Pos (1U) \r
-#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */\r
-#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */\r
-#define GPIO_BRR_BR2_Pos (2U) \r
-#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */\r
-#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */\r
-#define GPIO_BRR_BR3_Pos (3U) \r
-#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */\r
-#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */\r
-#define GPIO_BRR_BR4_Pos (4U) \r
-#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */\r
-#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */\r
-#define GPIO_BRR_BR5_Pos (5U) \r
-#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */\r
-#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */\r
-#define GPIO_BRR_BR6_Pos (6U) \r
-#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */\r
-#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */\r
-#define GPIO_BRR_BR7_Pos (7U) \r
-#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */\r
-#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */\r
-#define GPIO_BRR_BR8_Pos (8U) \r
-#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */\r
-#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */\r
-#define GPIO_BRR_BR9_Pos (9U) \r
-#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */\r
-#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */\r
-#define GPIO_BRR_BR10_Pos (10U) \r
-#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */\r
-#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */\r
-#define GPIO_BRR_BR11_Pos (11U) \r
-#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */\r
-#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */\r
-#define GPIO_BRR_BR12_Pos (12U) \r
-#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */\r
-#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */\r
-#define GPIO_BRR_BR13_Pos (13U) \r
-#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */\r
-#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */\r
-#define GPIO_BRR_BR14_Pos (14U) \r
-#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */\r
-#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */\r
-#define GPIO_BRR_BR15_Pos (15U) \r
-#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */\r
-#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */\r
-\r
-/****************** Bit definition for GPIO_LCKR register *******************/\r
-#define GPIO_LCKR_LCK0_Pos (0U) \r
-#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */\r
-#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */\r
-#define GPIO_LCKR_LCK1_Pos (1U) \r
-#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */\r
-#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */\r
-#define GPIO_LCKR_LCK2_Pos (2U) \r
-#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */\r
-#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */\r
-#define GPIO_LCKR_LCK3_Pos (3U) \r
-#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */\r
-#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */\r
-#define GPIO_LCKR_LCK4_Pos (4U) \r
-#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */\r
-#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */\r
-#define GPIO_LCKR_LCK5_Pos (5U) \r
-#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */\r
-#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */\r
-#define GPIO_LCKR_LCK6_Pos (6U) \r
-#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */\r
-#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */\r
-#define GPIO_LCKR_LCK7_Pos (7U) \r
-#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */\r
-#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */\r
-#define GPIO_LCKR_LCK8_Pos (8U) \r
-#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */\r
-#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */\r
-#define GPIO_LCKR_LCK9_Pos (9U) \r
-#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */\r
-#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */\r
-#define GPIO_LCKR_LCK10_Pos (10U) \r
-#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */\r
-#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */\r
-#define GPIO_LCKR_LCK11_Pos (11U) \r
-#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */\r
-#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */\r
-#define GPIO_LCKR_LCK12_Pos (12U) \r
-#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */\r
-#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */\r
-#define GPIO_LCKR_LCK13_Pos (13U) \r
-#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */\r
-#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */\r
-#define GPIO_LCKR_LCK14_Pos (14U) \r
-#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */\r
-#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */\r
-#define GPIO_LCKR_LCK15_Pos (15U) \r
-#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */\r
-#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */\r
-#define GPIO_LCKR_LCKK_Pos (16U) \r
-#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */\r
-#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/****************** Bit definition for AFIO_EVCR register *******************/\r
-#define AFIO_EVCR_PIN_Pos (0U) \r
-#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */\r
-#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */\r
-#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */\r
-#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */\r
-#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */\r
-#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */\r
-\r
-/*!< PIN configuration */\r
-#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */\r
-#define AFIO_EVCR_PIN_PX1_Pos (0U) \r
-#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */\r
-#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */\r
-#define AFIO_EVCR_PIN_PX2_Pos (1U) \r
-#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */\r
-#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */\r
-#define AFIO_EVCR_PIN_PX3_Pos (0U) \r
-#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */\r
-#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */\r
-#define AFIO_EVCR_PIN_PX4_Pos (2U) \r
-#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */\r
-#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */\r
-#define AFIO_EVCR_PIN_PX5_Pos (0U) \r
-#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */\r
-#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */\r
-#define AFIO_EVCR_PIN_PX6_Pos (1U) \r
-#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */\r
-#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */\r
-#define AFIO_EVCR_PIN_PX7_Pos (0U) \r
-#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */\r
-#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */\r
-#define AFIO_EVCR_PIN_PX8_Pos (3U) \r
-#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */\r
-#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */\r
-#define AFIO_EVCR_PIN_PX9_Pos (0U) \r
-#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */\r
-#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */\r
-#define AFIO_EVCR_PIN_PX10_Pos (1U) \r
-#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */\r
-#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */\r
-#define AFIO_EVCR_PIN_PX11_Pos (0U) \r
-#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */\r
-#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */\r
-#define AFIO_EVCR_PIN_PX12_Pos (2U) \r
-#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */\r
-#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */\r
-#define AFIO_EVCR_PIN_PX13_Pos (0U) \r
-#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */\r
-#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */\r
-#define AFIO_EVCR_PIN_PX14_Pos (1U) \r
-#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */\r
-#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */\r
-#define AFIO_EVCR_PIN_PX15_Pos (0U) \r
-#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */\r
-#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */\r
-\r
-#define AFIO_EVCR_PORT_Pos (4U) \r
-#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */\r
-#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */\r
-#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */\r
-#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */\r
-#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */\r
-\r
-/*!< PORT configuration */\r
-#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */\r
-#define AFIO_EVCR_PORT_PB_Pos (4U) \r
-#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */\r
-#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */\r
-#define AFIO_EVCR_PORT_PC_Pos (5U) \r
-#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */\r
-#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */\r
-#define AFIO_EVCR_PORT_PD_Pos (4U) \r
-#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */\r
-#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */\r
-#define AFIO_EVCR_PORT_PE_Pos (6U) \r
-#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */\r
-#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */\r
-\r
-#define AFIO_EVCR_EVOE_Pos (7U) \r
-#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */\r
-#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */\r
-\r
-/****************** Bit definition for AFIO_MAPR register *******************/\r
-#define AFIO_MAPR_SPI1_REMAP_Pos (0U) \r
-#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */\r
-#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */\r
-#define AFIO_MAPR_I2C1_REMAP_Pos (1U) \r
-#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */\r
-#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */\r
-#define AFIO_MAPR_USART1_REMAP_Pos (2U) \r
-#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */\r
-#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */\r
-#define AFIO_MAPR_USART2_REMAP_Pos (3U) \r
-#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */\r
-#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */\r
-\r
-#define AFIO_MAPR_USART3_REMAP_Pos (4U) \r
-#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */\r
-#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */\r
-#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */\r
-#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */\r
-\r
-/* USART3_REMAP configuration */\r
-#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */\r
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) \r
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */\r
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */\r
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) \r
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */\r
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */\r
-\r
-#define AFIO_MAPR_TIM1_REMAP_Pos (6U) \r
-#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */\r
-#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */\r
-#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */\r
-#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */\r
-\r
-/*!< TIM1_REMAP configuration */\r
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */\r
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) \r
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */\r
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */\r
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) \r
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */\r
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */\r
-\r
-#define AFIO_MAPR_TIM2_REMAP_Pos (8U) \r
-#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */\r
-#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */\r
-#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */\r
-#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */\r
-\r
-/*!< TIM2_REMAP configuration */\r
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */\r
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) \r
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */\r
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */\r
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) \r
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */\r
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */\r
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) \r
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */\r
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */\r
-\r
-#define AFIO_MAPR_TIM3_REMAP_Pos (10U) \r
-#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */\r
-#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */\r
-#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */\r
-#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */\r
-\r
-/*!< TIM3_REMAP configuration */\r
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */\r
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) \r
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */\r
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */\r
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) \r
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */\r
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */\r
-\r
-#define AFIO_MAPR_TIM4_REMAP_Pos (12U) \r
-#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */\r
-#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */\r
-\r
-#define AFIO_MAPR_CAN_REMAP_Pos (13U) \r
-#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */\r
-#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */\r
-#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */\r
-#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */\r
-\r
-/*!< CAN_REMAP configuration */\r
-#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */\r
-#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) \r
-#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */\r
-#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */\r
-#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) \r
-#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */\r
-#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */\r
-\r
-#define AFIO_MAPR_PD01_REMAP_Pos (15U) \r
-#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */\r
-#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */\r
-#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U) \r
-#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1U << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */\r
-#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */\r
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos (17U) \r
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk (0x1U << AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos) /*!< 0x00020000 */\r
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk /*!< ADC 1 External Trigger Injected Conversion remapping */\r
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos (18U) \r
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk (0x1U << AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos) /*!< 0x00040000 */\r
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk /*!< ADC 1 External Trigger Regular Conversion remapping */\r
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos (19U) \r
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk (0x1U << AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos) /*!< 0x00080000 */\r
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk /*!< ADC 2 External Trigger Injected Conversion remapping */\r
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos (20U) \r
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk (0x1U << AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos) /*!< 0x00100000 */\r
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk /*!< ADC 2 External Trigger Regular Conversion remapping */\r
-\r
-/*!< SWJ_CFG configuration */\r
-#define AFIO_MAPR_SWJ_CFG_Pos (24U) \r
-#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */\r
-#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */\r
-#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */\r
-#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */\r
-#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */\r
-\r
-#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */\r
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) \r
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */\r
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */\r
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) \r
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */\r
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */\r
-#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) \r
-#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */\r
-#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */\r
-\r
-\r
-/***************** Bit definition for AFIO_EXTICR1 register *****************/\r
-#define AFIO_EXTICR1_EXTI0_Pos (0U) \r
-#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\r
-#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */\r
-#define AFIO_EXTICR1_EXTI1_Pos (4U) \r
-#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\r
-#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */\r
-#define AFIO_EXTICR1_EXTI2_Pos (8U) \r
-#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\r
-#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */\r
-#define AFIO_EXTICR1_EXTI3_Pos (12U) \r
-#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\r
-#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */\r
-\r
-/*!< EXTI0 configuration */\r
-#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) \r
-#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */\r
-#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) \r
-#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */\r
-#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) \r
-#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */\r
-#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) \r
-#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */\r
-#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) \r
-#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */\r
-#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */\r
-#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) \r
-#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */\r
-#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */\r
-\r
-/*!< EXTI1 configuration */\r
-#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) \r
-#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */\r
-#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) \r
-#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */\r
-#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) \r
-#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */\r
-#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) \r
-#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */\r
-#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) \r
-#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */\r
-#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */\r
-#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) \r
-#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */\r
-#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */\r
-\r
-/*!< EXTI2 configuration */ \r
-#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) \r
-#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */\r
-#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) \r
-#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */\r
-#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) \r
-#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */\r
-#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) \r
-#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */\r
-#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) \r
-#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */\r
-#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */\r
-#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) \r
-#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */\r
-#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */\r
-\r
-/*!< EXTI3 configuration */\r
-#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) \r
-#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */\r
-#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) \r
-#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */\r
-#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) \r
-#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */\r
-#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) \r
-#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */\r
-#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) \r
-#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */\r
-#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */\r
-#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) \r
-#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */\r
-#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */\r
-\r
-/***************** Bit definition for AFIO_EXTICR2 register *****************/\r
-#define AFIO_EXTICR2_EXTI4_Pos (0U) \r
-#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\r
-#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */\r
-#define AFIO_EXTICR2_EXTI5_Pos (4U) \r
-#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\r
-#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */\r
-#define AFIO_EXTICR2_EXTI6_Pos (8U) \r
-#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\r
-#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */\r
-#define AFIO_EXTICR2_EXTI7_Pos (12U) \r
-#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\r
-#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */\r
-\r
-/*!< EXTI4 configuration */\r
-#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) \r
-#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */\r
-#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) \r
-#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */\r
-#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) \r
-#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */\r
-#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) \r
-#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */\r
-#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) \r
-#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */\r
-#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */\r
-#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) \r
-#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */\r
-#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */\r
-\r
-/* EXTI5 configuration */\r
-#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) \r
-#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */\r
-#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) \r
-#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */\r
-#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) \r
-#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */\r
-#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) \r
-#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */\r
-#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) \r
-#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */\r
-#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */\r
-#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) \r
-#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */\r
-#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */\r
-\r
-/*!< EXTI6 configuration */ \r
-#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) \r
-#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */\r
-#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) \r
-#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */\r
-#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) \r
-#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */\r
-#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) \r
-#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */\r
-#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) \r
-#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */\r
-#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */\r
-#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) \r
-#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */\r
-#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */\r
-\r
-/*!< EXTI7 configuration */\r
-#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) \r
-#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */\r
-#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) \r
-#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */\r
-#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) \r
-#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */\r
-#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) \r
-#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */\r
-#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) \r
-#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */\r
-#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */\r
-#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) \r
-#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */\r
-#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */\r
-\r
-/***************** Bit definition for AFIO_EXTICR3 register *****************/\r
-#define AFIO_EXTICR3_EXTI8_Pos (0U) \r
-#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\r
-#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */\r
-#define AFIO_EXTICR3_EXTI9_Pos (4U) \r
-#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\r
-#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */\r
-#define AFIO_EXTICR3_EXTI10_Pos (8U) \r
-#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\r
-#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */\r
-#define AFIO_EXTICR3_EXTI11_Pos (12U) \r
-#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\r
-#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */\r
-\r
-/*!< EXTI8 configuration */\r
-#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) \r
-#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */\r
-#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) \r
-#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */\r
-#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) \r
-#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */\r
-#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) \r
-#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */\r
-#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) \r
-#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */\r
-#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */\r
-#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) \r
-#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */\r
-#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */\r
-\r
-/*!< EXTI9 configuration */\r
-#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) \r
-#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */\r
-#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) \r
-#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */\r
-#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) \r
-#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */\r
-#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) \r
-#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */\r
-#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) \r
-#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */\r
-#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */\r
-#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) \r
-#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */\r
-#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */\r
-\r
-/*!< EXTI10 configuration */ \r
-#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) \r
-#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */\r
-#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) \r
-#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */\r
-#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) \r
-#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */\r
-#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) \r
-#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */\r
-#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) \r
-#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */\r
-#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */\r
-#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) \r
-#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */\r
-#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */\r
-\r
-/*!< EXTI11 configuration */\r
-#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) \r
-#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */\r
-#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) \r
-#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */\r
-#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) \r
-#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */\r
-#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) \r
-#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */\r
-#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) \r
-#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */\r
-#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */\r
-#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) \r
-#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */\r
-#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */\r
-\r
-/***************** Bit definition for AFIO_EXTICR4 register *****************/\r
-#define AFIO_EXTICR4_EXTI12_Pos (0U) \r
-#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\r
-#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */\r
-#define AFIO_EXTICR4_EXTI13_Pos (4U) \r
-#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\r
-#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */\r
-#define AFIO_EXTICR4_EXTI14_Pos (8U) \r
-#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\r
-#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */\r
-#define AFIO_EXTICR4_EXTI15_Pos (12U) \r
-#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\r
-#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */\r
-\r
-/* EXTI12 configuration */\r
-#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) \r
-#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */\r
-#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) \r
-#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */\r
-#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) \r
-#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */\r
-#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) \r
-#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */\r
-#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) \r
-#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */\r
-#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */\r
-#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) \r
-#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */\r
-#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */\r
-\r
-/* EXTI13 configuration */\r
-#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) \r
-#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */\r
-#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) \r
-#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */\r
-#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) \r
-#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */\r
-#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) \r
-#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */\r
-#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) \r
-#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */\r
-#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */\r
-#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) \r
-#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */\r
-#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */\r
-\r
-/*!< EXTI14 configuration */ \r
-#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) \r
-#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */\r
-#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) \r
-#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */\r
-#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) \r
-#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */\r
-#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) \r
-#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */\r
-#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) \r
-#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */\r
-#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */\r
-#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) \r
-#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */\r
-#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */\r
-\r
-/*!< EXTI15 configuration */\r
-#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) \r
-#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */\r
-#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) \r
-#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */\r
-#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) \r
-#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */\r
-#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) \r
-#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */\r
-#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) \r
-#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */\r
-#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */\r
-#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) \r
-#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */\r
-#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */\r
-\r
-/****************** Bit definition for AFIO_MAPR2 register ******************/\r
-\r
-\r
-#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U) \r
-#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1U << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */\r
-#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* External Interrupt/Event Controller */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for EXTI_IMR register *******************/\r
-#define EXTI_IMR_MR0_Pos (0U) \r
-#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */\r
-#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */\r
-#define EXTI_IMR_MR1_Pos (1U) \r
-#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */\r
-#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */\r
-#define EXTI_IMR_MR2_Pos (2U) \r
-#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */\r
-#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */\r
-#define EXTI_IMR_MR3_Pos (3U) \r
-#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */\r
-#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */\r
-#define EXTI_IMR_MR4_Pos (4U) \r
-#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */\r
-#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */\r
-#define EXTI_IMR_MR5_Pos (5U) \r
-#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */\r
-#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */\r
-#define EXTI_IMR_MR6_Pos (6U) \r
-#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */\r
-#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */\r
-#define EXTI_IMR_MR7_Pos (7U) \r
-#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */\r
-#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */\r
-#define EXTI_IMR_MR8_Pos (8U) \r
-#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */\r
-#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */\r
-#define EXTI_IMR_MR9_Pos (9U) \r
-#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */\r
-#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */\r
-#define EXTI_IMR_MR10_Pos (10U) \r
-#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */\r
-#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */\r
-#define EXTI_IMR_MR11_Pos (11U) \r
-#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */\r
-#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */\r
-#define EXTI_IMR_MR12_Pos (12U) \r
-#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */\r
-#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */\r
-#define EXTI_IMR_MR13_Pos (13U) \r
-#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */\r
-#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */\r
-#define EXTI_IMR_MR14_Pos (14U) \r
-#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */\r
-#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */\r
-#define EXTI_IMR_MR15_Pos (15U) \r
-#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */\r
-#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */\r
-#define EXTI_IMR_MR16_Pos (16U) \r
-#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */\r
-#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */\r
-#define EXTI_IMR_MR17_Pos (17U) \r
-#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */\r
-#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */\r
-#define EXTI_IMR_MR18_Pos (18U) \r
-#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */\r
-#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */\r
-\r
-/* References Defines */\r
-#define EXTI_IMR_IM0 EXTI_IMR_MR0\r
-#define EXTI_IMR_IM1 EXTI_IMR_MR1\r
-#define EXTI_IMR_IM2 EXTI_IMR_MR2\r
-#define EXTI_IMR_IM3 EXTI_IMR_MR3\r
-#define EXTI_IMR_IM4 EXTI_IMR_MR4\r
-#define EXTI_IMR_IM5 EXTI_IMR_MR5\r
-#define EXTI_IMR_IM6 EXTI_IMR_MR6\r
-#define EXTI_IMR_IM7 EXTI_IMR_MR7\r
-#define EXTI_IMR_IM8 EXTI_IMR_MR8\r
-#define EXTI_IMR_IM9 EXTI_IMR_MR9\r
-#define EXTI_IMR_IM10 EXTI_IMR_MR10\r
-#define EXTI_IMR_IM11 EXTI_IMR_MR11\r
-#define EXTI_IMR_IM12 EXTI_IMR_MR12\r
-#define EXTI_IMR_IM13 EXTI_IMR_MR13\r
-#define EXTI_IMR_IM14 EXTI_IMR_MR14\r
-#define EXTI_IMR_IM15 EXTI_IMR_MR15\r
-#define EXTI_IMR_IM16 EXTI_IMR_MR16\r
-#define EXTI_IMR_IM17 EXTI_IMR_MR17\r
-#define EXTI_IMR_IM18 EXTI_IMR_MR18\r
-#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */\r
- \r
-/******************* Bit definition for EXTI_EMR register *******************/\r
-#define EXTI_EMR_MR0_Pos (0U) \r
-#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */\r
-#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */\r
-#define EXTI_EMR_MR1_Pos (1U) \r
-#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */\r
-#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */\r
-#define EXTI_EMR_MR2_Pos (2U) \r
-#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */\r
-#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */\r
-#define EXTI_EMR_MR3_Pos (3U) \r
-#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */\r
-#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */\r
-#define EXTI_EMR_MR4_Pos (4U) \r
-#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */\r
-#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */\r
-#define EXTI_EMR_MR5_Pos (5U) \r
-#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */\r
-#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */\r
-#define EXTI_EMR_MR6_Pos (6U) \r
-#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */\r
-#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */\r
-#define EXTI_EMR_MR7_Pos (7U) \r
-#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */\r
-#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */\r
-#define EXTI_EMR_MR8_Pos (8U) \r
-#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */\r
-#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */\r
-#define EXTI_EMR_MR9_Pos (9U) \r
-#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */\r
-#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */\r
-#define EXTI_EMR_MR10_Pos (10U) \r
-#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */\r
-#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */\r
-#define EXTI_EMR_MR11_Pos (11U) \r
-#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */\r
-#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */\r
-#define EXTI_EMR_MR12_Pos (12U) \r
-#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */\r
-#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */\r
-#define EXTI_EMR_MR13_Pos (13U) \r
-#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */\r
-#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */\r
-#define EXTI_EMR_MR14_Pos (14U) \r
-#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */\r
-#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */\r
-#define EXTI_EMR_MR15_Pos (15U) \r
-#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */\r
-#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */\r
-#define EXTI_EMR_MR16_Pos (16U) \r
-#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */\r
-#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */\r
-#define EXTI_EMR_MR17_Pos (17U) \r
-#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */\r
-#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */\r
-#define EXTI_EMR_MR18_Pos (18U) \r
-#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */\r
-#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */\r
-\r
-/* References Defines */\r
-#define EXTI_EMR_EM0 EXTI_EMR_MR0\r
-#define EXTI_EMR_EM1 EXTI_EMR_MR1\r
-#define EXTI_EMR_EM2 EXTI_EMR_MR2\r
-#define EXTI_EMR_EM3 EXTI_EMR_MR3\r
-#define EXTI_EMR_EM4 EXTI_EMR_MR4\r
-#define EXTI_EMR_EM5 EXTI_EMR_MR5\r
-#define EXTI_EMR_EM6 EXTI_EMR_MR6\r
-#define EXTI_EMR_EM7 EXTI_EMR_MR7\r
-#define EXTI_EMR_EM8 EXTI_EMR_MR8\r
-#define EXTI_EMR_EM9 EXTI_EMR_MR9\r
-#define EXTI_EMR_EM10 EXTI_EMR_MR10\r
-#define EXTI_EMR_EM11 EXTI_EMR_MR11\r
-#define EXTI_EMR_EM12 EXTI_EMR_MR12\r
-#define EXTI_EMR_EM13 EXTI_EMR_MR13\r
-#define EXTI_EMR_EM14 EXTI_EMR_MR14\r
-#define EXTI_EMR_EM15 EXTI_EMR_MR15\r
-#define EXTI_EMR_EM16 EXTI_EMR_MR16\r
-#define EXTI_EMR_EM17 EXTI_EMR_MR17\r
-#define EXTI_EMR_EM18 EXTI_EMR_MR18\r
-\r
-/****************** Bit definition for EXTI_RTSR register *******************/\r
-#define EXTI_RTSR_TR0_Pos (0U) \r
-#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */\r
-#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */\r
-#define EXTI_RTSR_TR1_Pos (1U) \r
-#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */\r
-#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */\r
-#define EXTI_RTSR_TR2_Pos (2U) \r
-#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */\r
-#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */\r
-#define EXTI_RTSR_TR3_Pos (3U) \r
-#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */\r
-#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */\r
-#define EXTI_RTSR_TR4_Pos (4U) \r
-#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */\r
-#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */\r
-#define EXTI_RTSR_TR5_Pos (5U) \r
-#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */\r
-#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */\r
-#define EXTI_RTSR_TR6_Pos (6U) \r
-#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */\r
-#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */\r
-#define EXTI_RTSR_TR7_Pos (7U) \r
-#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */\r
-#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */\r
-#define EXTI_RTSR_TR8_Pos (8U) \r
-#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */\r
-#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */\r
-#define EXTI_RTSR_TR9_Pos (9U) \r
-#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */\r
-#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */\r
-#define EXTI_RTSR_TR10_Pos (10U) \r
-#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */\r
-#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */\r
-#define EXTI_RTSR_TR11_Pos (11U) \r
-#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */\r
-#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */\r
-#define EXTI_RTSR_TR12_Pos (12U) \r
-#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */\r
-#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */\r
-#define EXTI_RTSR_TR13_Pos (13U) \r
-#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */\r
-#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */\r
-#define EXTI_RTSR_TR14_Pos (14U) \r
-#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */\r
-#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */\r
-#define EXTI_RTSR_TR15_Pos (15U) \r
-#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */\r
-#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */\r
-#define EXTI_RTSR_TR16_Pos (16U) \r
-#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */\r
-#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */\r
-#define EXTI_RTSR_TR17_Pos (17U) \r
-#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */\r
-#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */\r
-#define EXTI_RTSR_TR18_Pos (18U) \r
-#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */\r
-#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */\r
-\r
-/* References Defines */\r
-#define EXTI_RTSR_RT0 EXTI_RTSR_TR0\r
-#define EXTI_RTSR_RT1 EXTI_RTSR_TR1\r
-#define EXTI_RTSR_RT2 EXTI_RTSR_TR2\r
-#define EXTI_RTSR_RT3 EXTI_RTSR_TR3\r
-#define EXTI_RTSR_RT4 EXTI_RTSR_TR4\r
-#define EXTI_RTSR_RT5 EXTI_RTSR_TR5\r
-#define EXTI_RTSR_RT6 EXTI_RTSR_TR6\r
-#define EXTI_RTSR_RT7 EXTI_RTSR_TR7\r
-#define EXTI_RTSR_RT8 EXTI_RTSR_TR8\r
-#define EXTI_RTSR_RT9 EXTI_RTSR_TR9\r
-#define EXTI_RTSR_RT10 EXTI_RTSR_TR10\r
-#define EXTI_RTSR_RT11 EXTI_RTSR_TR11\r
-#define EXTI_RTSR_RT12 EXTI_RTSR_TR12\r
-#define EXTI_RTSR_RT13 EXTI_RTSR_TR13\r
-#define EXTI_RTSR_RT14 EXTI_RTSR_TR14\r
-#define EXTI_RTSR_RT15 EXTI_RTSR_TR15\r
-#define EXTI_RTSR_RT16 EXTI_RTSR_TR16\r
-#define EXTI_RTSR_RT17 EXTI_RTSR_TR17\r
-#define EXTI_RTSR_RT18 EXTI_RTSR_TR18\r
-\r
-/****************** Bit definition for EXTI_FTSR register *******************/\r
-#define EXTI_FTSR_TR0_Pos (0U) \r
-#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */\r
-#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */\r
-#define EXTI_FTSR_TR1_Pos (1U) \r
-#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */\r
-#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */\r
-#define EXTI_FTSR_TR2_Pos (2U) \r
-#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */\r
-#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */\r
-#define EXTI_FTSR_TR3_Pos (3U) \r
-#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */\r
-#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */\r
-#define EXTI_FTSR_TR4_Pos (4U) \r
-#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */\r
-#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */\r
-#define EXTI_FTSR_TR5_Pos (5U) \r
-#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */\r
-#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */\r
-#define EXTI_FTSR_TR6_Pos (6U) \r
-#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */\r
-#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */\r
-#define EXTI_FTSR_TR7_Pos (7U) \r
-#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */\r
-#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */\r
-#define EXTI_FTSR_TR8_Pos (8U) \r
-#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */\r
-#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */\r
-#define EXTI_FTSR_TR9_Pos (9U) \r
-#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */\r
-#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */\r
-#define EXTI_FTSR_TR10_Pos (10U) \r
-#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */\r
-#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */\r
-#define EXTI_FTSR_TR11_Pos (11U) \r
-#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */\r
-#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */\r
-#define EXTI_FTSR_TR12_Pos (12U) \r
-#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */\r
-#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */\r
-#define EXTI_FTSR_TR13_Pos (13U) \r
-#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */\r
-#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */\r
-#define EXTI_FTSR_TR14_Pos (14U) \r
-#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */\r
-#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */\r
-#define EXTI_FTSR_TR15_Pos (15U) \r
-#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */\r
-#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */\r
-#define EXTI_FTSR_TR16_Pos (16U) \r
-#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */\r
-#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */\r
-#define EXTI_FTSR_TR17_Pos (17U) \r
-#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */\r
-#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */\r
-#define EXTI_FTSR_TR18_Pos (18U) \r
-#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */\r
-#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */\r
-\r
-/* References Defines */\r
-#define EXTI_FTSR_FT0 EXTI_FTSR_TR0\r
-#define EXTI_FTSR_FT1 EXTI_FTSR_TR1\r
-#define EXTI_FTSR_FT2 EXTI_FTSR_TR2\r
-#define EXTI_FTSR_FT3 EXTI_FTSR_TR3\r
-#define EXTI_FTSR_FT4 EXTI_FTSR_TR4\r
-#define EXTI_FTSR_FT5 EXTI_FTSR_TR5\r
-#define EXTI_FTSR_FT6 EXTI_FTSR_TR6\r
-#define EXTI_FTSR_FT7 EXTI_FTSR_TR7\r
-#define EXTI_FTSR_FT8 EXTI_FTSR_TR8\r
-#define EXTI_FTSR_FT9 EXTI_FTSR_TR9\r
-#define EXTI_FTSR_FT10 EXTI_FTSR_TR10\r
-#define EXTI_FTSR_FT11 EXTI_FTSR_TR11\r
-#define EXTI_FTSR_FT12 EXTI_FTSR_TR12\r
-#define EXTI_FTSR_FT13 EXTI_FTSR_TR13\r
-#define EXTI_FTSR_FT14 EXTI_FTSR_TR14\r
-#define EXTI_FTSR_FT15 EXTI_FTSR_TR15\r
-#define EXTI_FTSR_FT16 EXTI_FTSR_TR16\r
-#define EXTI_FTSR_FT17 EXTI_FTSR_TR17\r
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18\r
-\r
-/****************** Bit definition for EXTI_SWIER register ******************/\r
-#define EXTI_SWIER_SWIER0_Pos (0U) \r
-#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */\r
-#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */\r
-#define EXTI_SWIER_SWIER1_Pos (1U) \r
-#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */\r
-#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */\r
-#define EXTI_SWIER_SWIER2_Pos (2U) \r
-#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */\r
-#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */\r
-#define EXTI_SWIER_SWIER3_Pos (3U) \r
-#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */\r
-#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */\r
-#define EXTI_SWIER_SWIER4_Pos (4U) \r
-#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */\r
-#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */\r
-#define EXTI_SWIER_SWIER5_Pos (5U) \r
-#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */\r
-#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */\r
-#define EXTI_SWIER_SWIER6_Pos (6U) \r
-#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */\r
-#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */\r
-#define EXTI_SWIER_SWIER7_Pos (7U) \r
-#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */\r
-#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */\r
-#define EXTI_SWIER_SWIER8_Pos (8U) \r
-#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */\r
-#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */\r
-#define EXTI_SWIER_SWIER9_Pos (9U) \r
-#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */\r
-#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */\r
-#define EXTI_SWIER_SWIER10_Pos (10U) \r
-#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */\r
-#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */\r
-#define EXTI_SWIER_SWIER11_Pos (11U) \r
-#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */\r
-#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */\r
-#define EXTI_SWIER_SWIER12_Pos (12U) \r
-#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */\r
-#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */\r
-#define EXTI_SWIER_SWIER13_Pos (13U) \r
-#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */\r
-#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */\r
-#define EXTI_SWIER_SWIER14_Pos (14U) \r
-#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */\r
-#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */\r
-#define EXTI_SWIER_SWIER15_Pos (15U) \r
-#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */\r
-#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */\r
-#define EXTI_SWIER_SWIER16_Pos (16U) \r
-#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */\r
-#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */\r
-#define EXTI_SWIER_SWIER17_Pos (17U) \r
-#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */\r
-#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */\r
-#define EXTI_SWIER_SWIER18_Pos (18U) \r
-#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */\r
-#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */\r
-\r
-/* References Defines */\r
-#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0\r
-#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1\r
-#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2\r
-#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3\r
-#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4\r
-#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5\r
-#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6\r
-#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7\r
-#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8\r
-#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9\r
-#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10\r
-#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11\r
-#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12\r
-#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13\r
-#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14\r
-#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15\r
-#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16\r
-#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17\r
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18\r
-\r
-/******************* Bit definition for EXTI_PR register ********************/\r
-#define EXTI_PR_PR0_Pos (0U) \r
-#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */\r
-#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */\r
-#define EXTI_PR_PR1_Pos (1U) \r
-#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */\r
-#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */\r
-#define EXTI_PR_PR2_Pos (2U) \r
-#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */\r
-#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */\r
-#define EXTI_PR_PR3_Pos (3U) \r
-#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */\r
-#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */\r
-#define EXTI_PR_PR4_Pos (4U) \r
-#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */\r
-#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */\r
-#define EXTI_PR_PR5_Pos (5U) \r
-#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */\r
-#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */\r
-#define EXTI_PR_PR6_Pos (6U) \r
-#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */\r
-#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */\r
-#define EXTI_PR_PR7_Pos (7U) \r
-#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */\r
-#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */\r
-#define EXTI_PR_PR8_Pos (8U) \r
-#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */\r
-#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */\r
-#define EXTI_PR_PR9_Pos (9U) \r
-#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */\r
-#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */\r
-#define EXTI_PR_PR10_Pos (10U) \r
-#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */\r
-#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */\r
-#define EXTI_PR_PR11_Pos (11U) \r
-#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */\r
-#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */\r
-#define EXTI_PR_PR12_Pos (12U) \r
-#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */\r
-#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */\r
-#define EXTI_PR_PR13_Pos (13U) \r
-#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */\r
-#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */\r
-#define EXTI_PR_PR14_Pos (14U) \r
-#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */\r
-#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */\r
-#define EXTI_PR_PR15_Pos (15U) \r
-#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */\r
-#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */\r
-#define EXTI_PR_PR16_Pos (16U) \r
-#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */\r
-#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */\r
-#define EXTI_PR_PR17_Pos (17U) \r
-#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */\r
-#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */\r
-#define EXTI_PR_PR18_Pos (18U) \r
-#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */\r
-#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */\r
-\r
-/* References Defines */\r
-#define EXTI_PR_PIF0 EXTI_PR_PR0\r
-#define EXTI_PR_PIF1 EXTI_PR_PR1\r
-#define EXTI_PR_PIF2 EXTI_PR_PR2\r
-#define EXTI_PR_PIF3 EXTI_PR_PR3\r
-#define EXTI_PR_PIF4 EXTI_PR_PR4\r
-#define EXTI_PR_PIF5 EXTI_PR_PR5\r
-#define EXTI_PR_PIF6 EXTI_PR_PR6\r
-#define EXTI_PR_PIF7 EXTI_PR_PR7\r
-#define EXTI_PR_PIF8 EXTI_PR_PR8\r
-#define EXTI_PR_PIF9 EXTI_PR_PR9\r
-#define EXTI_PR_PIF10 EXTI_PR_PR10\r
-#define EXTI_PR_PIF11 EXTI_PR_PR11\r
-#define EXTI_PR_PIF12 EXTI_PR_PR12\r
-#define EXTI_PR_PIF13 EXTI_PR_PR13\r
-#define EXTI_PR_PIF14 EXTI_PR_PR14\r
-#define EXTI_PR_PIF15 EXTI_PR_PR15\r
-#define EXTI_PR_PIF16 EXTI_PR_PR16\r
-#define EXTI_PR_PIF17 EXTI_PR_PR17\r
-#define EXTI_PR_PIF18 EXTI_PR_PR18\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* DMA Controller */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for DMA_ISR register ********************/\r
-#define DMA_ISR_GIF1_Pos (0U) \r
-#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */\r
-#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */\r
-#define DMA_ISR_TCIF1_Pos (1U) \r
-#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */\r
-#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */\r
-#define DMA_ISR_HTIF1_Pos (2U) \r
-#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */\r
-#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */\r
-#define DMA_ISR_TEIF1_Pos (3U) \r
-#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */\r
-#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */\r
-#define DMA_ISR_GIF2_Pos (4U) \r
-#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */\r
-#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */\r
-#define DMA_ISR_TCIF2_Pos (5U) \r
-#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */\r
-#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */\r
-#define DMA_ISR_HTIF2_Pos (6U) \r
-#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */\r
-#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */\r
-#define DMA_ISR_TEIF2_Pos (7U) \r
-#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */\r
-#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */\r
-#define DMA_ISR_GIF3_Pos (8U) \r
-#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */\r
-#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */\r
-#define DMA_ISR_TCIF3_Pos (9U) \r
-#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */\r
-#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */\r
-#define DMA_ISR_HTIF3_Pos (10U) \r
-#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */\r
-#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */\r
-#define DMA_ISR_TEIF3_Pos (11U) \r
-#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */\r
-#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */\r
-#define DMA_ISR_GIF4_Pos (12U) \r
-#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */\r
-#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */\r
-#define DMA_ISR_TCIF4_Pos (13U) \r
-#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */\r
-#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */\r
-#define DMA_ISR_HTIF4_Pos (14U) \r
-#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */\r
-#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */\r
-#define DMA_ISR_TEIF4_Pos (15U) \r
-#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */\r
-#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */\r
-#define DMA_ISR_GIF5_Pos (16U) \r
-#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */\r
-#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */\r
-#define DMA_ISR_TCIF5_Pos (17U) \r
-#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */\r
-#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */\r
-#define DMA_ISR_HTIF5_Pos (18U) \r
-#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */\r
-#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */\r
-#define DMA_ISR_TEIF5_Pos (19U) \r
-#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */\r
-#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */\r
-#define DMA_ISR_GIF6_Pos (20U) \r
-#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */\r
-#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */\r
-#define DMA_ISR_TCIF6_Pos (21U) \r
-#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */\r
-#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */\r
-#define DMA_ISR_HTIF6_Pos (22U) \r
-#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */\r
-#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */\r
-#define DMA_ISR_TEIF6_Pos (23U) \r
-#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */\r
-#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */\r
-#define DMA_ISR_GIF7_Pos (24U) \r
-#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */\r
-#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */\r
-#define DMA_ISR_TCIF7_Pos (25U) \r
-#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */\r
-#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */\r
-#define DMA_ISR_HTIF7_Pos (26U) \r
-#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */\r
-#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */\r
-#define DMA_ISR_TEIF7_Pos (27U) \r
-#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */\r
-#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */\r
-\r
-/******************* Bit definition for DMA_IFCR register *******************/\r
-#define DMA_IFCR_CGIF1_Pos (0U) \r
-#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */\r
-#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF1_Pos (1U) \r
-#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */\r
-#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF1_Pos (2U) \r
-#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */\r
-#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF1_Pos (3U) \r
-#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */\r
-#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */\r
-#define DMA_IFCR_CGIF2_Pos (4U) \r
-#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */\r
-#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF2_Pos (5U) \r
-#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */\r
-#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF2_Pos (6U) \r
-#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */\r
-#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF2_Pos (7U) \r
-#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */\r
-#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */\r
-#define DMA_IFCR_CGIF3_Pos (8U) \r
-#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */\r
-#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF3_Pos (9U) \r
-#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */\r
-#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF3_Pos (10U) \r
-#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */\r
-#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF3_Pos (11U) \r
-#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */\r
-#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */\r
-#define DMA_IFCR_CGIF4_Pos (12U) \r
-#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */\r
-#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF4_Pos (13U) \r
-#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */\r
-#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF4_Pos (14U) \r
-#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */\r
-#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF4_Pos (15U) \r
-#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */\r
-#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */\r
-#define DMA_IFCR_CGIF5_Pos (16U) \r
-#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */\r
-#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF5_Pos (17U) \r
-#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */\r
-#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF5_Pos (18U) \r
-#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */\r
-#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF5_Pos (19U) \r
-#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */\r
-#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */\r
-#define DMA_IFCR_CGIF6_Pos (20U) \r
-#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */\r
-#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF6_Pos (21U) \r
-#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */\r
-#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF6_Pos (22U) \r
-#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */\r
-#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF6_Pos (23U) \r
-#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */\r
-#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */\r
-#define DMA_IFCR_CGIF7_Pos (24U) \r
-#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */\r
-#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */\r
-#define DMA_IFCR_CTCIF7_Pos (25U) \r
-#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */\r
-#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */\r
-#define DMA_IFCR_CHTIF7_Pos (26U) \r
-#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */\r
-#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */\r
-#define DMA_IFCR_CTEIF7_Pos (27U) \r
-#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */\r
-#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */\r
-\r
-/******************* Bit definition for DMA_CCR register *******************/\r
-#define DMA_CCR_EN_Pos (0U) \r
-#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */\r
-#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */\r
-#define DMA_CCR_TCIE_Pos (1U) \r
-#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */\r
-#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */\r
-#define DMA_CCR_HTIE_Pos (2U) \r
-#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */\r
-#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */\r
-#define DMA_CCR_TEIE_Pos (3U) \r
-#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */\r
-#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */\r
-#define DMA_CCR_DIR_Pos (4U) \r
-#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */\r
-#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */\r
-#define DMA_CCR_CIRC_Pos (5U) \r
-#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */\r
-#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */\r
-#define DMA_CCR_PINC_Pos (6U) \r
-#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */\r
-#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */\r
-#define DMA_CCR_MINC_Pos (7U) \r
-#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */\r
-#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */\r
-\r
-#define DMA_CCR_PSIZE_Pos (8U) \r
-#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */\r
-#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */\r
-#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */\r
-#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */\r
-\r
-#define DMA_CCR_MSIZE_Pos (10U) \r
-#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */\r
-#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */\r
-#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */\r
-#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */\r
-\r
-#define DMA_CCR_PL_Pos (12U) \r
-#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */\r
-#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */\r
-#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */\r
-#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */\r
-\r
-#define DMA_CCR_MEM2MEM_Pos (14U) \r
-#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */\r
-#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */\r
-\r
-/****************** Bit definition for DMA_CNDTR register ******************/\r
-#define DMA_CNDTR_NDT_Pos (0U) \r
-#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */\r
-#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */\r
-\r
-/****************** Bit definition for DMA_CPAR register *******************/\r
-#define DMA_CPAR_PA_Pos (0U) \r
-#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */\r
-#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */\r
-\r
-/****************** Bit definition for DMA_CMAR register *******************/\r
-#define DMA_CMAR_MA_Pos (0U) \r
-#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
-#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Analog to Digital Converter (ADC) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/*\r
- * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)\r
- */\r
-#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */\r
-\r
-/******************** Bit definition for ADC_SR register ********************/\r
-#define ADC_SR_AWD_Pos (0U) \r
-#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */\r
-#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */\r
-#define ADC_SR_EOS_Pos (1U) \r
-#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */\r
-#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */\r
-#define ADC_SR_JEOS_Pos (2U) \r
-#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */\r
-#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */\r
-#define ADC_SR_JSTRT_Pos (3U) \r
-#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */\r
-#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */\r
-#define ADC_SR_STRT_Pos (4U) \r
-#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */\r
-#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */\r
-\r
-/* Legacy defines */\r
-#define ADC_SR_EOC (ADC_SR_EOS)\r
-#define ADC_SR_JEOC (ADC_SR_JEOS)\r
-\r
-/******************* Bit definition for ADC_CR1 register ********************/\r
-#define ADC_CR1_AWDCH_Pos (0U) \r
-#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */\r
-#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */\r
-#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */\r
-#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */\r
-#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */\r
-#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */\r
-#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */\r
-\r
-#define ADC_CR1_EOSIE_Pos (5U) \r
-#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */\r
-#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */\r
-#define ADC_CR1_AWDIE_Pos (6U) \r
-#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */\r
-#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */\r
-#define ADC_CR1_JEOSIE_Pos (7U) \r
-#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */\r
-#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */\r
-#define ADC_CR1_SCAN_Pos (8U) \r
-#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */\r
-#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */\r
-#define ADC_CR1_AWDSGL_Pos (9U) \r
-#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */\r
-#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\r
-#define ADC_CR1_JAUTO_Pos (10U) \r
-#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */\r
-#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */\r
-#define ADC_CR1_DISCEN_Pos (11U) \r
-#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */\r
-#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */\r
-#define ADC_CR1_JDISCEN_Pos (12U) \r
-#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */\r
-#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */\r
-\r
-#define ADC_CR1_DISCNUM_Pos (13U) \r
-#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */\r
-#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */\r
-#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */\r
-#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */\r
-#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */\r
-\r
-#define ADC_CR1_DUALMOD_Pos (16U) \r
-#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */\r
-#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */\r
-#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */\r
-#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */\r
-#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */\r
-#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */\r
-\r
-#define ADC_CR1_JAWDEN_Pos (22U) \r
-#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */\r
-#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */\r
-#define ADC_CR1_AWDEN_Pos (23U) \r
-#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */\r
-#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */\r
-\r
-/* Legacy defines */\r
-#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)\r
-#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)\r
-\r
-/******************* Bit definition for ADC_CR2 register ********************/\r
-#define ADC_CR2_ADON_Pos (0U) \r
-#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */\r
-#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */\r
-#define ADC_CR2_CONT_Pos (1U) \r
-#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */\r
-#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */\r
-#define ADC_CR2_CAL_Pos (2U) \r
-#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */\r
-#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */\r
-#define ADC_CR2_RSTCAL_Pos (3U) \r
-#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */\r
-#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */\r
-#define ADC_CR2_DMA_Pos (8U) \r
-#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */\r
-#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */\r
-#define ADC_CR2_ALIGN_Pos (11U) \r
-#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */\r
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */\r
-\r
-#define ADC_CR2_JEXTSEL_Pos (12U) \r
-#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */\r
-#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */\r
-#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */\r
-#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */\r
-#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */\r
-\r
-#define ADC_CR2_JEXTTRIG_Pos (15U) \r
-#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */\r
-#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */\r
-\r
-#define ADC_CR2_EXTSEL_Pos (17U) \r
-#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */\r
-#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */\r
-#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */\r
-#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */\r
-#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */\r
-\r
-#define ADC_CR2_EXTTRIG_Pos (20U) \r
-#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */\r
-#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */\r
-#define ADC_CR2_JSWSTART_Pos (21U) \r
-#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */\r
-#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */\r
-#define ADC_CR2_SWSTART_Pos (22U) \r
-#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */\r
-#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */\r
-#define ADC_CR2_TSVREFE_Pos (23U) \r
-#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */\r
-#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */\r
-\r
-/****************** Bit definition for ADC_SMPR1 register *******************/\r
-#define ADC_SMPR1_SMP10_Pos (0U) \r
-#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */\r
-#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */\r
-#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */\r
-#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */\r
-#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */\r
-\r
-#define ADC_SMPR1_SMP11_Pos (3U) \r
-#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */\r
-#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */\r
-#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */\r
-#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */\r
-#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */\r
-\r
-#define ADC_SMPR1_SMP12_Pos (6U) \r
-#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */\r
-#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */\r
-#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */\r
-#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */\r
-#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */\r
-\r
-#define ADC_SMPR1_SMP13_Pos (9U) \r
-#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */\r
-#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */\r
-#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */\r
-#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */\r
-#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */\r
-\r
-#define ADC_SMPR1_SMP14_Pos (12U) \r
-#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */\r
-#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */\r
-#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */\r
-#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */\r
-#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */\r
-\r
-#define ADC_SMPR1_SMP15_Pos (15U) \r
-#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */\r
-#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */\r
-#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */\r
-#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */\r
-#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */\r
-\r
-#define ADC_SMPR1_SMP16_Pos (18U) \r
-#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */\r
-#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */\r
-#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */\r
-#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */\r
-#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */\r
-\r
-#define ADC_SMPR1_SMP17_Pos (21U) \r
-#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */\r
-#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */\r
-#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */\r
-#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */\r
-#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */\r
-\r
-/****************** Bit definition for ADC_SMPR2 register *******************/\r
-#define ADC_SMPR2_SMP0_Pos (0U) \r
-#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */\r
-#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */\r
-#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */\r
-#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */\r
-#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */\r
-\r
-#define ADC_SMPR2_SMP1_Pos (3U) \r
-#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */\r
-#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */\r
-#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */\r
-#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */\r
-#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */\r
-\r
-#define ADC_SMPR2_SMP2_Pos (6U) \r
-#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */\r
-#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */\r
-#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */\r
-#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */\r
-#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */\r
-\r
-#define ADC_SMPR2_SMP3_Pos (9U) \r
-#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */\r
-#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */\r
-#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */\r
-#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */\r
-#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */\r
-\r
-#define ADC_SMPR2_SMP4_Pos (12U) \r
-#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */\r
-#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */\r
-#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */\r
-#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */\r
-#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */\r
-\r
-#define ADC_SMPR2_SMP5_Pos (15U) \r
-#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */\r
-#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */\r
-#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */\r
-#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */\r
-#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */\r
-\r
-#define ADC_SMPR2_SMP6_Pos (18U) \r
-#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */\r
-#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */\r
-#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */\r
-#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */\r
-#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */\r
-\r
-#define ADC_SMPR2_SMP7_Pos (21U) \r
-#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */\r
-#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */\r
-#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */\r
-#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */\r
-#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */\r
-\r
-#define ADC_SMPR2_SMP8_Pos (24U) \r
-#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */\r
-#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */\r
-#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */\r
-#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */\r
-#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */\r
-\r
-#define ADC_SMPR2_SMP9_Pos (27U) \r
-#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */\r
-#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */\r
-#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */\r
-#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */\r
-#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */\r
-\r
-/****************** Bit definition for ADC_JOFR1 register *******************/\r
-#define ADC_JOFR1_JOFFSET1_Pos (0U) \r
-#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */\r
-#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */\r
-\r
-/****************** Bit definition for ADC_JOFR2 register *******************/\r
-#define ADC_JOFR2_JOFFSET2_Pos (0U) \r
-#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */\r
-#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */\r
-\r
-/****************** Bit definition for ADC_JOFR3 register *******************/\r
-#define ADC_JOFR3_JOFFSET3_Pos (0U) \r
-#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */\r
-#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */\r
-\r
-/****************** Bit definition for ADC_JOFR4 register *******************/\r
-#define ADC_JOFR4_JOFFSET4_Pos (0U) \r
-#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */\r
-#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */\r
-\r
-/******************* Bit definition for ADC_HTR register ********************/\r
-#define ADC_HTR_HT_Pos (0U) \r
-#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */\r
-#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */\r
-\r
-/******************* Bit definition for ADC_LTR register ********************/\r
-#define ADC_LTR_LT_Pos (0U) \r
-#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */\r
-#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */\r
-\r
-/******************* Bit definition for ADC_SQR1 register *******************/\r
-#define ADC_SQR1_SQ13_Pos (0U) \r
-#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */\r
-#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */\r
-#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */\r
-#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */\r
-#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */\r
-#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */\r
-#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */\r
-\r
-#define ADC_SQR1_SQ14_Pos (5U) \r
-#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */\r
-#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */\r
-#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */\r
-#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */\r
-#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */\r
-#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */\r
-#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */\r
-\r
-#define ADC_SQR1_SQ15_Pos (10U) \r
-#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */\r
-#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */\r
-#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */\r
-#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */\r
-#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */\r
-#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */\r
-#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */\r
-\r
-#define ADC_SQR1_SQ16_Pos (15U) \r
-#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */\r
-#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */\r
-#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */\r
-#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */\r
-#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */\r
-#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */\r
-#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */\r
-\r
-#define ADC_SQR1_L_Pos (20U) \r
-#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */\r
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */\r
-#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */\r
-#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */\r
-#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */\r
-#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */\r
-\r
-/******************* Bit definition for ADC_SQR2 register *******************/\r
-#define ADC_SQR2_SQ7_Pos (0U) \r
-#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */\r
-#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */\r
-#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */\r
-#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */\r
-#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */\r
-#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */\r
-#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */\r
-\r
-#define ADC_SQR2_SQ8_Pos (5U) \r
-#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */\r
-#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */\r
-#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */\r
-#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */\r
-#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */\r
-#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */\r
-#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */\r
-\r
-#define ADC_SQR2_SQ9_Pos (10U) \r
-#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */\r
-#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */\r
-#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */\r
-#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */\r
-#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */\r
-#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */\r
-#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */\r
-\r
-#define ADC_SQR2_SQ10_Pos (15U) \r
-#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */\r
-#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */\r
-#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */\r
-#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */\r
-#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */\r
-#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */\r
-#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */\r
-\r
-#define ADC_SQR2_SQ11_Pos (20U) \r
-#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */\r
-#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */\r
-#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */\r
-#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */\r
-#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */\r
-#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */\r
-#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */\r
-\r
-#define ADC_SQR2_SQ12_Pos (25U) \r
-#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */\r
-#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */\r
-#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */\r
-#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */\r
-#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */\r
-#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */\r
-#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */\r
-\r
-/******************* Bit definition for ADC_SQR3 register *******************/\r
-#define ADC_SQR3_SQ1_Pos (0U) \r
-#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */\r
-#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */\r
-#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */\r
-#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */\r
-#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */\r
-#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */\r
-#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */\r
-\r
-#define ADC_SQR3_SQ2_Pos (5U) \r
-#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */\r
-#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */\r
-#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */\r
-#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */\r
-#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */\r
-#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */\r
-#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */\r
-\r
-#define ADC_SQR3_SQ3_Pos (10U) \r
-#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */\r
-#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */\r
-#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */\r
-#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */\r
-#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */\r
-#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */\r
-#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */\r
-\r
-#define ADC_SQR3_SQ4_Pos (15U) \r
-#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */\r
-#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */\r
-#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */\r
-#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */\r
-#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */\r
-#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */\r
-#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */\r
-\r
-#define ADC_SQR3_SQ5_Pos (20U) \r
-#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */\r
-#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */\r
-#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */\r
-#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */\r
-#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */\r
-#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */\r
-#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */\r
-\r
-#define ADC_SQR3_SQ6_Pos (25U) \r
-#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */\r
-#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */\r
-#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */\r
-#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */\r
-#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */\r
-#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */\r
-#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */\r
-\r
-/******************* Bit definition for ADC_JSQR register *******************/\r
-#define ADC_JSQR_JSQ1_Pos (0U) \r
-#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */\r
-#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */\r
-#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */\r
-#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */\r
-#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */\r
-#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */\r
-#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */\r
-\r
-#define ADC_JSQR_JSQ2_Pos (5U) \r
-#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */\r
-#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */\r
-#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */\r
-#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */\r
-#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */\r
-#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */\r
-#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */\r
-\r
-#define ADC_JSQR_JSQ3_Pos (10U) \r
-#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */\r
-#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */\r
-#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */\r
-#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */\r
-#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */\r
-#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */\r
-#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */\r
-\r
-#define ADC_JSQR_JSQ4_Pos (15U) \r
-#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */\r
-#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */\r
-#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */\r
-#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */\r
-#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */\r
-#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */\r
-#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */\r
-\r
-#define ADC_JSQR_JL_Pos (20U) \r
-#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */\r
-#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */\r
-#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */\r
-#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */\r
-\r
-/******************* Bit definition for ADC_JDR1 register *******************/\r
-#define ADC_JDR1_JDATA_Pos (0U) \r
-#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */\r
-#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */\r
-\r
-/******************* Bit definition for ADC_JDR2 register *******************/\r
-#define ADC_JDR2_JDATA_Pos (0U) \r
-#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */\r
-#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */\r
-\r
-/******************* Bit definition for ADC_JDR3 register *******************/\r
-#define ADC_JDR3_JDATA_Pos (0U) \r
-#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */\r
-#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */\r
-\r
-/******************* Bit definition for ADC_JDR4 register *******************/\r
-#define ADC_JDR4_JDATA_Pos (0U) \r
-#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */\r
-#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */\r
-\r
-/******************** Bit definition for ADC_DR register ********************/\r
-#define ADC_DR_DATA_Pos (0U) \r
-#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */\r
-#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */\r
-#define ADC_DR_ADC2DATA_Pos (16U) \r
-#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */\r
-#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */\r
-/******************************************************************************/\r
-/* */\r
-/* Digital to Analog Converter */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for DAC_CR register ********************/\r
-#define DAC_CR_EN1_Pos (0U) \r
-#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */\r
-#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */\r
-#define DAC_CR_BOFF1_Pos (1U) \r
-#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */\r
-#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */\r
-#define DAC_CR_TEN1_Pos (2U) \r
-#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */\r
-#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */\r
-\r
-#define DAC_CR_TSEL1_Pos (3U) \r
-#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */\r
-#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */\r
-#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */\r
-#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */\r
-#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */\r
-\r
-#define DAC_CR_WAVE1_Pos (6U) \r
-#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */\r
-#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */\r
-#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */\r
-\r
-#define DAC_CR_MAMP1_Pos (8U) \r
-#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */\r
-#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */\r
-#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */\r
-#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */\r
-#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */\r
-\r
-#define DAC_CR_DMAEN1_Pos (12U) \r
-#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */\r
-#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */\r
-#define DAC_CR_EN2_Pos (16U) \r
-#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */\r
-#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */\r
-#define DAC_CR_BOFF2_Pos (17U) \r
-#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */\r
-#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */\r
-#define DAC_CR_TEN2_Pos (18U) \r
-#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */\r
-#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */\r
-\r
-#define DAC_CR_TSEL2_Pos (19U) \r
-#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */\r
-#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */\r
-#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */\r
-#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */\r
-#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */\r
-\r
-#define DAC_CR_WAVE2_Pos (22U) \r
-#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */\r
-#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */\r
-#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */\r
-\r
-#define DAC_CR_MAMP2_Pos (24U) \r
-#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */\r
-#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */\r
-#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */\r
-#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */\r
-#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */\r
-\r
-#define DAC_CR_DMAEN2_Pos (28U) \r
-#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */\r
-#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */\r
-\r
-\r
-/***************** Bit definition for DAC_SWTRIGR register ******************/\r
-#define DAC_SWTRIGR_SWTRIG1_Pos (0U) \r
-#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\r
-#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */\r
-#define DAC_SWTRIGR_SWTRIG2_Pos (1U) \r
-#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */\r
-#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */\r
-\r
-/***************** Bit definition for DAC_DHR12R1 register ******************/\r
-#define DAC_DHR12R1_DACC1DHR_Pos (0U) \r
-#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */\r
-#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12L1 register ******************/\r
-#define DAC_DHR12L1_DACC1DHR_Pos (4U) \r
-#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
-#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8R1 register ******************/\r
-#define DAC_DHR8R1_DACC1DHR_Pos (0U) \r
-#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */\r
-#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12R2 register ******************/\r
-#define DAC_DHR12R2_DACC2DHR_Pos (0U) \r
-#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */\r
-#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12L2 register ******************/\r
-#define DAC_DHR12L2_DACC2DHR_Pos (4U) \r
-#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */\r
-#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8R2 register ******************/\r
-#define DAC_DHR8R2_DACC2DHR_Pos (0U) \r
-#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */\r
-#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12RD register ******************/\r
-#define DAC_DHR12RD_DACC1DHR_Pos (0U) \r
-#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */\r
-#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */\r
-#define DAC_DHR12RD_DACC2DHR_Pos (16U) \r
-#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */\r
-#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12LD register ******************/\r
-#define DAC_DHR12LD_DACC1DHR_Pos (4U) \r
-#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
-#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */\r
-#define DAC_DHR12LD_DACC2DHR_Pos (20U) \r
-#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */\r
-#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8RD register ******************/\r
-#define DAC_DHR8RD_DACC1DHR_Pos (0U) \r
-#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */\r
-#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */\r
-#define DAC_DHR8RD_DACC2DHR_Pos (8U) \r
-#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */\r
-#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */\r
-\r
-/******************* Bit definition for DAC_DOR1 register *******************/\r
-#define DAC_DOR1_DACC1DOR_Pos (0U) \r
-#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */\r
-#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */\r
-\r
-/******************* Bit definition for DAC_DOR2 register *******************/\r
-#define DAC_DOR2_DACC2DOR_Pos (0U) \r
-#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */\r
-#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */\r
-\r
-\r
-\r
-/*****************************************************************************/\r
-/* */\r
-/* Timers (TIM) */\r
-/* */\r
-/*****************************************************************************/\r
-/******************* Bit definition for TIM_CR1 register *******************/\r
-#define TIM_CR1_CEN_Pos (0U) \r
-#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */\r
-#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */\r
-#define TIM_CR1_UDIS_Pos (1U) \r
-#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */\r
-#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */\r
-#define TIM_CR1_URS_Pos (2U) \r
-#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */\r
-#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */\r
-#define TIM_CR1_OPM_Pos (3U) \r
-#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */\r
-#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */\r
-#define TIM_CR1_DIR_Pos (4U) \r
-#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */\r
-#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */\r
-\r
-#define TIM_CR1_CMS_Pos (5U) \r
-#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */\r
-#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
-#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */\r
-#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */\r
-\r
-#define TIM_CR1_ARPE_Pos (7U) \r
-#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */\r
-#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */\r
-\r
-#define TIM_CR1_CKD_Pos (8U) \r
-#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */\r
-#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */\r
-#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */\r
-#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */\r
-\r
-/******************* Bit definition for TIM_CR2 register *******************/\r
-#define TIM_CR2_CCPC_Pos (0U) \r
-#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */\r
-#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */\r
-#define TIM_CR2_CCUS_Pos (2U) \r
-#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */\r
-#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */\r
-#define TIM_CR2_CCDS_Pos (3U) \r
-#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */\r
-#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */\r
-\r
-#define TIM_CR2_MMS_Pos (4U) \r
-#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */\r
-#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */\r
-#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */\r
-#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */\r
-#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */\r
-\r
-#define TIM_CR2_TI1S_Pos (7U) \r
-#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */\r
-#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */\r
-#define TIM_CR2_OIS1_Pos (8U) \r
-#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */\r
-#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */\r
-#define TIM_CR2_OIS1N_Pos (9U) \r
-#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */\r
-#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */\r
-#define TIM_CR2_OIS2_Pos (10U) \r
-#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */\r
-#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */\r
-#define TIM_CR2_OIS2N_Pos (11U) \r
-#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */\r
-#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */\r
-#define TIM_CR2_OIS3_Pos (12U) \r
-#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */\r
-#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */\r
-#define TIM_CR2_OIS3N_Pos (13U) \r
-#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */\r
-#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */\r
-#define TIM_CR2_OIS4_Pos (14U) \r
-#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */\r
-#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */\r
-\r
-/******************* Bit definition for TIM_SMCR register ******************/\r
-#define TIM_SMCR_SMS_Pos (0U) \r
-#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */\r
-#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */\r
-#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */\r
-#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */\r
-#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */\r
-\r
-#define TIM_SMCR_TS_Pos (4U) \r
-#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */\r
-#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */\r
-#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */\r
-#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */\r
-#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */\r
-\r
-#define TIM_SMCR_MSM_Pos (7U) \r
-#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */\r
-#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */\r
-\r
-#define TIM_SMCR_ETF_Pos (8U) \r
-#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */\r
-#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */\r
-#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */\r
-#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */\r
-#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */\r
-#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */\r
-\r
-#define TIM_SMCR_ETPS_Pos (12U) \r
-#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */\r
-#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */\r
-#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */\r
-#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */\r
-\r
-#define TIM_SMCR_ECE_Pos (14U) \r
-#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */\r
-#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */\r
-#define TIM_SMCR_ETP_Pos (15U) \r
-#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */\r
-#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */\r
-\r
-/******************* Bit definition for TIM_DIER register ******************/\r
-#define TIM_DIER_UIE_Pos (0U) \r
-#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */\r
-#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */\r
-#define TIM_DIER_CC1IE_Pos (1U) \r
-#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */\r
-#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */\r
-#define TIM_DIER_CC2IE_Pos (2U) \r
-#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */\r
-#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */\r
-#define TIM_DIER_CC3IE_Pos (3U) \r
-#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */\r
-#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */\r
-#define TIM_DIER_CC4IE_Pos (4U) \r
-#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */\r
-#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */\r
-#define TIM_DIER_COMIE_Pos (5U) \r
-#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */\r
-#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */\r
-#define TIM_DIER_TIE_Pos (6U) \r
-#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */\r
-#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */\r
-#define TIM_DIER_BIE_Pos (7U) \r
-#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */\r
-#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */\r
-#define TIM_DIER_UDE_Pos (8U) \r
-#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */\r
-#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */\r
-#define TIM_DIER_CC1DE_Pos (9U) \r
-#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */\r
-#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */\r
-#define TIM_DIER_CC2DE_Pos (10U) \r
-#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */\r
-#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */\r
-#define TIM_DIER_CC3DE_Pos (11U) \r
-#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */\r
-#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */\r
-#define TIM_DIER_CC4DE_Pos (12U) \r
-#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */\r
-#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */\r
-#define TIM_DIER_COMDE_Pos (13U) \r
-#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */\r
-#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */\r
-#define TIM_DIER_TDE_Pos (14U) \r
-#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */\r
-#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */\r
-\r
-/******************** Bit definition for TIM_SR register *******************/\r
-#define TIM_SR_UIF_Pos (0U) \r
-#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */\r
-#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */\r
-#define TIM_SR_CC1IF_Pos (1U) \r
-#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */\r
-#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */\r
-#define TIM_SR_CC2IF_Pos (2U) \r
-#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */\r
-#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */\r
-#define TIM_SR_CC3IF_Pos (3U) \r
-#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */\r
-#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */\r
-#define TIM_SR_CC4IF_Pos (4U) \r
-#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */\r
-#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */\r
-#define TIM_SR_COMIF_Pos (5U) \r
-#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */\r
-#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */\r
-#define TIM_SR_TIF_Pos (6U) \r
-#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */\r
-#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */\r
-#define TIM_SR_BIF_Pos (7U) \r
-#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */\r
-#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */\r
-#define TIM_SR_CC1OF_Pos (9U) \r
-#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */\r
-#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */\r
-#define TIM_SR_CC2OF_Pos (10U) \r
-#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */\r
-#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */\r
-#define TIM_SR_CC3OF_Pos (11U) \r
-#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */\r
-#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */\r
-#define TIM_SR_CC4OF_Pos (12U) \r
-#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */\r
-#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */\r
-\r
-/******************* Bit definition for TIM_EGR register *******************/\r
-#define TIM_EGR_UG_Pos (0U) \r
-#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */\r
-#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */\r
-#define TIM_EGR_CC1G_Pos (1U) \r
-#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */\r
-#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */\r
-#define TIM_EGR_CC2G_Pos (2U) \r
-#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */\r
-#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */\r
-#define TIM_EGR_CC3G_Pos (3U) \r
-#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */\r
-#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */\r
-#define TIM_EGR_CC4G_Pos (4U) \r
-#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */\r
-#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */\r
-#define TIM_EGR_COMG_Pos (5U) \r
-#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */\r
-#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */\r
-#define TIM_EGR_TG_Pos (6U) \r
-#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */\r
-#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */\r
-#define TIM_EGR_BG_Pos (7U) \r
-#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */\r
-#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */\r
-\r
-/****************** Bit definition for TIM_CCMR1 register ******************/\r
-#define TIM_CCMR1_CC1S_Pos (0U) \r
-#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */\r
-#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
-#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */\r
-#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */\r
-\r
-#define TIM_CCMR1_OC1FE_Pos (2U) \r
-#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */\r
-#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */\r
-#define TIM_CCMR1_OC1PE_Pos (3U) \r
-#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */\r
-#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */\r
-\r
-#define TIM_CCMR1_OC1M_Pos (4U) \r
-#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */\r
-#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
-#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */\r
-#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */\r
-#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */\r
-\r
-#define TIM_CCMR1_OC1CE_Pos (7U) \r
-#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */\r
-#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */\r
-\r
-#define TIM_CCMR1_CC2S_Pos (8U) \r
-#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */\r
-#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
-#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */\r
-#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */\r
-\r
-#define TIM_CCMR1_OC2FE_Pos (10U) \r
-#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */\r
-#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */\r
-#define TIM_CCMR1_OC2PE_Pos (11U) \r
-#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */\r
-#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */\r
-\r
-#define TIM_CCMR1_OC2M_Pos (12U) \r
-#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */\r
-#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
-#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */\r
-#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */\r
-#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */\r
-\r
-#define TIM_CCMR1_OC2CE_Pos (15U) \r
-#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */\r
-#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */\r
-\r
-/*---------------------------------------------------------------------------*/\r
-\r
-#define TIM_CCMR1_IC1PSC_Pos (2U) \r
-#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */\r
-#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
-#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */\r
-#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */\r
-\r
-#define TIM_CCMR1_IC1F_Pos (4U) \r
-#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */\r
-#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
-#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */\r
-#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */\r
-#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */\r
-#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */\r
-\r
-#define TIM_CCMR1_IC2PSC_Pos (10U) \r
-#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */\r
-#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
-#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */\r
-#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */\r
-\r
-#define TIM_CCMR1_IC2F_Pos (12U) \r
-#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */\r
-#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
-#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */\r
-#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */\r
-#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */\r
-#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */\r
-\r
-/****************** Bit definition for TIM_CCMR2 register ******************/\r
-#define TIM_CCMR2_CC3S_Pos (0U) \r
-#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */\r
-#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
-#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */\r
-#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */\r
-\r
-#define TIM_CCMR2_OC3FE_Pos (2U) \r
-#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */\r
-#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */\r
-#define TIM_CCMR2_OC3PE_Pos (3U) \r
-#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */\r
-#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */\r
-\r
-#define TIM_CCMR2_OC3M_Pos (4U) \r
-#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */\r
-#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
-#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */\r
-#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */\r
-#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */\r
-\r
-#define TIM_CCMR2_OC3CE_Pos (7U) \r
-#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */\r
-#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */\r
-\r
-#define TIM_CCMR2_CC4S_Pos (8U) \r
-#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */\r
-#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
-#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */\r
-#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */\r
-\r
-#define TIM_CCMR2_OC4FE_Pos (10U) \r
-#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */\r
-#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */\r
-#define TIM_CCMR2_OC4PE_Pos (11U) \r
-#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */\r
-#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */\r
-\r
-#define TIM_CCMR2_OC4M_Pos (12U) \r
-#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */\r
-#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
-#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */\r
-#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */\r
-#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */\r
-\r
-#define TIM_CCMR2_OC4CE_Pos (15U) \r
-#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */\r
-#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */\r
-\r
-/*---------------------------------------------------------------------------*/\r
-\r
-#define TIM_CCMR2_IC3PSC_Pos (2U) \r
-#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */\r
-#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
-#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */\r
-#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */\r
-\r
-#define TIM_CCMR2_IC3F_Pos (4U) \r
-#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */\r
-#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
-#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */\r
-#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */\r
-#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */\r
-#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */\r
-\r
-#define TIM_CCMR2_IC4PSC_Pos (10U) \r
-#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */\r
-#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
-#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */\r
-#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */\r
-\r
-#define TIM_CCMR2_IC4F_Pos (12U) \r
-#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */\r
-#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
-#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */\r
-#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */\r
-#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */\r
-#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */\r
-\r
-/******************* Bit definition for TIM_CCER register ******************/\r
-#define TIM_CCER_CC1E_Pos (0U) \r
-#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */\r
-#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */\r
-#define TIM_CCER_CC1P_Pos (1U) \r
-#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */\r
-#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */\r
-#define TIM_CCER_CC1NE_Pos (2U) \r
-#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */\r
-#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */\r
-#define TIM_CCER_CC1NP_Pos (3U) \r
-#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */\r
-#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */\r
-#define TIM_CCER_CC2E_Pos (4U) \r
-#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */\r
-#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */\r
-#define TIM_CCER_CC2P_Pos (5U) \r
-#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */\r
-#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */\r
-#define TIM_CCER_CC2NE_Pos (6U) \r
-#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */\r
-#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */\r
-#define TIM_CCER_CC2NP_Pos (7U) \r
-#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */\r
-#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */\r
-#define TIM_CCER_CC3E_Pos (8U) \r
-#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */\r
-#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */\r
-#define TIM_CCER_CC3P_Pos (9U) \r
-#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */\r
-#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */\r
-#define TIM_CCER_CC3NE_Pos (10U) \r
-#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */\r
-#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */\r
-#define TIM_CCER_CC3NP_Pos (11U) \r
-#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */\r
-#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */\r
-#define TIM_CCER_CC4E_Pos (12U) \r
-#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */\r
-#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */\r
-#define TIM_CCER_CC4P_Pos (13U) \r
-#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */\r
-#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */\r
-\r
-/******************* Bit definition for TIM_CNT register *******************/\r
-#define TIM_CNT_CNT_Pos (0U) \r
-#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */\r
-#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */\r
-\r
-/******************* Bit definition for TIM_PSC register *******************/\r
-#define TIM_PSC_PSC_Pos (0U) \r
-#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */\r
-#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */\r
-\r
-/******************* Bit definition for TIM_ARR register *******************/\r
-#define TIM_ARR_ARR_Pos (0U) \r
-#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */\r
-#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */\r
-\r
-/******************* Bit definition for TIM_RCR register *******************/\r
-#define TIM_RCR_REP_Pos (0U) \r
-#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */\r
-#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */\r
-\r
-/******************* Bit definition for TIM_CCR1 register ******************/\r
-#define TIM_CCR1_CCR1_Pos (0U) \r
-#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */\r
-#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */\r
-\r
-/******************* Bit definition for TIM_CCR2 register ******************/\r
-#define TIM_CCR2_CCR2_Pos (0U) \r
-#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */\r
-#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */\r
-\r
-/******************* Bit definition for TIM_CCR3 register ******************/\r
-#define TIM_CCR3_CCR3_Pos (0U) \r
-#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */\r
-#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */\r
-\r
-/******************* Bit definition for TIM_CCR4 register ******************/\r
-#define TIM_CCR4_CCR4_Pos (0U) \r
-#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */\r
-#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */\r
-\r
-/******************* Bit definition for TIM_BDTR register ******************/\r
-#define TIM_BDTR_DTG_Pos (0U) \r
-#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */\r
-#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
-#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */\r
-#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */\r
-#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */\r
-#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */\r
-#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */\r
-#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */\r
-#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */\r
-#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */\r
-\r
-#define TIM_BDTR_LOCK_Pos (8U) \r
-#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */\r
-#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */\r
-#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */\r
-#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */\r
-\r
-#define TIM_BDTR_OSSI_Pos (10U) \r
-#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */\r
-#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */\r
-#define TIM_BDTR_OSSR_Pos (11U) \r
-#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */\r
-#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */\r
-#define TIM_BDTR_BKE_Pos (12U) \r
-#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */\r
-#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */\r
-#define TIM_BDTR_BKP_Pos (13U) \r
-#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */\r
-#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */\r
-#define TIM_BDTR_AOE_Pos (14U) \r
-#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */\r
-#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */\r
-#define TIM_BDTR_MOE_Pos (15U) \r
-#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */\r
-#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */\r
-\r
-/******************* Bit definition for TIM_DCR register *******************/\r
-#define TIM_DCR_DBA_Pos (0U) \r
-#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */\r
-#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */\r
-#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */\r
-#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */\r
-#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */\r
-#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */\r
-#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */\r
-\r
-#define TIM_DCR_DBL_Pos (8U) \r
-#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */\r
-#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */\r
-#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */\r
-#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */\r
-#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */\r
-#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */\r
-#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */\r
-\r
-/******************* Bit definition for TIM_DMAR register ******************/\r
-#define TIM_DMAR_DMAB_Pos (0U) \r
-#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */\r
-#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Real-Time Clock */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for RTC_CRH register ********************/\r
-#define RTC_CRH_SECIE_Pos (0U) \r
-#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */\r
-#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */\r
-#define RTC_CRH_ALRIE_Pos (1U) \r
-#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */\r
-#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */\r
-#define RTC_CRH_OWIE_Pos (2U) \r
-#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */\r
-#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */\r
-\r
-/******************* Bit definition for RTC_CRL register ********************/\r
-#define RTC_CRL_SECF_Pos (0U) \r
-#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */\r
-#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */\r
-#define RTC_CRL_ALRF_Pos (1U) \r
-#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */\r
-#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */\r
-#define RTC_CRL_OWF_Pos (2U) \r
-#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */\r
-#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */\r
-#define RTC_CRL_RSF_Pos (3U) \r
-#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */\r
-#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */\r
-#define RTC_CRL_CNF_Pos (4U) \r
-#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */\r
-#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */\r
-#define RTC_CRL_RTOFF_Pos (5U) \r
-#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */\r
-#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */\r
-\r
-/******************* Bit definition for RTC_PRLH register *******************/\r
-#define RTC_PRLH_PRL_Pos (0U) \r
-#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */\r
-#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */\r
-\r
-/******************* Bit definition for RTC_PRLL register *******************/\r
-#define RTC_PRLL_PRL_Pos (0U) \r
-#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */\r
-#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */\r
-\r
-/******************* Bit definition for RTC_DIVH register *******************/\r
-#define RTC_DIVH_RTC_DIV_Pos (0U) \r
-#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */\r
-#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */\r
-\r
-/******************* Bit definition for RTC_DIVL register *******************/\r
-#define RTC_DIVL_RTC_DIV_Pos (0U) \r
-#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */\r
-#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */\r
-\r
-/******************* Bit definition for RTC_CNTH register *******************/\r
-#define RTC_CNTH_RTC_CNT_Pos (0U) \r
-#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */\r
-#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */\r
-\r
-/******************* Bit definition for RTC_CNTL register *******************/\r
-#define RTC_CNTL_RTC_CNT_Pos (0U) \r
-#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */\r
-#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */\r
-\r
-/******************* Bit definition for RTC_ALRH register *******************/\r
-#define RTC_ALRH_RTC_ALR_Pos (0U) \r
-#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */\r
-#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */\r
-\r
-/******************* Bit definition for RTC_ALRL register *******************/\r
-#define RTC_ALRL_RTC_ALR_Pos (0U) \r
-#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */\r
-#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Independent WATCHDOG (IWDG) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for IWDG_KR register ********************/\r
-#define IWDG_KR_KEY_Pos (0U) \r
-#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */\r
-#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */\r
-\r
-/******************* Bit definition for IWDG_PR register ********************/\r
-#define IWDG_PR_PR_Pos (0U) \r
-#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */\r
-#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */\r
-#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */\r
-#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */\r
-#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */\r
-\r
-/******************* Bit definition for IWDG_RLR register *******************/\r
-#define IWDG_RLR_RL_Pos (0U) \r
-#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */\r
-#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */\r
-\r
-/******************* Bit definition for IWDG_SR register ********************/\r
-#define IWDG_SR_PVU_Pos (0U) \r
-#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */\r
-#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */\r
-#define IWDG_SR_RVU_Pos (1U) \r
-#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */\r
-#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Window WATCHDOG (WWDG) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for WWDG_CR register ********************/\r
-#define WWDG_CR_T_Pos (0U) \r
-#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */\r
-#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
-#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */\r
-#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */\r
-#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */\r
-#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */\r
-#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */\r
-#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */\r
-#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */\r
-\r
-/* Legacy defines */\r
-#define WWDG_CR_T0 WWDG_CR_T_0\r
-#define WWDG_CR_T1 WWDG_CR_T_1\r
-#define WWDG_CR_T2 WWDG_CR_T_2\r
-#define WWDG_CR_T3 WWDG_CR_T_3\r
-#define WWDG_CR_T4 WWDG_CR_T_4\r
-#define WWDG_CR_T5 WWDG_CR_T_5\r
-#define WWDG_CR_T6 WWDG_CR_T_6\r
-\r
-#define WWDG_CR_WDGA_Pos (7U) \r
-#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */\r
-#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */\r
-\r
-/******************* Bit definition for WWDG_CFR register *******************/\r
-#define WWDG_CFR_W_Pos (0U) \r
-#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */\r
-#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */\r
-#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */\r
-#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */\r
-#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */\r
-#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */\r
-#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */\r
-#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */\r
-#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */\r
-\r
-/* Legacy defines */\r
-#define WWDG_CFR_W0 WWDG_CFR_W_0\r
-#define WWDG_CFR_W1 WWDG_CFR_W_1\r
-#define WWDG_CFR_W2 WWDG_CFR_W_2\r
-#define WWDG_CFR_W3 WWDG_CFR_W_3\r
-#define WWDG_CFR_W4 WWDG_CFR_W_4\r
-#define WWDG_CFR_W5 WWDG_CFR_W_5\r
-#define WWDG_CFR_W6 WWDG_CFR_W_6\r
-\r
-#define WWDG_CFR_WDGTB_Pos (7U) \r
-#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */\r
-#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */\r
-#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */\r
-#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */\r
-\r
-/* Legacy defines */\r
-#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0\r
-#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1\r
-\r
-#define WWDG_CFR_EWI_Pos (9U) \r
-#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */\r
-#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */\r
-\r
-/******************* Bit definition for WWDG_SR register ********************/\r
-#define WWDG_SR_EWIF_Pos (0U) \r
-#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */\r
-#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Flexible Static Memory Controller */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/****************** Bit definition for FSMC_BCRx (x=1..4) register **********/\r
-#define FSMC_BCRx_MBKEN_Pos (0U) \r
-#define FSMC_BCRx_MBKEN_Msk (0x1U << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */\r
-#define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */\r
-#define FSMC_BCRx_MUXEN_Pos (1U) \r
-#define FSMC_BCRx_MUXEN_Msk (0x1U << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */\r
-#define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */\r
-\r
-#define FSMC_BCRx_MTYP_Pos (2U) \r
-#define FSMC_BCRx_MTYP_Msk (0x3U << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */\r
-#define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */\r
-#define FSMC_BCRx_MTYP_0 (0x1U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */\r
-#define FSMC_BCRx_MTYP_1 (0x2U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */\r
-\r
-#define FSMC_BCRx_MWID_Pos (4U) \r
-#define FSMC_BCRx_MWID_Msk (0x3U << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */\r
-#define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */\r
-#define FSMC_BCRx_MWID_0 (0x1U << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */\r
-#define FSMC_BCRx_MWID_1 (0x2U << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */\r
-\r
-#define FSMC_BCRx_FACCEN_Pos (6U) \r
-#define FSMC_BCRx_FACCEN_Msk (0x1U << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */\r
-#define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */\r
-#define FSMC_BCRx_BURSTEN_Pos (8U) \r
-#define FSMC_BCRx_BURSTEN_Msk (0x1U << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */\r
-#define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */\r
-#define FSMC_BCRx_WAITPOL_Pos (9U) \r
-#define FSMC_BCRx_WAITPOL_Msk (0x1U << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */\r
-#define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */\r
-#define FSMC_BCRx_WRAPMOD_Pos (10U) \r
-#define FSMC_BCRx_WRAPMOD_Msk (0x1U << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */\r
-#define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */\r
-#define FSMC_BCRx_WAITCFG_Pos (11U) \r
-#define FSMC_BCRx_WAITCFG_Msk (0x1U << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */\r
-#define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */\r
-#define FSMC_BCRx_WREN_Pos (12U) \r
-#define FSMC_BCRx_WREN_Msk (0x1U << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */\r
-#define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */\r
-#define FSMC_BCRx_WAITEN_Pos (13U) \r
-#define FSMC_BCRx_WAITEN_Msk (0x1U << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */\r
-#define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */\r
-#define FSMC_BCRx_EXTMOD_Pos (14U) \r
-#define FSMC_BCRx_EXTMOD_Msk (0x1U << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */\r
-#define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */\r
-#define FSMC_BCRx_ASYNCWAIT_Pos (15U) \r
-#define FSMC_BCRx_ASYNCWAIT_Msk (0x1U << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
-#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */\r
-#define FSMC_BCRx_CBURSTRW_Pos (19U) \r
-#define FSMC_BCRx_CBURSTRW_Msk (0x1U << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */\r
-#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */\r
-\r
-/****************** Bit definition for FSMC_BTRx (x=1..4) register ******/\r
-#define FSMC_BTRx_ADDSET_Pos (0U) \r
-#define FSMC_BTRx_ADDSET_Msk (0xFU << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */\r
-#define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BTRx_ADDSET_0 (0x1U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */\r
-#define FSMC_BTRx_ADDSET_1 (0x2U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */\r
-#define FSMC_BTRx_ADDSET_2 (0x4U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */\r
-#define FSMC_BTRx_ADDSET_3 (0x8U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */\r
-\r
-#define FSMC_BTRx_ADDHLD_Pos (4U) \r
-#define FSMC_BTRx_ADDHLD_Msk (0xFU << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */\r
-#define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BTRx_ADDHLD_0 (0x1U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */\r
-#define FSMC_BTRx_ADDHLD_1 (0x2U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */\r
-#define FSMC_BTRx_ADDHLD_2 (0x4U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */\r
-#define FSMC_BTRx_ADDHLD_3 (0x8U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */\r
-\r
-#define FSMC_BTRx_DATAST_Pos (8U) \r
-#define FSMC_BTRx_DATAST_Msk (0xFFU << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */\r
-#define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BTRx_DATAST_0 (0x01U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */\r
-#define FSMC_BTRx_DATAST_1 (0x02U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */\r
-#define FSMC_BTRx_DATAST_2 (0x04U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */\r
-#define FSMC_BTRx_DATAST_3 (0x08U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */\r
-#define FSMC_BTRx_DATAST_4 (0x10U << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */\r
-#define FSMC_BTRx_DATAST_5 (0x20U << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */\r
-#define FSMC_BTRx_DATAST_6 (0x40U << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */\r
-#define FSMC_BTRx_DATAST_7 (0x80U << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */\r
-\r
-#define FSMC_BTRx_BUSTURN_Pos (16U) \r
-#define FSMC_BTRx_BUSTURN_Msk (0xFU << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */\r
-#define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BTRx_BUSTURN_0 (0x1U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */\r
-#define FSMC_BTRx_BUSTURN_1 (0x2U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */\r
-#define FSMC_BTRx_BUSTURN_2 (0x4U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */\r
-#define FSMC_BTRx_BUSTURN_3 (0x8U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */\r
-\r
-#define FSMC_BTRx_CLKDIV_Pos (20U) \r
-#define FSMC_BTRx_CLKDIV_Msk (0xFU << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */\r
-#define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BTRx_CLKDIV_0 (0x1U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */\r
-#define FSMC_BTRx_CLKDIV_1 (0x2U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */\r
-#define FSMC_BTRx_CLKDIV_2 (0x4U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */\r
-#define FSMC_BTRx_CLKDIV_3 (0x8U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */\r
-\r
-#define FSMC_BTRx_DATLAT_Pos (24U) \r
-#define FSMC_BTRx_DATLAT_Msk (0xFU << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */\r
-#define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BTRx_DATLAT_0 (0x1U << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */\r
-#define FSMC_BTRx_DATLAT_1 (0x2U << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */\r
-#define FSMC_BTRx_DATLAT_2 (0x4U << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */\r
-#define FSMC_BTRx_DATLAT_3 (0x8U << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */\r
-\r
-#define FSMC_BTRx_ACCMOD_Pos (28U) \r
-#define FSMC_BTRx_ACCMOD_Msk (0x3U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */\r
-#define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BTRx_ACCMOD_0 (0x1U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */\r
-#define FSMC_BTRx_ACCMOD_1 (0x2U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */\r
-\r
-/****************** Bit definition for FSMC_BWTRx (x=1..4) register ******/\r
-#define FSMC_BWTRx_ADDSET_Pos (0U) \r
-#define FSMC_BWTRx_ADDSET_Msk (0xFU << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */\r
-#define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BWTRx_ADDSET_0 (0x1U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */\r
-#define FSMC_BWTRx_ADDSET_1 (0x2U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */\r
-#define FSMC_BWTRx_ADDSET_2 (0x4U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */\r
-#define FSMC_BWTRx_ADDSET_3 (0x8U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */\r
-\r
-#define FSMC_BWTRx_ADDHLD_Pos (4U) \r
-#define FSMC_BWTRx_ADDHLD_Msk (0xFU << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */\r
-#define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BWTRx_ADDHLD_0 (0x1U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */\r
-#define FSMC_BWTRx_ADDHLD_1 (0x2U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */\r
-#define FSMC_BWTRx_ADDHLD_2 (0x4U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */\r
-#define FSMC_BWTRx_ADDHLD_3 (0x8U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */\r
-\r
-#define FSMC_BWTRx_DATAST_Pos (8U) \r
-#define FSMC_BWTRx_DATAST_Msk (0xFFU << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */\r
-#define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BWTRx_DATAST_0 (0x01U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */\r
-#define FSMC_BWTRx_DATAST_1 (0x02U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */\r
-#define FSMC_BWTRx_DATAST_2 (0x04U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */\r
-#define FSMC_BWTRx_DATAST_3 (0x08U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */\r
-#define FSMC_BWTRx_DATAST_4 (0x10U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */\r
-#define FSMC_BWTRx_DATAST_5 (0x20U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */\r
-#define FSMC_BWTRx_DATAST_6 (0x40U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */\r
-#define FSMC_BWTRx_DATAST_7 (0x80U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */\r
-\r
-#define FSMC_BWTRx_BUSTURN_Pos (16U) \r
-#define FSMC_BWTRx_BUSTURN_Msk (0xFU << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */\r
-#define FSMC_BWTRx_BUSTURN FSMC_BWTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BWTRx_BUSTURN_0 (0x1U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */\r
-#define FSMC_BWTRx_BUSTURN_1 (0x2U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */\r
-#define FSMC_BWTRx_BUSTURN_2 (0x4U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */\r
-#define FSMC_BWTRx_BUSTURN_3 (0x8U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */\r
-\r
-#define FSMC_BWTRx_ACCMOD_Pos (28U) \r
-#define FSMC_BWTRx_ACCMOD_Msk (0x3U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */\r
-#define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BWTRx_ACCMOD_0 (0x1U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */\r
-#define FSMC_BWTRx_ACCMOD_1 (0x2U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */\r
-\r
-/****************** Bit definition for FSMC_PCRx (x = 2 to 4) register *******************/\r
-#define FSMC_PCRx_PWAITEN_Pos (1U) \r
-#define FSMC_PCRx_PWAITEN_Msk (0x1U << FSMC_PCRx_PWAITEN_Pos) /*!< 0x00000002 */\r
-#define FSMC_PCRx_PWAITEN FSMC_PCRx_PWAITEN_Msk /*!< Wait feature enable bit */\r
-#define FSMC_PCRx_PBKEN_Pos (2U) \r
-#define FSMC_PCRx_PBKEN_Msk (0x1U << FSMC_PCRx_PBKEN_Pos) /*!< 0x00000004 */\r
-#define FSMC_PCRx_PBKEN FSMC_PCRx_PBKEN_Msk /*!< PC Card/NAND Flash memory bank enable bit */\r
-#define FSMC_PCRx_PTYP_Pos (3U) \r
-#define FSMC_PCRx_PTYP_Msk (0x1U << FSMC_PCRx_PTYP_Pos) /*!< 0x00000008 */\r
-#define FSMC_PCRx_PTYP FSMC_PCRx_PTYP_Msk /*!< Memory type */\r
-\r
-#define FSMC_PCRx_PWID_Pos (4U) \r
-#define FSMC_PCRx_PWID_Msk (0x3U << FSMC_PCRx_PWID_Pos) /*!< 0x00000030 */\r
-#define FSMC_PCRx_PWID FSMC_PCRx_PWID_Msk /*!< PWID[1:0] bits (NAND Flash databus width) */\r
-#define FSMC_PCRx_PWID_0 (0x1U << FSMC_PCRx_PWID_Pos) /*!< 0x00000010 */\r
-#define FSMC_PCRx_PWID_1 (0x2U << FSMC_PCRx_PWID_Pos) /*!< 0x00000020 */\r
-\r
-#define FSMC_PCRx_ECCEN_Pos (6U) \r
-#define FSMC_PCRx_ECCEN_Msk (0x1U << FSMC_PCRx_ECCEN_Pos) /*!< 0x00000040 */\r
-#define FSMC_PCRx_ECCEN FSMC_PCRx_ECCEN_Msk /*!< ECC computation logic enable bit */\r
-\r
-#define FSMC_PCRx_TCLR_Pos (9U) \r
-#define FSMC_PCRx_TCLR_Msk (0xFU << FSMC_PCRx_TCLR_Pos) /*!< 0x00001E00 */\r
-#define FSMC_PCRx_TCLR FSMC_PCRx_TCLR_Msk /*!< TCLR[3:0] bits (CLE to RE delay) */\r
-#define FSMC_PCRx_TCLR_0 (0x1U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000200 */\r
-#define FSMC_PCRx_TCLR_1 (0x2U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000400 */\r
-#define FSMC_PCRx_TCLR_2 (0x4U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000800 */\r
-#define FSMC_PCRx_TCLR_3 (0x8U << FSMC_PCRx_TCLR_Pos) /*!< 0x00001000 */\r
-\r
-#define FSMC_PCRx_TAR_Pos (13U) \r
-#define FSMC_PCRx_TAR_Msk (0xFU << FSMC_PCRx_TAR_Pos) /*!< 0x0001E000 */\r
-#define FSMC_PCRx_TAR FSMC_PCRx_TAR_Msk /*!< TAR[3:0] bits (ALE to RE delay) */\r
-#define FSMC_PCRx_TAR_0 (0x1U << FSMC_PCRx_TAR_Pos) /*!< 0x00002000 */\r
-#define FSMC_PCRx_TAR_1 (0x2U << FSMC_PCRx_TAR_Pos) /*!< 0x00004000 */\r
-#define FSMC_PCRx_TAR_2 (0x4U << FSMC_PCRx_TAR_Pos) /*!< 0x00008000 */\r
-#define FSMC_PCRx_TAR_3 (0x8U << FSMC_PCRx_TAR_Pos) /*!< 0x00010000 */\r
-\r
-#define FSMC_PCRx_ECCPS_Pos (17U) \r
-#define FSMC_PCRx_ECCPS_Msk (0x7U << FSMC_PCRx_ECCPS_Pos) /*!< 0x000E0000 */\r
-#define FSMC_PCRx_ECCPS FSMC_PCRx_ECCPS_Msk /*!< ECCPS[1:0] bits (ECC page size) */\r
-#define FSMC_PCRx_ECCPS_0 (0x1U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00020000 */\r
-#define FSMC_PCRx_ECCPS_1 (0x2U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00040000 */\r
-#define FSMC_PCRx_ECCPS_2 (0x4U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00080000 */\r
-\r
-/******************* Bit definition for FSMC_SRx (x = 2 to 4) register *******************/\r
-#define FSMC_SRx_IRS_Pos (0U) \r
-#define FSMC_SRx_IRS_Msk (0x1U << FSMC_SRx_IRS_Pos) /*!< 0x00000001 */\r
-#define FSMC_SRx_IRS FSMC_SRx_IRS_Msk /*!< Interrupt Rising Edge status */\r
-#define FSMC_SRx_ILS_Pos (1U) \r
-#define FSMC_SRx_ILS_Msk (0x1U << FSMC_SRx_ILS_Pos) /*!< 0x00000002 */\r
-#define FSMC_SRx_ILS FSMC_SRx_ILS_Msk /*!< Interrupt Level status */\r
-#define FSMC_SRx_IFS_Pos (2U) \r
-#define FSMC_SRx_IFS_Msk (0x1U << FSMC_SRx_IFS_Pos) /*!< 0x00000004 */\r
-#define FSMC_SRx_IFS FSMC_SRx_IFS_Msk /*!< Interrupt Falling Edge status */\r
-#define FSMC_SRx_IREN_Pos (3U) \r
-#define FSMC_SRx_IREN_Msk (0x1U << FSMC_SRx_IREN_Pos) /*!< 0x00000008 */\r
-#define FSMC_SRx_IREN FSMC_SRx_IREN_Msk /*!< Interrupt Rising Edge detection Enable bit */\r
-#define FSMC_SRx_ILEN_Pos (4U) \r
-#define FSMC_SRx_ILEN_Msk (0x1U << FSMC_SRx_ILEN_Pos) /*!< 0x00000010 */\r
-#define FSMC_SRx_ILEN FSMC_SRx_ILEN_Msk /*!< Interrupt Level detection Enable bit */\r
-#define FSMC_SRx_IFEN_Pos (5U) \r
-#define FSMC_SRx_IFEN_Msk (0x1U << FSMC_SRx_IFEN_Pos) /*!< 0x00000020 */\r
-#define FSMC_SRx_IFEN FSMC_SRx_IFEN_Msk /*!< Interrupt Falling Edge detection Enable bit */\r
-#define FSMC_SRx_FEMPT_Pos (6U) \r
-#define FSMC_SRx_FEMPT_Msk (0x1U << FSMC_SRx_FEMPT_Pos) /*!< 0x00000040 */\r
-#define FSMC_SRx_FEMPT FSMC_SRx_FEMPT_Msk /*!< FIFO empty */\r
-\r
-/****************** Bit definition for FSMC_PMEMx (x = 2 to 4) register ******************/\r
-#define FSMC_PMEMx_MEMSETx_Pos (0U) \r
-#define FSMC_PMEMx_MEMSETx_Msk (0xFFU << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x000000FF */\r
-#define FSMC_PMEMx_MEMSETx FSMC_PMEMx_MEMSETx_Msk /*!< MEMSETx[7:0] bits (Common memory x setup time) */\r
-#define FSMC_PMEMx_MEMSETx_0 (0x01U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000001 */\r
-#define FSMC_PMEMx_MEMSETx_1 (0x02U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000002 */\r
-#define FSMC_PMEMx_MEMSETx_2 (0x04U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000004 */\r
-#define FSMC_PMEMx_MEMSETx_3 (0x08U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000008 */\r
-#define FSMC_PMEMx_MEMSETx_4 (0x10U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000010 */\r
-#define FSMC_PMEMx_MEMSETx_5 (0x20U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000020 */\r
-#define FSMC_PMEMx_MEMSETx_6 (0x40U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000040 */\r
-#define FSMC_PMEMx_MEMSETx_7 (0x80U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000080 */\r
-\r
-#define FSMC_PMEMx_MEMWAITx_Pos (8U) \r
-#define FSMC_PMEMx_MEMWAITx_Msk (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */\r
-#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /*!< MEMWAITx[7:0] bits (Common memory x wait time) */\r
-#define FSMC_PMEMx_MEMWAIT2_0 0x00000100U /*!< Bit 0 */\r
-#define FSMC_PMEMx_MEMWAITx_1 0x00000200U /*!< Bit 1 */\r
-#define FSMC_PMEMx_MEMWAITx_2 0x00000400U /*!< Bit 2 */\r
-#define FSMC_PMEMx_MEMWAITx_3 0x00000800U /*!< Bit 3 */\r
-#define FSMC_PMEMx_MEMWAITx_4 0x00001000U /*!< Bit 4 */\r
-#define FSMC_PMEMx_MEMWAITx_5 0x00002000U /*!< Bit 5 */\r
-#define FSMC_PMEMx_MEMWAITx_6 0x00004000U /*!< Bit 6 */\r
-#define FSMC_PMEMx_MEMWAITx_7 0x00008000U /*!< Bit 7 */\r
-\r
-#define FSMC_PMEMx_MEMHOLDx_Pos (16U) \r
-#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */\r
-#define FSMC_PMEMx_MEMHOLDx FSMC_PMEMx_MEMHOLDx_Msk /*!< MEMHOLDx[7:0] bits (Common memory x hold time) */\r
-#define FSMC_PMEMx_MEMHOLDx_0 (0x01U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00010000 */\r
-#define FSMC_PMEMx_MEMHOLDx_1 (0x02U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00020000 */\r
-#define FSMC_PMEMx_MEMHOLDx_2 (0x04U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00040000 */\r
-#define FSMC_PMEMx_MEMHOLDx_3 (0x08U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00080000 */\r
-#define FSMC_PMEMx_MEMHOLDx_4 (0x10U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00100000 */\r
-#define FSMC_PMEMx_MEMHOLDx_5 (0x20U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00200000 */\r
-#define FSMC_PMEMx_MEMHOLDx_6 (0x40U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00400000 */\r
-#define FSMC_PMEMx_MEMHOLDx_7 (0x80U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00800000 */\r
-\r
-#define FSMC_PMEMx_MEMHIZx_Pos (24U) \r
-#define FSMC_PMEMx_MEMHIZx_Msk (0xFFU << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0xFF000000 */\r
-#define FSMC_PMEMx_MEMHIZx FSMC_PMEMx_MEMHIZx_Msk /*!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) */\r
-#define FSMC_PMEMx_MEMHIZx_0 (0x01U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x01000000 */\r
-#define FSMC_PMEMx_MEMHIZx_1 (0x02U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x02000000 */\r
-#define FSMC_PMEMx_MEMHIZx_2 (0x04U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x04000000 */\r
-#define FSMC_PMEMx_MEMHIZx_3 (0x08U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x08000000 */\r
-#define FSMC_PMEMx_MEMHIZx_4 (0x10U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x10000000 */\r
-#define FSMC_PMEMx_MEMHIZx_5 (0x20U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x20000000 */\r
-#define FSMC_PMEMx_MEMHIZx_6 (0x40U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x40000000 */\r
-#define FSMC_PMEMx_MEMHIZx_7 (0x80U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x80000000 */\r
-\r
-/****************** Bit definition for FSMC_PATTx (x = 2 to 4) register ******************/\r
-#define FSMC_PATTx_ATTSETx_Pos (0U) \r
-#define FSMC_PATTx_ATTSETx_Msk (0xFFU << FSMC_PATTx_ATTSETx_Pos) /*!< 0x000000FF */\r
-#define FSMC_PATTx_ATTSETx FSMC_PATTx_ATTSETx_Msk /*!< ATTSETx[7:0] bits (Attribute memory x setup time) */\r
-#define FSMC_PATTx_ATTSETx_0 (0x01U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000001 */\r
-#define FSMC_PATTx_ATTSETx_1 (0x02U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000002 */\r
-#define FSMC_PATTx_ATTSETx_2 (0x04U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000004 */\r
-#define FSMC_PATTx_ATTSETx_3 (0x08U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000008 */\r
-#define FSMC_PATTx_ATTSETx_4 (0x10U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000010 */\r
-#define FSMC_PATTx_ATTSETx_5 (0x20U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000020 */\r
-#define FSMC_PATTx_ATTSETx_6 (0x40U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000040 */\r
-#define FSMC_PATTx_ATTSETx_7 (0x80U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000080 */\r
-\r
-#define FSMC_PATTx_ATTWAITx_Pos (8U) \r
-#define FSMC_PATTx_ATTWAITx_Msk (0xFFU << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x0000FF00 */\r
-#define FSMC_PATTx_ATTWAITx FSMC_PATTx_ATTWAITx_Msk /*!< ATTWAITx[7:0] bits (Attribute memory x wait time) */\r
-#define FSMC_PATTx_ATTWAITx_0 (0x01U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000100 */\r
-#define FSMC_PATTx_ATTWAITx_1 (0x02U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000200 */\r
-#define FSMC_PATTx_ATTWAITx_2 (0x04U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000400 */\r
-#define FSMC_PATTx_ATTWAITx_3 (0x08U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000800 */\r
-#define FSMC_PATTx_ATTWAITx_4 (0x10U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00001000 */\r
-#define FSMC_PATTx_ATTWAITx_5 (0x20U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00002000 */\r
-#define FSMC_PATTx_ATTWAITx_6 (0x40U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00004000 */\r
-#define FSMC_PATTx_ATTWAITx_7 (0x80U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00008000 */\r
-\r
-#define FSMC_PATTx_ATTHOLDx_Pos (16U) \r
-#define FSMC_PATTx_ATTHOLDx_Msk (0xFFU << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */\r
-#define FSMC_PATTx_ATTHOLDx FSMC_PATTx_ATTHOLDx_Msk /*!< ATTHOLDx[7:0] bits (Attribute memory x hold time) */\r
-#define FSMC_PATTx_ATTHOLDx_0 (0x01U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */\r
-#define FSMC_PATTx_ATTHOLDx_1 (0x02U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */\r
-#define FSMC_PATTx_ATTHOLDx_2 (0x04U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */\r
-#define FSMC_PATTx_ATTHOLDx_3 (0x08U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */\r
-#define FSMC_PATTx_ATTHOLDx_4 (0x10U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */\r
-#define FSMC_PATTx_ATTHOLDx_5 (0x20U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */\r
-#define FSMC_PATTx_ATTHOLDx_6 (0x40U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */\r
-#define FSMC_PATTx_ATTHOLDx_7 (0x80U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */\r
-\r
-#define FSMC_PATTx_ATTHIZx_Pos (24U) \r
-#define FSMC_PATTx_ATTHIZx_Msk (0xFFU << FSMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */\r
-#define FSMC_PATTx_ATTHIZx FSMC_PATTx_ATTHIZx_Msk /*!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */\r
-#define FSMC_PATTx_ATTHIZx_0 (0x01U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */\r
-#define FSMC_PATTx_ATTHIZx_1 (0x02U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */\r
-#define FSMC_PATTx_ATTHIZx_2 (0x04U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */\r
-#define FSMC_PATTx_ATTHIZx_3 (0x08U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */\r
-#define FSMC_PATTx_ATTHIZx_4 (0x10U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */\r
-#define FSMC_PATTx_ATTHIZx_5 (0x20U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */\r
-#define FSMC_PATTx_ATTHIZx_6 (0x40U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */\r
-#define FSMC_PATTx_ATTHIZx_7 (0x80U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */\r
-\r
-/****************** Bit definition for FSMC_PIO4 register *******************/\r
-#define FSMC_PIO4_IOSET4_Pos (0U) \r
-#define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */\r
-#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!< IOSET4[7:0] bits (I/O 4 setup time) */\r
-#define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */\r
-#define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */\r
-#define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */\r
-#define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */\r
-#define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */\r
-#define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */\r
-#define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */\r
-#define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */\r
-\r
-#define FSMC_PIO4_IOWAIT4_Pos (8U) \r
-#define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */\r
-#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */\r
-#define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */\r
-#define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */\r
-#define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */\r
-#define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */\r
-#define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */\r
-#define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */\r
-#define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */\r
-#define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */\r
-\r
-#define FSMC_PIO4_IOHOLD4_Pos (16U) \r
-#define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */\r
-#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */\r
-#define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */\r
-#define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */\r
-#define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */\r
-#define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */\r
-#define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */\r
-#define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */\r
-#define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */\r
-#define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */\r
-\r
-#define FSMC_PIO4_IOHIZ4_Pos (24U) \r
-#define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */\r
-#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
-#define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */\r
-#define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */\r
-#define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */\r
-#define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */\r
-#define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */\r
-#define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */\r
-#define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */\r
-#define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */\r
-\r
-/****************** Bit definition for FSMC_ECCR2 register ******************/\r
-#define FSMC_ECCR2_ECC2_Pos (0U) \r
-#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */\r
-#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!< ECC result */\r
-\r
-/****************** Bit definition for FSMC_ECCR3 register ******************/\r
-#define FSMC_ECCR3_ECC3_Pos (0U) \r
-#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */\r
-#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!< ECC result */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* SD host Interface */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/****************** Bit definition for SDIO_POWER register ******************/\r
-#define SDIO_POWER_PWRCTRL_Pos (0U) \r
-#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */\r
-#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */\r
-#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */\r
-#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */\r
-\r
-/****************** Bit definition for SDIO_CLKCR register ******************/\r
-#define SDIO_CLKCR_CLKDIV_Pos (0U) \r
-#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */\r
-#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */\r
-#define SDIO_CLKCR_CLKEN_Pos (8U) \r
-#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */\r
-#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */\r
-#define SDIO_CLKCR_PWRSAV_Pos (9U) \r
-#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */\r
-#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */\r
-#define SDIO_CLKCR_BYPASS_Pos (10U) \r
-#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */\r
-#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */\r
-\r
-#define SDIO_CLKCR_WIDBUS_Pos (11U) \r
-#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */\r
-#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
-#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */\r
-#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */\r
-\r
-#define SDIO_CLKCR_NEGEDGE_Pos (13U) \r
-#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */\r
-#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */\r
-#define SDIO_CLKCR_HWFC_EN_Pos (14U) \r
-#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */\r
-#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */\r
-\r
-/******************* Bit definition for SDIO_ARG register *******************/\r
-#define SDIO_ARG_CMDARG_Pos (0U) \r
-#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */\r
-#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */\r
-\r
-/******************* Bit definition for SDIO_CMD register *******************/\r
-#define SDIO_CMD_CMDINDEX_Pos (0U) \r
-#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */\r
-#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */\r
-\r
-#define SDIO_CMD_WAITRESP_Pos (6U) \r
-#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */\r
-#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */\r
-#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */\r
-#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */\r
-\r
-#define SDIO_CMD_WAITINT_Pos (8U) \r
-#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */\r
-#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */\r
-#define SDIO_CMD_WAITPEND_Pos (9U) \r
-#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */\r
-#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
-#define SDIO_CMD_CPSMEN_Pos (10U) \r
-#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */\r
-#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */\r
-#define SDIO_CMD_SDIOSUSPEND_Pos (11U) \r
-#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */\r
-#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */\r
-#define SDIO_CMD_ENCMDCOMPL_Pos (12U) \r
-#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */\r
-#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */\r
-#define SDIO_CMD_NIEN_Pos (13U) \r
-#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */\r
-#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */\r
-#define SDIO_CMD_CEATACMD_Pos (14U) \r
-#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */\r
-#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */\r
-\r
-/***************** Bit definition for SDIO_RESPCMD register *****************/\r
-#define SDIO_RESPCMD_RESPCMD_Pos (0U) \r
-#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */\r
-#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */\r
-\r
-/****************** Bit definition for SDIO_RESP0 register ******************/\r
-#define SDIO_RESP0_CARDSTATUS0_Pos (0U) \r
-#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\r
-#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP1 register ******************/\r
-#define SDIO_RESP1_CARDSTATUS1_Pos (0U) \r
-#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\r
-#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP2 register ******************/\r
-#define SDIO_RESP2_CARDSTATUS2_Pos (0U) \r
-#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\r
-#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP3 register ******************/\r
-#define SDIO_RESP3_CARDSTATUS3_Pos (0U) \r
-#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\r
-#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP4 register ******************/\r
-#define SDIO_RESP4_CARDSTATUS4_Pos (0U) \r
-#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\r
-#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */\r
-\r
-/****************** Bit definition for SDIO_DTIMER register *****************/\r
-#define SDIO_DTIMER_DATATIME_Pos (0U) \r
-#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\r
-#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */\r
-\r
-/****************** Bit definition for SDIO_DLEN register *******************/\r
-#define SDIO_DLEN_DATALENGTH_Pos (0U) \r
-#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\r
-#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */\r
-\r
-/****************** Bit definition for SDIO_DCTRL register ******************/\r
-#define SDIO_DCTRL_DTEN_Pos (0U) \r
-#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */\r
-#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */\r
-#define SDIO_DCTRL_DTDIR_Pos (1U) \r
-#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */\r
-#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */\r
-#define SDIO_DCTRL_DTMODE_Pos (2U) \r
-#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */\r
-#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */\r
-#define SDIO_DCTRL_DMAEN_Pos (3U) \r
-#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */\r
-#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */\r
-\r
-#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) \r
-#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */\r
-#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */\r
-#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */\r
-#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */\r
-#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */\r
-#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */\r
-\r
-#define SDIO_DCTRL_RWSTART_Pos (8U) \r
-#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */\r
-#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */\r
-#define SDIO_DCTRL_RWSTOP_Pos (9U) \r
-#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */\r
-#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */\r
-#define SDIO_DCTRL_RWMOD_Pos (10U) \r
-#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */\r
-#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */\r
-#define SDIO_DCTRL_SDIOEN_Pos (11U) \r
-#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */\r
-#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */\r
-\r
-/****************** Bit definition for SDIO_DCOUNT register *****************/\r
-#define SDIO_DCOUNT_DATACOUNT_Pos (0U) \r
-#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\r
-#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */\r
-\r
-/****************** Bit definition for SDIO_STA register ********************/\r
-#define SDIO_STA_CCRCFAIL_Pos (0U) \r
-#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */\r
-#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */\r
-#define SDIO_STA_DCRCFAIL_Pos (1U) \r
-#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */\r
-#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */\r
-#define SDIO_STA_CTIMEOUT_Pos (2U) \r
-#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */\r
-#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */\r
-#define SDIO_STA_DTIMEOUT_Pos (3U) \r
-#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */\r
-#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */\r
-#define SDIO_STA_TXUNDERR_Pos (4U) \r
-#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */\r
-#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */\r
-#define SDIO_STA_RXOVERR_Pos (5U) \r
-#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */\r
-#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */\r
-#define SDIO_STA_CMDREND_Pos (6U) \r
-#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */\r
-#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */\r
-#define SDIO_STA_CMDSENT_Pos (7U) \r
-#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */\r
-#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */\r
-#define SDIO_STA_DATAEND_Pos (8U) \r
-#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */\r
-#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */\r
-#define SDIO_STA_STBITERR_Pos (9U) \r
-#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */\r
-#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */\r
-#define SDIO_STA_DBCKEND_Pos (10U) \r
-#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */\r
-#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */\r
-#define SDIO_STA_CMDACT_Pos (11U) \r
-#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */\r
-#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */\r
-#define SDIO_STA_TXACT_Pos (12U) \r
-#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */\r
-#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */\r
-#define SDIO_STA_RXACT_Pos (13U) \r
-#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */\r
-#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */\r
-#define SDIO_STA_TXFIFOHE_Pos (14U) \r
-#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */\r
-#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
-#define SDIO_STA_RXFIFOHF_Pos (15U) \r
-#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */\r
-#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
-#define SDIO_STA_TXFIFOF_Pos (16U) \r
-#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */\r
-#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */\r
-#define SDIO_STA_RXFIFOF_Pos (17U) \r
-#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */\r
-#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */\r
-#define SDIO_STA_TXFIFOE_Pos (18U) \r
-#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */\r
-#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */\r
-#define SDIO_STA_RXFIFOE_Pos (19U) \r
-#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */\r
-#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */\r
-#define SDIO_STA_TXDAVL_Pos (20U) \r
-#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */\r
-#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */\r
-#define SDIO_STA_RXDAVL_Pos (21U) \r
-#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */\r
-#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */\r
-#define SDIO_STA_SDIOIT_Pos (22U) \r
-#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */\r
-#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */\r
-#define SDIO_STA_CEATAEND_Pos (23U) \r
-#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */\r
-#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */\r
-\r
-/******************* Bit definition for SDIO_ICR register *******************/\r
-#define SDIO_ICR_CCRCFAILC_Pos (0U) \r
-#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */\r
-#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */\r
-#define SDIO_ICR_DCRCFAILC_Pos (1U) \r
-#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */\r
-#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */\r
-#define SDIO_ICR_CTIMEOUTC_Pos (2U) \r
-#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */\r
-#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */\r
-#define SDIO_ICR_DTIMEOUTC_Pos (3U) \r
-#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */\r
-#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */\r
-#define SDIO_ICR_TXUNDERRC_Pos (4U) \r
-#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */\r
-#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */\r
-#define SDIO_ICR_RXOVERRC_Pos (5U) \r
-#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */\r
-#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */\r
-#define SDIO_ICR_CMDRENDC_Pos (6U) \r
-#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */\r
-#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */\r
-#define SDIO_ICR_CMDSENTC_Pos (7U) \r
-#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */\r
-#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */\r
-#define SDIO_ICR_DATAENDC_Pos (8U) \r
-#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */\r
-#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */\r
-#define SDIO_ICR_STBITERRC_Pos (9U) \r
-#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */\r
-#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */\r
-#define SDIO_ICR_DBCKENDC_Pos (10U) \r
-#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */\r
-#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */\r
-#define SDIO_ICR_SDIOITC_Pos (22U) \r
-#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */\r
-#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */\r
-#define SDIO_ICR_CEATAENDC_Pos (23U) \r
-#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */\r
-#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */\r
-\r
-/****************** Bit definition for SDIO_MASK register *******************/\r
-#define SDIO_MASK_CCRCFAILIE_Pos (0U) \r
-#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */\r
-#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */\r
-#define SDIO_MASK_DCRCFAILIE_Pos (1U) \r
-#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */\r
-#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */\r
-#define SDIO_MASK_CTIMEOUTIE_Pos (2U) \r
-#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */\r
-#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */\r
-#define SDIO_MASK_DTIMEOUTIE_Pos (3U) \r
-#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */\r
-#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */\r
-#define SDIO_MASK_TXUNDERRIE_Pos (4U) \r
-#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */\r
-#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */\r
-#define SDIO_MASK_RXOVERRIE_Pos (5U) \r
-#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */\r
-#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */\r
-#define SDIO_MASK_CMDRENDIE_Pos (6U) \r
-#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */\r
-#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */\r
-#define SDIO_MASK_CMDSENTIE_Pos (7U) \r
-#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */\r
-#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */\r
-#define SDIO_MASK_DATAENDIE_Pos (8U) \r
-#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */\r
-#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */\r
-#define SDIO_MASK_STBITERRIE_Pos (9U) \r
-#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */\r
-#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */\r
-#define SDIO_MASK_DBCKENDIE_Pos (10U) \r
-#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */\r
-#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */\r
-#define SDIO_MASK_CMDACTIE_Pos (11U) \r
-#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */\r
-#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */\r
-#define SDIO_MASK_TXACTIE_Pos (12U) \r
-#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */\r
-#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */\r
-#define SDIO_MASK_RXACTIE_Pos (13U) \r
-#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */\r
-#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */\r
-#define SDIO_MASK_TXFIFOHEIE_Pos (14U) \r
-#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */\r
-#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */\r
-#define SDIO_MASK_RXFIFOHFIE_Pos (15U) \r
-#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */\r
-#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */\r
-#define SDIO_MASK_TXFIFOFIE_Pos (16U) \r
-#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */\r
-#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */\r
-#define SDIO_MASK_RXFIFOFIE_Pos (17U) \r
-#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */\r
-#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */\r
-#define SDIO_MASK_TXFIFOEIE_Pos (18U) \r
-#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */\r
-#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */\r
-#define SDIO_MASK_RXFIFOEIE_Pos (19U) \r
-#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */\r
-#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */\r
-#define SDIO_MASK_TXDAVLIE_Pos (20U) \r
-#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */\r
-#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */\r
-#define SDIO_MASK_RXDAVLIE_Pos (21U) \r
-#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */\r
-#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */\r
-#define SDIO_MASK_SDIOITIE_Pos (22U) \r
-#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */\r
-#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */\r
-#define SDIO_MASK_CEATAENDIE_Pos (23U) \r
-#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */\r
-#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */\r
-\r
-/***************** Bit definition for SDIO_FIFOCNT register *****************/\r
-#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) \r
-#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\r
-#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */\r
-\r
-/****************** Bit definition for SDIO_FIFO register *******************/\r
-#define SDIO_FIFO_FIFODATA_Pos (0U) \r
-#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\r
-#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* USB Device FS */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/*!< Endpoint-specific registers */\r
-#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */\r
-#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */\r
-#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */\r
-#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */\r
-#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */\r
-#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */\r
-#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */\r
-#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */\r
-\r
-/* bit positions */ \r
-#define USB_EP_CTR_RX_Pos (15U) \r
-#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */\r
-#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */\r
-#define USB_EP_DTOG_RX_Pos (14U) \r
-#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */\r
-#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */\r
-#define USB_EPRX_STAT_Pos (12U) \r
-#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */\r
-#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */\r
-#define USB_EP_SETUP_Pos (11U) \r
-#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */\r
-#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */\r
-#define USB_EP_T_FIELD_Pos (9U) \r
-#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */\r
-#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */\r
-#define USB_EP_KIND_Pos (8U) \r
-#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */\r
-#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */\r
-#define USB_EP_CTR_TX_Pos (7U) \r
-#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */\r
-#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */\r
-#define USB_EP_DTOG_TX_Pos (6U) \r
-#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */\r
-#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */\r
-#define USB_EPTX_STAT_Pos (4U) \r
-#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */\r
-#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */\r
-#define USB_EPADDR_FIELD_Pos (0U) \r
-#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */\r
-#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */\r
-\r
-/* EndPoint REGister MASK (no toggle fields) */\r
-#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)\r
- /*!< EP_TYPE[1:0] EndPoint TYPE */\r
-#define USB_EP_TYPE_MASK_Pos (9U) \r
-#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */\r
-#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */\r
-#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */\r
-#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */\r
-#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */\r
-#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */\r
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)\r
-\r
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */\r
- /*!< STAT_TX[1:0] STATus for TX transfer */\r
-#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */\r
-#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */\r
-#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */\r
-#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */\r
-#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */\r
-#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */\r
-#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)\r
- /*!< STAT_RX[1:0] STATus for RX transfer */\r
-#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */\r
-#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */\r
-#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */\r
-#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */\r
-#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */\r
-#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */\r
-#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)\r
-\r
-/******************* Bit definition for USB_EP0R register *******************/\r
-#define USB_EP0R_EA_Pos (0U) \r
-#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */\r
-#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */\r
-\r
-#define USB_EP0R_STAT_TX_Pos (4U) \r
-#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */\r
-#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */\r
-#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */\r
-\r
-#define USB_EP0R_DTOG_TX_Pos (6U) \r
-#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */\r
-#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */\r
-#define USB_EP0R_CTR_TX_Pos (7U) \r
-#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */\r
-#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */\r
-#define USB_EP0R_EP_KIND_Pos (8U) \r
-#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */\r
-#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */\r
- \r
-#define USB_EP0R_EP_TYPE_Pos (9U) \r
-#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */\r
-#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */\r
-#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */\r
-\r
-#define USB_EP0R_SETUP_Pos (11U) \r
-#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */\r
-#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */\r
-\r
-#define USB_EP0R_STAT_RX_Pos (12U) \r
-#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */\r
-#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */\r
-#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */\r
-\r
-#define USB_EP0R_DTOG_RX_Pos (14U) \r
-#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */\r
-#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */\r
-#define USB_EP0R_CTR_RX_Pos (15U) \r
-#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */\r
-#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP1R register *******************/\r
-#define USB_EP1R_EA_Pos (0U) \r
-#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */\r
-#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */\r
- \r
-#define USB_EP1R_STAT_TX_Pos (4U) \r
-#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */\r
-#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */\r
-#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */\r
-\r
-#define USB_EP1R_DTOG_TX_Pos (6U) \r
-#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */\r
-#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */\r
-#define USB_EP1R_CTR_TX_Pos (7U) \r
-#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */\r
-#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */\r
-#define USB_EP1R_EP_KIND_Pos (8U) \r
-#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */\r
-#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */\r
-\r
-#define USB_EP1R_EP_TYPE_Pos (9U) \r
-#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */\r
-#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */\r
-#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */\r
-\r
-#define USB_EP1R_SETUP_Pos (11U) \r
-#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */\r
-#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */\r
- \r
-#define USB_EP1R_STAT_RX_Pos (12U) \r
-#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */\r
-#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */\r
-#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */\r
-\r
-#define USB_EP1R_DTOG_RX_Pos (14U) \r
-#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */\r
-#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */\r
-#define USB_EP1R_CTR_RX_Pos (15U) \r
-#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */\r
-#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP2R register *******************/\r
-#define USB_EP2R_EA_Pos (0U) \r
-#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */\r
-#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */\r
-\r
-#define USB_EP2R_STAT_TX_Pos (4U) \r
-#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */\r
-#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */\r
-#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */\r
-\r
-#define USB_EP2R_DTOG_TX_Pos (6U) \r
-#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */\r
-#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */\r
-#define USB_EP2R_CTR_TX_Pos (7U) \r
-#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */\r
-#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */\r
-#define USB_EP2R_EP_KIND_Pos (8U) \r
-#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */\r
-#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */\r
-\r
-#define USB_EP2R_EP_TYPE_Pos (9U) \r
-#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */\r
-#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */\r
-#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */\r
-\r
-#define USB_EP2R_SETUP_Pos (11U) \r
-#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */\r
-#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */\r
-\r
-#define USB_EP2R_STAT_RX_Pos (12U) \r
-#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */\r
-#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */\r
-#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */\r
-\r
-#define USB_EP2R_DTOG_RX_Pos (14U) \r
-#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */\r
-#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */\r
-#define USB_EP2R_CTR_RX_Pos (15U) \r
-#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */\r
-#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP3R register *******************/\r
-#define USB_EP3R_EA_Pos (0U) \r
-#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */\r
-#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */\r
-\r
-#define USB_EP3R_STAT_TX_Pos (4U) \r
-#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */\r
-#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */\r
-#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */\r
-\r
-#define USB_EP3R_DTOG_TX_Pos (6U) \r
-#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */\r
-#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */\r
-#define USB_EP3R_CTR_TX_Pos (7U) \r
-#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */\r
-#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */\r
-#define USB_EP3R_EP_KIND_Pos (8U) \r
-#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */\r
-#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */\r
-\r
-#define USB_EP3R_EP_TYPE_Pos (9U) \r
-#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */\r
-#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */\r
-#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */\r
-\r
-#define USB_EP3R_SETUP_Pos (11U) \r
-#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */\r
-#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */\r
-\r
-#define USB_EP3R_STAT_RX_Pos (12U) \r
-#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */\r
-#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */\r
-#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */\r
-\r
-#define USB_EP3R_DTOG_RX_Pos (14U) \r
-#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */\r
-#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */\r
-#define USB_EP3R_CTR_RX_Pos (15U) \r
-#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */\r
-#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP4R register *******************/\r
-#define USB_EP4R_EA_Pos (0U) \r
-#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */\r
-#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */\r
-\r
-#define USB_EP4R_STAT_TX_Pos (4U) \r
-#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */\r
-#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */\r
-#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */\r
-\r
-#define USB_EP4R_DTOG_TX_Pos (6U) \r
-#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */\r
-#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */\r
-#define USB_EP4R_CTR_TX_Pos (7U) \r
-#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */\r
-#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */\r
-#define USB_EP4R_EP_KIND_Pos (8U) \r
-#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */\r
-#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */\r
-\r
-#define USB_EP4R_EP_TYPE_Pos (9U) \r
-#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */\r
-#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */\r
-#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */\r
-\r
-#define USB_EP4R_SETUP_Pos (11U) \r
-#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */\r
-#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */\r
-\r
-#define USB_EP4R_STAT_RX_Pos (12U) \r
-#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */\r
-#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */\r
-#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */\r
-\r
-#define USB_EP4R_DTOG_RX_Pos (14U) \r
-#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */\r
-#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */\r
-#define USB_EP4R_CTR_RX_Pos (15U) \r
-#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */\r
-#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP5R register *******************/\r
-#define USB_EP5R_EA_Pos (0U) \r
-#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */\r
-#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */\r
-\r
-#define USB_EP5R_STAT_TX_Pos (4U) \r
-#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */\r
-#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */\r
-#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */\r
-\r
-#define USB_EP5R_DTOG_TX_Pos (6U) \r
-#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */\r
-#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */\r
-#define USB_EP5R_CTR_TX_Pos (7U) \r
-#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */\r
-#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */\r
-#define USB_EP5R_EP_KIND_Pos (8U) \r
-#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */\r
-#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */\r
-\r
-#define USB_EP5R_EP_TYPE_Pos (9U) \r
-#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */\r
-#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */\r
-#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */\r
-\r
-#define USB_EP5R_SETUP_Pos (11U) \r
-#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */\r
-#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */\r
-\r
-#define USB_EP5R_STAT_RX_Pos (12U) \r
-#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */\r
-#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */\r
-#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */\r
-\r
-#define USB_EP5R_DTOG_RX_Pos (14U) \r
-#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */\r
-#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */\r
-#define USB_EP5R_CTR_RX_Pos (15U) \r
-#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */\r
-#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP6R register *******************/\r
-#define USB_EP6R_EA_Pos (0U) \r
-#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */\r
-#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */\r
-\r
-#define USB_EP6R_STAT_TX_Pos (4U) \r
-#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */\r
-#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */\r
-#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */\r
-\r
-#define USB_EP6R_DTOG_TX_Pos (6U) \r
-#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */\r
-#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */\r
-#define USB_EP6R_CTR_TX_Pos (7U) \r
-#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */\r
-#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */\r
-#define USB_EP6R_EP_KIND_Pos (8U) \r
-#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */\r
-#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */\r
-\r
-#define USB_EP6R_EP_TYPE_Pos (9U) \r
-#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */\r
-#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */\r
-#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */\r
-\r
-#define USB_EP6R_SETUP_Pos (11U) \r
-#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */\r
-#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */\r
-\r
-#define USB_EP6R_STAT_RX_Pos (12U) \r
-#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */\r
-#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */\r
-#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */\r
-\r
-#define USB_EP6R_DTOG_RX_Pos (14U) \r
-#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */\r
-#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */\r
-#define USB_EP6R_CTR_RX_Pos (15U) \r
-#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */\r
-#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */\r
-\r
-/******************* Bit definition for USB_EP7R register *******************/\r
-#define USB_EP7R_EA_Pos (0U) \r
-#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */\r
-#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */\r
-\r
-#define USB_EP7R_STAT_TX_Pos (4U) \r
-#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */\r
-#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
-#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */\r
-#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */\r
-\r
-#define USB_EP7R_DTOG_TX_Pos (6U) \r
-#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */\r
-#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */\r
-#define USB_EP7R_CTR_TX_Pos (7U) \r
-#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */\r
-#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */\r
-#define USB_EP7R_EP_KIND_Pos (8U) \r
-#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */\r
-#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */\r
-\r
-#define USB_EP7R_EP_TYPE_Pos (9U) \r
-#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */\r
-#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */\r
-#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */\r
-#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */\r
-\r
-#define USB_EP7R_SETUP_Pos (11U) \r
-#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */\r
-#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */\r
-\r
-#define USB_EP7R_STAT_RX_Pos (12U) \r
-#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */\r
-#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
-#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */\r
-#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */\r
-\r
-#define USB_EP7R_DTOG_RX_Pos (14U) \r
-#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */\r
-#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */\r
-#define USB_EP7R_CTR_RX_Pos (15U) \r
-#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */\r
-#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */\r
-\r
-/*!< Common registers */\r
-/******************* Bit definition for USB_CNTR register *******************/\r
-#define USB_CNTR_FRES_Pos (0U) \r
-#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */\r
-#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */\r
-#define USB_CNTR_PDWN_Pos (1U) \r
-#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */\r
-#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */\r
-#define USB_CNTR_LP_MODE_Pos (2U) \r
-#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */\r
-#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */\r
-#define USB_CNTR_FSUSP_Pos (3U) \r
-#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */\r
-#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */\r
-#define USB_CNTR_RESUME_Pos (4U) \r
-#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */\r
-#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */\r
-#define USB_CNTR_ESOFM_Pos (8U) \r
-#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */\r
-#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */\r
-#define USB_CNTR_SOFM_Pos (9U) \r
-#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */\r
-#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */\r
-#define USB_CNTR_RESETM_Pos (10U) \r
-#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */\r
-#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */\r
-#define USB_CNTR_SUSPM_Pos (11U) \r
-#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */\r
-#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */\r
-#define USB_CNTR_WKUPM_Pos (12U) \r
-#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */\r
-#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */\r
-#define USB_CNTR_ERRM_Pos (13U) \r
-#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */\r
-#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */\r
-#define USB_CNTR_PMAOVRM_Pos (14U) \r
-#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */\r
-#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */\r
-#define USB_CNTR_CTRM_Pos (15U) \r
-#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */\r
-#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */\r
-\r
-/******************* Bit definition for USB_ISTR register *******************/\r
-#define USB_ISTR_EP_ID_Pos (0U) \r
-#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */\r
-#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */\r
-#define USB_ISTR_DIR_Pos (4U) \r
-#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */\r
-#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */\r
-#define USB_ISTR_ESOF_Pos (8U) \r
-#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */\r
-#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */\r
-#define USB_ISTR_SOF_Pos (9U) \r
-#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */\r
-#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */\r
-#define USB_ISTR_RESET_Pos (10U) \r
-#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */\r
-#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */\r
-#define USB_ISTR_SUSP_Pos (11U) \r
-#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */\r
-#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */\r
-#define USB_ISTR_WKUP_Pos (12U) \r
-#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */\r
-#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */\r
-#define USB_ISTR_ERR_Pos (13U) \r
-#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */\r
-#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */\r
-#define USB_ISTR_PMAOVR_Pos (14U) \r
-#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */\r
-#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */\r
-#define USB_ISTR_CTR_Pos (15U) \r
-#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */\r
-#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */\r
-\r
-/******************* Bit definition for USB_FNR register ********************/\r
-#define USB_FNR_FN_Pos (0U) \r
-#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */\r
-#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */\r
-#define USB_FNR_LSOF_Pos (11U) \r
-#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */\r
-#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */\r
-#define USB_FNR_LCK_Pos (13U) \r
-#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */\r
-#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */\r
-#define USB_FNR_RXDM_Pos (14U) \r
-#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */\r
-#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */\r
-#define USB_FNR_RXDP_Pos (15U) \r
-#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */\r
-#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */\r
-\r
-/****************** Bit definition for USB_DADDR register *******************/\r
-#define USB_DADDR_ADD_Pos (0U) \r
-#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */\r
-#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */\r
-#define USB_DADDR_ADD0_Pos (0U) \r
-#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */\r
-#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */\r
-#define USB_DADDR_ADD1_Pos (1U) \r
-#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */\r
-#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */\r
-#define USB_DADDR_ADD2_Pos (2U) \r
-#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */\r
-#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */\r
-#define USB_DADDR_ADD3_Pos (3U) \r
-#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */\r
-#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */\r
-#define USB_DADDR_ADD4_Pos (4U) \r
-#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */\r
-#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */\r
-#define USB_DADDR_ADD5_Pos (5U) \r
-#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */\r
-#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */\r
-#define USB_DADDR_ADD6_Pos (6U) \r
-#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */\r
-#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */\r
-\r
-#define USB_DADDR_EF_Pos (7U) \r
-#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */\r
-#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */\r
-\r
-/****************** Bit definition for USB_BTABLE register ******************/ \r
-#define USB_BTABLE_BTABLE_Pos (3U) \r
-#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */\r
-#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */\r
-\r
-/*!< Buffer descriptor table */\r
-/***************** Bit definition for USB_ADDR0_TX register *****************/\r
-#define USB_ADDR0_TX_ADDR0_TX_Pos (1U) \r
-#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */\r
-\r
-/***************** Bit definition for USB_ADDR1_TX register *****************/\r
-#define USB_ADDR1_TX_ADDR1_TX_Pos (1U) \r
-#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */\r
-\r
-/***************** Bit definition for USB_ADDR2_TX register *****************/\r
-#define USB_ADDR2_TX_ADDR2_TX_Pos (1U) \r
-#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */\r
-\r
-/***************** Bit definition for USB_ADDR3_TX register *****************/\r
-#define USB_ADDR3_TX_ADDR3_TX_Pos (1U) \r
-#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */\r
-\r
-/***************** Bit definition for USB_ADDR4_TX register *****************/\r
-#define USB_ADDR4_TX_ADDR4_TX_Pos (1U) \r
-#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */\r
-\r
-/***************** Bit definition for USB_ADDR5_TX register *****************/\r
-#define USB_ADDR5_TX_ADDR5_TX_Pos (1U) \r
-#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */\r
-\r
-/***************** Bit definition for USB_ADDR6_TX register *****************/\r
-#define USB_ADDR6_TX_ADDR6_TX_Pos (1U) \r
-#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */\r
-\r
-/***************** Bit definition for USB_ADDR7_TX register *****************/\r
-#define USB_ADDR7_TX_ADDR7_TX_Pos (1U) \r
-#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/***************** Bit definition for USB_COUNT0_TX register ****************/\r
-#define USB_COUNT0_TX_COUNT0_TX_Pos (0U) \r
-#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */\r
-\r
-/***************** Bit definition for USB_COUNT1_TX register ****************/\r
-#define USB_COUNT1_TX_COUNT1_TX_Pos (0U) \r
-#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */\r
-\r
-/***************** Bit definition for USB_COUNT2_TX register ****************/\r
-#define USB_COUNT2_TX_COUNT2_TX_Pos (0U) \r
-#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */\r
-\r
-/***************** Bit definition for USB_COUNT3_TX register ****************/\r
-#define USB_COUNT3_TX_COUNT3_TX_Pos (0U) \r
-#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */\r
-\r
-/***************** Bit definition for USB_COUNT4_TX register ****************/\r
-#define USB_COUNT4_TX_COUNT4_TX_Pos (0U) \r
-#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */\r
-\r
-/***************** Bit definition for USB_COUNT5_TX register ****************/\r
-#define USB_COUNT5_TX_COUNT5_TX_Pos (0U) \r
-#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */\r
-\r
-/***************** Bit definition for USB_COUNT6_TX register ****************/\r
-#define USB_COUNT6_TX_COUNT6_TX_Pos (0U) \r
-#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */\r
-\r
-/***************** Bit definition for USB_COUNT7_TX register ****************/\r
-#define USB_COUNT7_TX_COUNT7_TX_Pos (0U) \r
-#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/**************** Bit definition for USB_COUNT0_TX_0 register ***************/\r
-#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT0_TX_1 register ***************/\r
-#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT1_TX_0 register ***************/\r
-#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT1_TX_1 register ***************/\r
-#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT2_TX_0 register ***************/\r
-#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT2_TX_1 register ***************/\r
-#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT3_TX_0 register ***************/\r
-#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT3_TX_1 register ***************/\r
-#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT4_TX_0 register ***************/\r
-#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT4_TX_1 register ***************/\r
-#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT5_TX_0 register ***************/\r
-#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT5_TX_1 register ***************/\r
-#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT6_TX_0 register ***************/\r
-#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT6_TX_1 register ***************/\r
-#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */\r
-\r
-/**************** Bit definition for USB_COUNT7_TX_0 register ***************/\r
-#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */\r
-\r
-/**************** Bit definition for USB_COUNT7_TX_1 register ***************/\r
-#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/***************** Bit definition for USB_ADDR0_RX register *****************/\r
-#define USB_ADDR0_RX_ADDR0_RX_Pos (1U) \r
-#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */\r
-\r
-/***************** Bit definition for USB_ADDR1_RX register *****************/\r
-#define USB_ADDR1_RX_ADDR1_RX_Pos (1U) \r
-#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */\r
-\r
-/***************** Bit definition for USB_ADDR2_RX register *****************/\r
-#define USB_ADDR2_RX_ADDR2_RX_Pos (1U) \r
-#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */\r
-\r
-/***************** Bit definition for USB_ADDR3_RX register *****************/\r
-#define USB_ADDR3_RX_ADDR3_RX_Pos (1U) \r
-#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */\r
-\r
-/***************** Bit definition for USB_ADDR4_RX register *****************/\r
-#define USB_ADDR4_RX_ADDR4_RX_Pos (1U) \r
-#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */\r
-\r
-/***************** Bit definition for USB_ADDR5_RX register *****************/\r
-#define USB_ADDR5_RX_ADDR5_RX_Pos (1U) \r
-#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */\r
-\r
-/***************** Bit definition for USB_ADDR6_RX register *****************/\r
-#define USB_ADDR6_RX_ADDR6_RX_Pos (1U) \r
-#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */\r
-\r
-/***************** Bit definition for USB_ADDR7_RX register *****************/\r
-#define USB_ADDR7_RX_ADDR7_RX_Pos (1U) \r
-#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */\r
-#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/***************** Bit definition for USB_COUNT0_RX register ****************/\r
-#define USB_COUNT0_RX_COUNT0_RX_Pos (0U) \r
-#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) \r
-#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
-#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
-#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
-\r
-#define USB_COUNT0_RX_BLSIZE_Pos (15U) \r
-#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
-#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT1_RX register ****************/\r
-#define USB_COUNT1_RX_COUNT1_RX_Pos (0U) \r
-#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) \r
-#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
-#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
-#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
-\r
-#define USB_COUNT1_RX_BLSIZE_Pos (15U) \r
-#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
-#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT2_RX register ****************/\r
-#define USB_COUNT2_RX_COUNT2_RX_Pos (0U) \r
-#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) \r
-#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
-#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
-#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
-\r
-#define USB_COUNT2_RX_BLSIZE_Pos (15U) \r
-#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
-#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT3_RX register ****************/\r
-#define USB_COUNT3_RX_COUNT3_RX_Pos (0U) \r
-#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) \r
-#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
-#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
-#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
-\r
-#define USB_COUNT3_RX_BLSIZE_Pos (15U) \r
-#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
-#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT4_RX register ****************/\r
-#define USB_COUNT4_RX_COUNT4_RX_Pos (0U) \r
-#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) \r
-#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
-#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
-#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
-\r
-#define USB_COUNT4_RX_BLSIZE_Pos (15U) \r
-#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
-#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT5_RX register ****************/\r
-#define USB_COUNT5_RX_COUNT5_RX_Pos (0U) \r
-#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) \r
-#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
-#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
-#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
-\r
-#define USB_COUNT5_RX_BLSIZE_Pos (15U) \r
-#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
-#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT6_RX register ****************/\r
-#define USB_COUNT6_RX_COUNT6_RX_Pos (0U) \r
-#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) \r
-#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
-#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
-#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
-\r
-#define USB_COUNT6_RX_BLSIZE_Pos (15U) \r
-#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
-#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */\r
-\r
-/***************** Bit definition for USB_COUNT7_RX register ****************/\r
-#define USB_COUNT7_RX_COUNT7_RX_Pos (0U) \r
-#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */\r
-#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */\r
-\r
-#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) \r
-#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\r
-#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
-#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\r
-#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\r
-\r
-#define USB_COUNT7_RX_BLSIZE_Pos (15U) \r
-#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */\r
-#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/**************** Bit definition for USB_COUNT0_RX_0 register ***************/\r
-#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */\r
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT0_RX_1 register ***************/\r
-#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */\r
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT1_RX_0 register ***************/\r
-#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */\r
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT1_RX_1 register ***************/\r
-#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */\r
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT2_RX_0 register ***************/\r
-#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */\r
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT2_RX_1 register ***************/\r
-#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */\r
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT3_RX_0 register ***************/\r
-#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */\r
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT3_RX_1 register ***************/\r
-#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */\r
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT4_RX_0 register ***************/\r
-#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */\r
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT4_RX_1 register ***************/\r
-#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */\r
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */\r
-\r
-/**************** Bit definition for USB_COUNT5_RX_0 register ***************/\r
-#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */\r
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT5_RX_1 register ***************/\r
-#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */\r
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */\r
-\r
-/*************** Bit definition for USB_COUNT6_RX_0 register ***************/\r
-#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */\r
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */\r
-\r
-/**************** Bit definition for USB_COUNT6_RX_1 register ***************/\r
-#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */\r
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */\r
-\r
-/*************** Bit definition for USB_COUNT7_RX_0 register ****************/\r
-#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */\r
-\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */\r
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */\r
-\r
-/*************** Bit definition for USB_COUNT7_RX_1 register ****************/\r
-#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */\r
-\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */\r
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */\r
-\r
-#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Controller Area Network */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/*!< CAN control and status registers */\r
-/******************* Bit definition for CAN_MCR register ********************/\r
-#define CAN_MCR_INRQ_Pos (0U) \r
-#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */\r
-#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */\r
-#define CAN_MCR_SLEEP_Pos (1U) \r
-#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */\r
-#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */\r
-#define CAN_MCR_TXFP_Pos (2U) \r
-#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */\r
-#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */\r
-#define CAN_MCR_RFLM_Pos (3U) \r
-#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */\r
-#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */\r
-#define CAN_MCR_NART_Pos (4U) \r
-#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */\r
-#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */\r
-#define CAN_MCR_AWUM_Pos (5U) \r
-#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */\r
-#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */\r
-#define CAN_MCR_ABOM_Pos (6U) \r
-#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */\r
-#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */\r
-#define CAN_MCR_TTCM_Pos (7U) \r
-#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */\r
-#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */\r
-#define CAN_MCR_RESET_Pos (15U) \r
-#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */\r
-#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */\r
-#define CAN_MCR_DBF_Pos (16U) \r
-#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */\r
-#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */\r
-\r
-/******************* Bit definition for CAN_MSR register ********************/\r
-#define CAN_MSR_INAK_Pos (0U) \r
-#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */\r
-#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */\r
-#define CAN_MSR_SLAK_Pos (1U) \r
-#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */\r
-#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */\r
-#define CAN_MSR_ERRI_Pos (2U) \r
-#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */\r
-#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */\r
-#define CAN_MSR_WKUI_Pos (3U) \r
-#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */\r
-#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */\r
-#define CAN_MSR_SLAKI_Pos (4U) \r
-#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */\r
-#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */\r
-#define CAN_MSR_TXM_Pos (8U) \r
-#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */\r
-#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */\r
-#define CAN_MSR_RXM_Pos (9U) \r
-#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */\r
-#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */\r
-#define CAN_MSR_SAMP_Pos (10U) \r
-#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */\r
-#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */\r
-#define CAN_MSR_RX_Pos (11U) \r
-#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */\r
-#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */\r
-\r
-/******************* Bit definition for CAN_TSR register ********************/\r
-#define CAN_TSR_RQCP0_Pos (0U) \r
-#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */\r
-#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */\r
-#define CAN_TSR_TXOK0_Pos (1U) \r
-#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */\r
-#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */\r
-#define CAN_TSR_ALST0_Pos (2U) \r
-#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */\r
-#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */\r
-#define CAN_TSR_TERR0_Pos (3U) \r
-#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */\r
-#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */\r
-#define CAN_TSR_ABRQ0_Pos (7U) \r
-#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */\r
-#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */\r
-#define CAN_TSR_RQCP1_Pos (8U) \r
-#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */\r
-#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */\r
-#define CAN_TSR_TXOK1_Pos (9U) \r
-#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */\r
-#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */\r
-#define CAN_TSR_ALST1_Pos (10U) \r
-#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */\r
-#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */\r
-#define CAN_TSR_TERR1_Pos (11U) \r
-#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */\r
-#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */\r
-#define CAN_TSR_ABRQ1_Pos (15U) \r
-#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */\r
-#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */\r
-#define CAN_TSR_RQCP2_Pos (16U) \r
-#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */\r
-#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */\r
-#define CAN_TSR_TXOK2_Pos (17U) \r
-#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */\r
-#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */\r
-#define CAN_TSR_ALST2_Pos (18U) \r
-#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */\r
-#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */\r
-#define CAN_TSR_TERR2_Pos (19U) \r
-#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */\r
-#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */\r
-#define CAN_TSR_ABRQ2_Pos (23U) \r
-#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */\r
-#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */\r
-#define CAN_TSR_CODE_Pos (24U) \r
-#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */\r
-#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */\r
-\r
-#define CAN_TSR_TME_Pos (26U) \r
-#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */\r
-#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */\r
-#define CAN_TSR_TME0_Pos (26U) \r
-#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */\r
-#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */\r
-#define CAN_TSR_TME1_Pos (27U) \r
-#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */\r
-#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */\r
-#define CAN_TSR_TME2_Pos (28U) \r
-#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */\r
-#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */\r
-\r
-#define CAN_TSR_LOW_Pos (29U) \r
-#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */\r
-#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */\r
-#define CAN_TSR_LOW0_Pos (29U) \r
-#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */\r
-#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */\r
-#define CAN_TSR_LOW1_Pos (30U) \r
-#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */\r
-#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */\r
-#define CAN_TSR_LOW2_Pos (31U) \r
-#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */\r
-#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */\r
-\r
-/******************* Bit definition for CAN_RF0R register *******************/\r
-#define CAN_RF0R_FMP0_Pos (0U) \r
-#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */\r
-#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */\r
-#define CAN_RF0R_FULL0_Pos (3U) \r
-#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */\r
-#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */\r
-#define CAN_RF0R_FOVR0_Pos (4U) \r
-#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */\r
-#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */\r
-#define CAN_RF0R_RFOM0_Pos (5U) \r
-#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */\r
-#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */\r
-\r
-/******************* Bit definition for CAN_RF1R register *******************/\r
-#define CAN_RF1R_FMP1_Pos (0U) \r
-#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */\r
-#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */\r
-#define CAN_RF1R_FULL1_Pos (3U) \r
-#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */\r
-#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */\r
-#define CAN_RF1R_FOVR1_Pos (4U) \r
-#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */\r
-#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */\r
-#define CAN_RF1R_RFOM1_Pos (5U) \r
-#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */\r
-#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */\r
-\r
-/******************** Bit definition for CAN_IER register *******************/\r
-#define CAN_IER_TMEIE_Pos (0U) \r
-#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */\r
-#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */\r
-#define CAN_IER_FMPIE0_Pos (1U) \r
-#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */\r
-#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */\r
-#define CAN_IER_FFIE0_Pos (2U) \r
-#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */\r
-#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */\r
-#define CAN_IER_FOVIE0_Pos (3U) \r
-#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */\r
-#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */\r
-#define CAN_IER_FMPIE1_Pos (4U) \r
-#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */\r
-#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */\r
-#define CAN_IER_FFIE1_Pos (5U) \r
-#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */\r
-#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */\r
-#define CAN_IER_FOVIE1_Pos (6U) \r
-#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */\r
-#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */\r
-#define CAN_IER_EWGIE_Pos (8U) \r
-#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */\r
-#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */\r
-#define CAN_IER_EPVIE_Pos (9U) \r
-#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */\r
-#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */\r
-#define CAN_IER_BOFIE_Pos (10U) \r
-#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */\r
-#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */\r
-#define CAN_IER_LECIE_Pos (11U) \r
-#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */\r
-#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */\r
-#define CAN_IER_ERRIE_Pos (15U) \r
-#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */\r
-#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */\r
-#define CAN_IER_WKUIE_Pos (16U) \r
-#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */\r
-#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */\r
-#define CAN_IER_SLKIE_Pos (17U) \r
-#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */\r
-#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */\r
-\r
-/******************** Bit definition for CAN_ESR register *******************/\r
-#define CAN_ESR_EWGF_Pos (0U) \r
-#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */\r
-#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */\r
-#define CAN_ESR_EPVF_Pos (1U) \r
-#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */\r
-#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */\r
-#define CAN_ESR_BOFF_Pos (2U) \r
-#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */\r
-#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */\r
-\r
-#define CAN_ESR_LEC_Pos (4U) \r
-#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */\r
-#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */\r
-#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */\r
-#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */\r
-#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */\r
-\r
-#define CAN_ESR_TEC_Pos (16U) \r
-#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */\r
-#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */\r
-#define CAN_ESR_REC_Pos (24U) \r
-#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */\r
-#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */\r
-\r
-/******************* Bit definition for CAN_BTR register ********************/\r
-#define CAN_BTR_BRP_Pos (0U) \r
-#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */\r
-#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */\r
-#define CAN_BTR_TS1_Pos (16U) \r
-#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */\r
-#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */\r
-#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */\r
-#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */\r
-#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */\r
-#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */\r
-#define CAN_BTR_TS2_Pos (20U) \r
-#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */\r
-#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */\r
-#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */\r
-#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */\r
-#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */\r
-#define CAN_BTR_SJW_Pos (24U) \r
-#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */\r
-#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */\r
-#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */\r
-#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */\r
-#define CAN_BTR_LBKM_Pos (30U) \r
-#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */\r
-#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */\r
-#define CAN_BTR_SILM_Pos (31U) \r
-#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */\r
-#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */\r
-\r
-/*!< Mailbox registers */\r
-/****************** Bit definition for CAN_TI0R register ********************/\r
-#define CAN_TI0R_TXRQ_Pos (0U) \r
-#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */\r
-#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */\r
-#define CAN_TI0R_RTR_Pos (1U) \r
-#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */\r
-#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */\r
-#define CAN_TI0R_IDE_Pos (2U) \r
-#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */\r
-#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */\r
-#define CAN_TI0R_EXID_Pos (3U) \r
-#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */\r
-#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */\r
-#define CAN_TI0R_STID_Pos (21U) \r
-#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */\r
-#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */\r
-\r
-/****************** Bit definition for CAN_TDT0R register *******************/\r
-#define CAN_TDT0R_DLC_Pos (0U) \r
-#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */\r
-#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */\r
-#define CAN_TDT0R_TGT_Pos (8U) \r
-#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */\r
-#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */\r
-#define CAN_TDT0R_TIME_Pos (16U) \r
-#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */\r
-#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */\r
-\r
-/****************** Bit definition for CAN_TDL0R register *******************/\r
-#define CAN_TDL0R_DATA0_Pos (0U) \r
-#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */\r
-#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */\r
-#define CAN_TDL0R_DATA1_Pos (8U) \r
-#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */\r
-#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */\r
-#define CAN_TDL0R_DATA2_Pos (16U) \r
-#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */\r
-#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */\r
-#define CAN_TDL0R_DATA3_Pos (24U) \r
-#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */\r
-#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */\r
-\r
-/****************** Bit definition for CAN_TDH0R register *******************/\r
-#define CAN_TDH0R_DATA4_Pos (0U) \r
-#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */\r
-#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */\r
-#define CAN_TDH0R_DATA5_Pos (8U) \r
-#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */\r
-#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */\r
-#define CAN_TDH0R_DATA6_Pos (16U) \r
-#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */\r
-#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */\r
-#define CAN_TDH0R_DATA7_Pos (24U) \r
-#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */\r
-#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_TI1R register *******************/\r
-#define CAN_TI1R_TXRQ_Pos (0U) \r
-#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */\r
-#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */\r
-#define CAN_TI1R_RTR_Pos (1U) \r
-#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */\r
-#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */\r
-#define CAN_TI1R_IDE_Pos (2U) \r
-#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */\r
-#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */\r
-#define CAN_TI1R_EXID_Pos (3U) \r
-#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */\r
-#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */\r
-#define CAN_TI1R_STID_Pos (21U) \r
-#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */\r
-#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_TDT1R register ******************/\r
-#define CAN_TDT1R_DLC_Pos (0U) \r
-#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */\r
-#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */\r
-#define CAN_TDT1R_TGT_Pos (8U) \r
-#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */\r
-#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */\r
-#define CAN_TDT1R_TIME_Pos (16U) \r
-#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */\r
-#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_TDL1R register ******************/\r
-#define CAN_TDL1R_DATA0_Pos (0U) \r
-#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */\r
-#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */\r
-#define CAN_TDL1R_DATA1_Pos (8U) \r
-#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */\r
-#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */\r
-#define CAN_TDL1R_DATA2_Pos (16U) \r
-#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */\r
-#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */\r
-#define CAN_TDL1R_DATA3_Pos (24U) \r
-#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */\r
-#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_TDH1R register ******************/\r
-#define CAN_TDH1R_DATA4_Pos (0U) \r
-#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */\r
-#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */\r
-#define CAN_TDH1R_DATA5_Pos (8U) \r
-#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */\r
-#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */\r
-#define CAN_TDH1R_DATA6_Pos (16U) \r
-#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */\r
-#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */\r
-#define CAN_TDH1R_DATA7_Pos (24U) \r
-#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */\r
-#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_TI2R register *******************/\r
-#define CAN_TI2R_TXRQ_Pos (0U) \r
-#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */\r
-#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */\r
-#define CAN_TI2R_RTR_Pos (1U) \r
-#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */\r
-#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */\r
-#define CAN_TI2R_IDE_Pos (2U) \r
-#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */\r
-#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */\r
-#define CAN_TI2R_EXID_Pos (3U) \r
-#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */\r
-#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */\r
-#define CAN_TI2R_STID_Pos (21U) \r
-#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */\r
-#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_TDT2R register ******************/ \r
-#define CAN_TDT2R_DLC_Pos (0U) \r
-#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */\r
-#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */\r
-#define CAN_TDT2R_TGT_Pos (8U) \r
-#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */\r
-#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */\r
-#define CAN_TDT2R_TIME_Pos (16U) \r
-#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */\r
-#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_TDL2R register ******************/\r
-#define CAN_TDL2R_DATA0_Pos (0U) \r
-#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */\r
-#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */\r
-#define CAN_TDL2R_DATA1_Pos (8U) \r
-#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */\r
-#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */\r
-#define CAN_TDL2R_DATA2_Pos (16U) \r
-#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */\r
-#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */\r
-#define CAN_TDL2R_DATA3_Pos (24U) \r
-#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */\r
-#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_TDH2R register ******************/\r
-#define CAN_TDH2R_DATA4_Pos (0U) \r
-#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */\r
-#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */\r
-#define CAN_TDH2R_DATA5_Pos (8U) \r
-#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */\r
-#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */\r
-#define CAN_TDH2R_DATA6_Pos (16U) \r
-#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */\r
-#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */\r
-#define CAN_TDH2R_DATA7_Pos (24U) \r
-#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */\r
-#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_RI0R register *******************/\r
-#define CAN_RI0R_RTR_Pos (1U) \r
-#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */\r
-#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */\r
-#define CAN_RI0R_IDE_Pos (2U) \r
-#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */\r
-#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */\r
-#define CAN_RI0R_EXID_Pos (3U) \r
-#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */\r
-#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */\r
-#define CAN_RI0R_STID_Pos (21U) \r
-#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */\r
-#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_RDT0R register ******************/\r
-#define CAN_RDT0R_DLC_Pos (0U) \r
-#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */\r
-#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */\r
-#define CAN_RDT0R_FMI_Pos (8U) \r
-#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */\r
-#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */\r
-#define CAN_RDT0R_TIME_Pos (16U) \r
-#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */\r
-#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_RDL0R register ******************/\r
-#define CAN_RDL0R_DATA0_Pos (0U) \r
-#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */\r
-#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */\r
-#define CAN_RDL0R_DATA1_Pos (8U) \r
-#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */\r
-#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */\r
-#define CAN_RDL0R_DATA2_Pos (16U) \r
-#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */\r
-#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */\r
-#define CAN_RDL0R_DATA3_Pos (24U) \r
-#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */\r
-#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_RDH0R register ******************/\r
-#define CAN_RDH0R_DATA4_Pos (0U) \r
-#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */\r
-#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */\r
-#define CAN_RDH0R_DATA5_Pos (8U) \r
-#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */\r
-#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */\r
-#define CAN_RDH0R_DATA6_Pos (16U) \r
-#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */\r
-#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */\r
-#define CAN_RDH0R_DATA7_Pos (24U) \r
-#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */\r
-#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_RI1R register *******************/\r
-#define CAN_RI1R_RTR_Pos (1U) \r
-#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */\r
-#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */\r
-#define CAN_RI1R_IDE_Pos (2U) \r
-#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */\r
-#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */\r
-#define CAN_RI1R_EXID_Pos (3U) \r
-#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */\r
-#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */\r
-#define CAN_RI1R_STID_Pos (21U) \r
-#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */\r
-#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_RDT1R register ******************/\r
-#define CAN_RDT1R_DLC_Pos (0U) \r
-#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */\r
-#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */\r
-#define CAN_RDT1R_FMI_Pos (8U) \r
-#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */\r
-#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */\r
-#define CAN_RDT1R_TIME_Pos (16U) \r
-#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */\r
-#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_RDL1R register ******************/\r
-#define CAN_RDL1R_DATA0_Pos (0U) \r
-#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */\r
-#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */\r
-#define CAN_RDL1R_DATA1_Pos (8U) \r
-#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */\r
-#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */\r
-#define CAN_RDL1R_DATA2_Pos (16U) \r
-#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */\r
-#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */\r
-#define CAN_RDL1R_DATA3_Pos (24U) \r
-#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */\r
-#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_RDH1R register ******************/\r
-#define CAN_RDH1R_DATA4_Pos (0U) \r
-#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */\r
-#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */\r
-#define CAN_RDH1R_DATA5_Pos (8U) \r
-#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */\r
-#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */\r
-#define CAN_RDH1R_DATA6_Pos (16U) \r
-#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */\r
-#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */\r
-#define CAN_RDH1R_DATA7_Pos (24U) \r
-#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */\r
-#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */\r
-\r
-/*!< CAN filter registers */\r
-/******************* Bit definition for CAN_FMR register ********************/\r
-#define CAN_FMR_FINIT_Pos (0U) \r
-#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */\r
-#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */\r
-#define CAN_FMR_CAN2SB_Pos (8U) \r
-#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */\r
-#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */\r
-\r
-/******************* Bit definition for CAN_FM1R register *******************/\r
-#define CAN_FM1R_FBM_Pos (0U) \r
-#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */\r
-#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */\r
-#define CAN_FM1R_FBM0_Pos (0U) \r
-#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */\r
-#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */\r
-#define CAN_FM1R_FBM1_Pos (1U) \r
-#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */\r
-#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */\r
-#define CAN_FM1R_FBM2_Pos (2U) \r
-#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */\r
-#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */\r
-#define CAN_FM1R_FBM3_Pos (3U) \r
-#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */\r
-#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */\r
-#define CAN_FM1R_FBM4_Pos (4U) \r
-#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */\r
-#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */\r
-#define CAN_FM1R_FBM5_Pos (5U) \r
-#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */\r
-#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */\r
-#define CAN_FM1R_FBM6_Pos (6U) \r
-#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */\r
-#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */\r
-#define CAN_FM1R_FBM7_Pos (7U) \r
-#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */\r
-#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */\r
-#define CAN_FM1R_FBM8_Pos (8U) \r
-#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */\r
-#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */\r
-#define CAN_FM1R_FBM9_Pos (9U) \r
-#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */\r
-#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */\r
-#define CAN_FM1R_FBM10_Pos (10U) \r
-#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */\r
-#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */\r
-#define CAN_FM1R_FBM11_Pos (11U) \r
-#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */\r
-#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */\r
-#define CAN_FM1R_FBM12_Pos (12U) \r
-#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */\r
-#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */\r
-#define CAN_FM1R_FBM13_Pos (13U) \r
-#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */\r
-#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */\r
-\r
-/******************* Bit definition for CAN_FS1R register *******************/\r
-#define CAN_FS1R_FSC_Pos (0U) \r
-#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */\r
-#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */\r
-#define CAN_FS1R_FSC0_Pos (0U) \r
-#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */\r
-#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */\r
-#define CAN_FS1R_FSC1_Pos (1U) \r
-#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */\r
-#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */\r
-#define CAN_FS1R_FSC2_Pos (2U) \r
-#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */\r
-#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */\r
-#define CAN_FS1R_FSC3_Pos (3U) \r
-#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */\r
-#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */\r
-#define CAN_FS1R_FSC4_Pos (4U) \r
-#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */\r
-#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */\r
-#define CAN_FS1R_FSC5_Pos (5U) \r
-#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */\r
-#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */\r
-#define CAN_FS1R_FSC6_Pos (6U) \r
-#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */\r
-#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */\r
-#define CAN_FS1R_FSC7_Pos (7U) \r
-#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */\r
-#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */\r
-#define CAN_FS1R_FSC8_Pos (8U) \r
-#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */\r
-#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */\r
-#define CAN_FS1R_FSC9_Pos (9U) \r
-#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */\r
-#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */\r
-#define CAN_FS1R_FSC10_Pos (10U) \r
-#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */\r
-#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */\r
-#define CAN_FS1R_FSC11_Pos (11U) \r
-#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */\r
-#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */\r
-#define CAN_FS1R_FSC12_Pos (12U) \r
-#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */\r
-#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */\r
-#define CAN_FS1R_FSC13_Pos (13U) \r
-#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */\r
-#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */\r
-\r
-/****************** Bit definition for CAN_FFA1R register *******************/\r
-#define CAN_FFA1R_FFA_Pos (0U) \r
-#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */\r
-#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */\r
-#define CAN_FFA1R_FFA0_Pos (0U) \r
-#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */\r
-#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */\r
-#define CAN_FFA1R_FFA1_Pos (1U) \r
-#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */\r
-#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */\r
-#define CAN_FFA1R_FFA2_Pos (2U) \r
-#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */\r
-#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */\r
-#define CAN_FFA1R_FFA3_Pos (3U) \r
-#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */\r
-#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */\r
-#define CAN_FFA1R_FFA4_Pos (4U) \r
-#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */\r
-#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */\r
-#define CAN_FFA1R_FFA5_Pos (5U) \r
-#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */\r
-#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */\r
-#define CAN_FFA1R_FFA6_Pos (6U) \r
-#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */\r
-#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */\r
-#define CAN_FFA1R_FFA7_Pos (7U) \r
-#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */\r
-#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */\r
-#define CAN_FFA1R_FFA8_Pos (8U) \r
-#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */\r
-#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */\r
-#define CAN_FFA1R_FFA9_Pos (9U) \r
-#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */\r
-#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */\r
-#define CAN_FFA1R_FFA10_Pos (10U) \r
-#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */\r
-#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */\r
-#define CAN_FFA1R_FFA11_Pos (11U) \r
-#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */\r
-#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */\r
-#define CAN_FFA1R_FFA12_Pos (12U) \r
-#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */\r
-#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */\r
-#define CAN_FFA1R_FFA13_Pos (13U) \r
-#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */\r
-#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */\r
-\r
-/******************* Bit definition for CAN_FA1R register *******************/\r
-#define CAN_FA1R_FACT_Pos (0U) \r
-#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */\r
-#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */\r
-#define CAN_FA1R_FACT0_Pos (0U) \r
-#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */\r
-#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */\r
-#define CAN_FA1R_FACT1_Pos (1U) \r
-#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */\r
-#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */\r
-#define CAN_FA1R_FACT2_Pos (2U) \r
-#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */\r
-#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */\r
-#define CAN_FA1R_FACT3_Pos (3U) \r
-#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */\r
-#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */\r
-#define CAN_FA1R_FACT4_Pos (4U) \r
-#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */\r
-#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */\r
-#define CAN_FA1R_FACT5_Pos (5U) \r
-#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */\r
-#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */\r
-#define CAN_FA1R_FACT6_Pos (6U) \r
-#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */\r
-#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */\r
-#define CAN_FA1R_FACT7_Pos (7U) \r
-#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */\r
-#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */\r
-#define CAN_FA1R_FACT8_Pos (8U) \r
-#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */\r
-#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */\r
-#define CAN_FA1R_FACT9_Pos (9U) \r
-#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */\r
-#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */\r
-#define CAN_FA1R_FACT10_Pos (10U) \r
-#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */\r
-#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */\r
-#define CAN_FA1R_FACT11_Pos (11U) \r
-#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */\r
-#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */\r
-#define CAN_FA1R_FACT12_Pos (12U) \r
-#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */\r
-#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */\r
-#define CAN_FA1R_FACT13_Pos (13U) \r
-#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */\r
-#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */\r
-\r
-/******************* Bit definition for CAN_F0R1 register *******************/\r
-#define CAN_F0R1_FB0_Pos (0U) \r
-#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F0R1_FB1_Pos (1U) \r
-#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F0R1_FB2_Pos (2U) \r
-#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F0R1_FB3_Pos (3U) \r
-#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F0R1_FB4_Pos (4U) \r
-#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F0R1_FB5_Pos (5U) \r
-#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F0R1_FB6_Pos (6U) \r
-#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F0R1_FB7_Pos (7U) \r
-#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F0R1_FB8_Pos (8U) \r
-#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F0R1_FB9_Pos (9U) \r
-#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F0R1_FB10_Pos (10U) \r
-#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F0R1_FB11_Pos (11U) \r
-#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F0R1_FB12_Pos (12U) \r
-#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F0R1_FB13_Pos (13U) \r
-#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F0R1_FB14_Pos (14U) \r
-#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F0R1_FB15_Pos (15U) \r
-#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F0R1_FB16_Pos (16U) \r
-#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F0R1_FB17_Pos (17U) \r
-#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F0R1_FB18_Pos (18U) \r
-#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F0R1_FB19_Pos (19U) \r
-#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F0R1_FB20_Pos (20U) \r
-#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F0R1_FB21_Pos (21U) \r
-#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F0R1_FB22_Pos (22U) \r
-#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F0R1_FB23_Pos (23U) \r
-#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F0R1_FB24_Pos (24U) \r
-#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F0R1_FB25_Pos (25U) \r
-#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F0R1_FB26_Pos (26U) \r
-#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F0R1_FB27_Pos (27U) \r
-#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F0R1_FB28_Pos (28U) \r
-#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F0R1_FB29_Pos (29U) \r
-#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F0R1_FB30_Pos (30U) \r
-#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F0R1_FB31_Pos (31U) \r
-#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F1R1 register *******************/\r
-#define CAN_F1R1_FB0_Pos (0U) \r
-#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F1R1_FB1_Pos (1U) \r
-#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F1R1_FB2_Pos (2U) \r
-#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F1R1_FB3_Pos (3U) \r
-#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F1R1_FB4_Pos (4U) \r
-#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F1R1_FB5_Pos (5U) \r
-#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F1R1_FB6_Pos (6U) \r
-#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F1R1_FB7_Pos (7U) \r
-#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F1R1_FB8_Pos (8U) \r
-#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F1R1_FB9_Pos (9U) \r
-#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F1R1_FB10_Pos (10U) \r
-#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F1R1_FB11_Pos (11U) \r
-#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F1R1_FB12_Pos (12U) \r
-#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F1R1_FB13_Pos (13U) \r
-#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F1R1_FB14_Pos (14U) \r
-#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F1R1_FB15_Pos (15U) \r
-#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F1R1_FB16_Pos (16U) \r
-#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F1R1_FB17_Pos (17U) \r
-#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F1R1_FB18_Pos (18U) \r
-#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F1R1_FB19_Pos (19U) \r
-#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F1R1_FB20_Pos (20U) \r
-#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F1R1_FB21_Pos (21U) \r
-#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F1R1_FB22_Pos (22U) \r
-#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F1R1_FB23_Pos (23U) \r
-#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F1R1_FB24_Pos (24U) \r
-#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F1R1_FB25_Pos (25U) \r
-#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F1R1_FB26_Pos (26U) \r
-#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F1R1_FB27_Pos (27U) \r
-#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F1R1_FB28_Pos (28U) \r
-#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F1R1_FB29_Pos (29U) \r
-#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F1R1_FB30_Pos (30U) \r
-#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F1R1_FB31_Pos (31U) \r
-#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F2R1 register *******************/\r
-#define CAN_F2R1_FB0_Pos (0U) \r
-#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F2R1_FB1_Pos (1U) \r
-#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F2R1_FB2_Pos (2U) \r
-#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F2R1_FB3_Pos (3U) \r
-#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F2R1_FB4_Pos (4U) \r
-#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F2R1_FB5_Pos (5U) \r
-#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F2R1_FB6_Pos (6U) \r
-#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F2R1_FB7_Pos (7U) \r
-#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F2R1_FB8_Pos (8U) \r
-#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F2R1_FB9_Pos (9U) \r
-#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F2R1_FB10_Pos (10U) \r
-#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F2R1_FB11_Pos (11U) \r
-#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F2R1_FB12_Pos (12U) \r
-#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F2R1_FB13_Pos (13U) \r
-#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F2R1_FB14_Pos (14U) \r
-#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F2R1_FB15_Pos (15U) \r
-#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F2R1_FB16_Pos (16U) \r
-#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F2R1_FB17_Pos (17U) \r
-#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F2R1_FB18_Pos (18U) \r
-#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F2R1_FB19_Pos (19U) \r
-#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F2R1_FB20_Pos (20U) \r
-#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F2R1_FB21_Pos (21U) \r
-#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F2R1_FB22_Pos (22U) \r
-#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F2R1_FB23_Pos (23U) \r
-#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F2R1_FB24_Pos (24U) \r
-#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F2R1_FB25_Pos (25U) \r
-#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F2R1_FB26_Pos (26U) \r
-#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F2R1_FB27_Pos (27U) \r
-#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F2R1_FB28_Pos (28U) \r
-#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F2R1_FB29_Pos (29U) \r
-#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F2R1_FB30_Pos (30U) \r
-#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F2R1_FB31_Pos (31U) \r
-#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F3R1 register *******************/\r
-#define CAN_F3R1_FB0_Pos (0U) \r
-#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F3R1_FB1_Pos (1U) \r
-#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F3R1_FB2_Pos (2U) \r
-#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F3R1_FB3_Pos (3U) \r
-#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F3R1_FB4_Pos (4U) \r
-#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F3R1_FB5_Pos (5U) \r
-#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F3R1_FB6_Pos (6U) \r
-#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F3R1_FB7_Pos (7U) \r
-#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F3R1_FB8_Pos (8U) \r
-#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F3R1_FB9_Pos (9U) \r
-#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F3R1_FB10_Pos (10U) \r
-#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F3R1_FB11_Pos (11U) \r
-#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F3R1_FB12_Pos (12U) \r
-#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F3R1_FB13_Pos (13U) \r
-#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F3R1_FB14_Pos (14U) \r
-#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F3R1_FB15_Pos (15U) \r
-#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F3R1_FB16_Pos (16U) \r
-#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F3R1_FB17_Pos (17U) \r
-#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F3R1_FB18_Pos (18U) \r
-#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F3R1_FB19_Pos (19U) \r
-#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F3R1_FB20_Pos (20U) \r
-#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F3R1_FB21_Pos (21U) \r
-#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F3R1_FB22_Pos (22U) \r
-#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F3R1_FB23_Pos (23U) \r
-#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F3R1_FB24_Pos (24U) \r
-#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F3R1_FB25_Pos (25U) \r
-#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F3R1_FB26_Pos (26U) \r
-#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F3R1_FB27_Pos (27U) \r
-#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F3R1_FB28_Pos (28U) \r
-#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F3R1_FB29_Pos (29U) \r
-#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F3R1_FB30_Pos (30U) \r
-#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F3R1_FB31_Pos (31U) \r
-#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F4R1 register *******************/\r
-#define CAN_F4R1_FB0_Pos (0U) \r
-#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F4R1_FB1_Pos (1U) \r
-#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F4R1_FB2_Pos (2U) \r
-#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F4R1_FB3_Pos (3U) \r
-#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F4R1_FB4_Pos (4U) \r
-#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F4R1_FB5_Pos (5U) \r
-#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F4R1_FB6_Pos (6U) \r
-#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F4R1_FB7_Pos (7U) \r
-#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F4R1_FB8_Pos (8U) \r
-#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F4R1_FB9_Pos (9U) \r
-#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F4R1_FB10_Pos (10U) \r
-#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F4R1_FB11_Pos (11U) \r
-#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F4R1_FB12_Pos (12U) \r
-#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F4R1_FB13_Pos (13U) \r
-#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F4R1_FB14_Pos (14U) \r
-#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F4R1_FB15_Pos (15U) \r
-#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F4R1_FB16_Pos (16U) \r
-#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F4R1_FB17_Pos (17U) \r
-#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F4R1_FB18_Pos (18U) \r
-#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F4R1_FB19_Pos (19U) \r
-#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F4R1_FB20_Pos (20U) \r
-#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F4R1_FB21_Pos (21U) \r
-#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F4R1_FB22_Pos (22U) \r
-#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F4R1_FB23_Pos (23U) \r
-#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F4R1_FB24_Pos (24U) \r
-#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F4R1_FB25_Pos (25U) \r
-#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F4R1_FB26_Pos (26U) \r
-#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F4R1_FB27_Pos (27U) \r
-#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F4R1_FB28_Pos (28U) \r
-#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F4R1_FB29_Pos (29U) \r
-#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F4R1_FB30_Pos (30U) \r
-#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F4R1_FB31_Pos (31U) \r
-#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F5R1 register *******************/\r
-#define CAN_F5R1_FB0_Pos (0U) \r
-#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F5R1_FB1_Pos (1U) \r
-#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F5R1_FB2_Pos (2U) \r
-#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F5R1_FB3_Pos (3U) \r
-#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F5R1_FB4_Pos (4U) \r
-#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F5R1_FB5_Pos (5U) \r
-#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F5R1_FB6_Pos (6U) \r
-#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F5R1_FB7_Pos (7U) \r
-#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F5R1_FB8_Pos (8U) \r
-#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F5R1_FB9_Pos (9U) \r
-#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F5R1_FB10_Pos (10U) \r
-#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F5R1_FB11_Pos (11U) \r
-#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F5R1_FB12_Pos (12U) \r
-#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F5R1_FB13_Pos (13U) \r
-#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F5R1_FB14_Pos (14U) \r
-#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F5R1_FB15_Pos (15U) \r
-#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F5R1_FB16_Pos (16U) \r
-#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F5R1_FB17_Pos (17U) \r
-#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F5R1_FB18_Pos (18U) \r
-#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F5R1_FB19_Pos (19U) \r
-#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F5R1_FB20_Pos (20U) \r
-#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F5R1_FB21_Pos (21U) \r
-#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F5R1_FB22_Pos (22U) \r
-#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F5R1_FB23_Pos (23U) \r
-#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F5R1_FB24_Pos (24U) \r
-#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F5R1_FB25_Pos (25U) \r
-#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F5R1_FB26_Pos (26U) \r
-#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F5R1_FB27_Pos (27U) \r
-#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F5R1_FB28_Pos (28U) \r
-#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F5R1_FB29_Pos (29U) \r
-#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F5R1_FB30_Pos (30U) \r
-#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F5R1_FB31_Pos (31U) \r
-#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F6R1 register *******************/\r
-#define CAN_F6R1_FB0_Pos (0U) \r
-#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F6R1_FB1_Pos (1U) \r
-#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F6R1_FB2_Pos (2U) \r
-#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F6R1_FB3_Pos (3U) \r
-#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F6R1_FB4_Pos (4U) \r
-#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F6R1_FB5_Pos (5U) \r
-#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F6R1_FB6_Pos (6U) \r
-#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F6R1_FB7_Pos (7U) \r
-#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F6R1_FB8_Pos (8U) \r
-#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F6R1_FB9_Pos (9U) \r
-#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F6R1_FB10_Pos (10U) \r
-#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F6R1_FB11_Pos (11U) \r
-#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F6R1_FB12_Pos (12U) \r
-#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F6R1_FB13_Pos (13U) \r
-#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F6R1_FB14_Pos (14U) \r
-#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F6R1_FB15_Pos (15U) \r
-#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F6R1_FB16_Pos (16U) \r
-#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F6R1_FB17_Pos (17U) \r
-#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F6R1_FB18_Pos (18U) \r
-#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F6R1_FB19_Pos (19U) \r
-#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F6R1_FB20_Pos (20U) \r
-#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F6R1_FB21_Pos (21U) \r
-#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F6R1_FB22_Pos (22U) \r
-#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F6R1_FB23_Pos (23U) \r
-#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F6R1_FB24_Pos (24U) \r
-#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F6R1_FB25_Pos (25U) \r
-#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F6R1_FB26_Pos (26U) \r
-#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F6R1_FB27_Pos (27U) \r
-#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F6R1_FB28_Pos (28U) \r
-#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F6R1_FB29_Pos (29U) \r
-#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F6R1_FB30_Pos (30U) \r
-#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F6R1_FB31_Pos (31U) \r
-#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F7R1 register *******************/\r
-#define CAN_F7R1_FB0_Pos (0U) \r
-#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F7R1_FB1_Pos (1U) \r
-#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F7R1_FB2_Pos (2U) \r
-#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F7R1_FB3_Pos (3U) \r
-#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F7R1_FB4_Pos (4U) \r
-#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F7R1_FB5_Pos (5U) \r
-#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F7R1_FB6_Pos (6U) \r
-#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F7R1_FB7_Pos (7U) \r
-#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F7R1_FB8_Pos (8U) \r
-#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F7R1_FB9_Pos (9U) \r
-#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F7R1_FB10_Pos (10U) \r
-#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F7R1_FB11_Pos (11U) \r
-#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F7R1_FB12_Pos (12U) \r
-#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F7R1_FB13_Pos (13U) \r
-#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F7R1_FB14_Pos (14U) \r
-#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F7R1_FB15_Pos (15U) \r
-#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F7R1_FB16_Pos (16U) \r
-#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F7R1_FB17_Pos (17U) \r
-#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F7R1_FB18_Pos (18U) \r
-#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F7R1_FB19_Pos (19U) \r
-#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F7R1_FB20_Pos (20U) \r
-#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F7R1_FB21_Pos (21U) \r
-#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F7R1_FB22_Pos (22U) \r
-#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F7R1_FB23_Pos (23U) \r
-#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F7R1_FB24_Pos (24U) \r
-#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F7R1_FB25_Pos (25U) \r
-#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F7R1_FB26_Pos (26U) \r
-#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F7R1_FB27_Pos (27U) \r
-#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F7R1_FB28_Pos (28U) \r
-#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F7R1_FB29_Pos (29U) \r
-#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F7R1_FB30_Pos (30U) \r
-#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F7R1_FB31_Pos (31U) \r
-#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F8R1 register *******************/\r
-#define CAN_F8R1_FB0_Pos (0U) \r
-#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F8R1_FB1_Pos (1U) \r
-#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F8R1_FB2_Pos (2U) \r
-#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F8R1_FB3_Pos (3U) \r
-#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F8R1_FB4_Pos (4U) \r
-#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F8R1_FB5_Pos (5U) \r
-#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F8R1_FB6_Pos (6U) \r
-#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F8R1_FB7_Pos (7U) \r
-#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F8R1_FB8_Pos (8U) \r
-#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F8R1_FB9_Pos (9U) \r
-#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F8R1_FB10_Pos (10U) \r
-#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F8R1_FB11_Pos (11U) \r
-#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F8R1_FB12_Pos (12U) \r
-#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F8R1_FB13_Pos (13U) \r
-#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F8R1_FB14_Pos (14U) \r
-#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F8R1_FB15_Pos (15U) \r
-#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F8R1_FB16_Pos (16U) \r
-#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F8R1_FB17_Pos (17U) \r
-#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F8R1_FB18_Pos (18U) \r
-#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F8R1_FB19_Pos (19U) \r
-#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F8R1_FB20_Pos (20U) \r
-#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F8R1_FB21_Pos (21U) \r
-#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F8R1_FB22_Pos (22U) \r
-#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F8R1_FB23_Pos (23U) \r
-#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F8R1_FB24_Pos (24U) \r
-#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F8R1_FB25_Pos (25U) \r
-#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F8R1_FB26_Pos (26U) \r
-#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F8R1_FB27_Pos (27U) \r
-#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F8R1_FB28_Pos (28U) \r
-#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F8R1_FB29_Pos (29U) \r
-#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F8R1_FB30_Pos (30U) \r
-#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F8R1_FB31_Pos (31U) \r
-#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F9R1 register *******************/\r
-#define CAN_F9R1_FB0_Pos (0U) \r
-#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F9R1_FB1_Pos (1U) \r
-#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F9R1_FB2_Pos (2U) \r
-#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F9R1_FB3_Pos (3U) \r
-#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F9R1_FB4_Pos (4U) \r
-#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F9R1_FB5_Pos (5U) \r
-#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F9R1_FB6_Pos (6U) \r
-#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F9R1_FB7_Pos (7U) \r
-#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F9R1_FB8_Pos (8U) \r
-#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F9R1_FB9_Pos (9U) \r
-#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F9R1_FB10_Pos (10U) \r
-#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F9R1_FB11_Pos (11U) \r
-#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F9R1_FB12_Pos (12U) \r
-#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F9R1_FB13_Pos (13U) \r
-#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F9R1_FB14_Pos (14U) \r
-#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F9R1_FB15_Pos (15U) \r
-#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F9R1_FB16_Pos (16U) \r
-#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F9R1_FB17_Pos (17U) \r
-#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F9R1_FB18_Pos (18U) \r
-#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F9R1_FB19_Pos (19U) \r
-#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F9R1_FB20_Pos (20U) \r
-#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F9R1_FB21_Pos (21U) \r
-#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F9R1_FB22_Pos (22U) \r
-#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F9R1_FB23_Pos (23U) \r
-#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F9R1_FB24_Pos (24U) \r
-#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F9R1_FB25_Pos (25U) \r
-#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F9R1_FB26_Pos (26U) \r
-#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F9R1_FB27_Pos (27U) \r
-#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F9R1_FB28_Pos (28U) \r
-#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F9R1_FB29_Pos (29U) \r
-#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F9R1_FB30_Pos (30U) \r
-#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F9R1_FB31_Pos (31U) \r
-#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F10R1 register ******************/\r
-#define CAN_F10R1_FB0_Pos (0U) \r
-#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F10R1_FB1_Pos (1U) \r
-#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F10R1_FB2_Pos (2U) \r
-#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F10R1_FB3_Pos (3U) \r
-#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F10R1_FB4_Pos (4U) \r
-#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F10R1_FB5_Pos (5U) \r
-#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F10R1_FB6_Pos (6U) \r
-#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F10R1_FB7_Pos (7U) \r
-#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F10R1_FB8_Pos (8U) \r
-#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F10R1_FB9_Pos (9U) \r
-#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F10R1_FB10_Pos (10U) \r
-#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F10R1_FB11_Pos (11U) \r
-#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F10R1_FB12_Pos (12U) \r
-#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F10R1_FB13_Pos (13U) \r
-#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F10R1_FB14_Pos (14U) \r
-#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F10R1_FB15_Pos (15U) \r
-#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F10R1_FB16_Pos (16U) \r
-#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F10R1_FB17_Pos (17U) \r
-#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F10R1_FB18_Pos (18U) \r
-#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F10R1_FB19_Pos (19U) \r
-#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F10R1_FB20_Pos (20U) \r
-#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F10R1_FB21_Pos (21U) \r
-#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F10R1_FB22_Pos (22U) \r
-#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F10R1_FB23_Pos (23U) \r
-#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F10R1_FB24_Pos (24U) \r
-#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F10R1_FB25_Pos (25U) \r
-#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F10R1_FB26_Pos (26U) \r
-#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F10R1_FB27_Pos (27U) \r
-#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F10R1_FB28_Pos (28U) \r
-#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F10R1_FB29_Pos (29U) \r
-#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F10R1_FB30_Pos (30U) \r
-#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F10R1_FB31_Pos (31U) \r
-#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F11R1 register ******************/\r
-#define CAN_F11R1_FB0_Pos (0U) \r
-#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F11R1_FB1_Pos (1U) \r
-#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F11R1_FB2_Pos (2U) \r
-#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F11R1_FB3_Pos (3U) \r
-#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F11R1_FB4_Pos (4U) \r
-#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F11R1_FB5_Pos (5U) \r
-#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F11R1_FB6_Pos (6U) \r
-#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F11R1_FB7_Pos (7U) \r
-#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F11R1_FB8_Pos (8U) \r
-#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F11R1_FB9_Pos (9U) \r
-#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F11R1_FB10_Pos (10U) \r
-#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F11R1_FB11_Pos (11U) \r
-#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F11R1_FB12_Pos (12U) \r
-#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F11R1_FB13_Pos (13U) \r
-#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F11R1_FB14_Pos (14U) \r
-#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F11R1_FB15_Pos (15U) \r
-#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F11R1_FB16_Pos (16U) \r
-#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F11R1_FB17_Pos (17U) \r
-#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F11R1_FB18_Pos (18U) \r
-#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F11R1_FB19_Pos (19U) \r
-#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F11R1_FB20_Pos (20U) \r
-#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F11R1_FB21_Pos (21U) \r
-#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F11R1_FB22_Pos (22U) \r
-#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F11R1_FB23_Pos (23U) \r
-#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F11R1_FB24_Pos (24U) \r
-#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F11R1_FB25_Pos (25U) \r
-#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F11R1_FB26_Pos (26U) \r
-#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F11R1_FB27_Pos (27U) \r
-#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F11R1_FB28_Pos (28U) \r
-#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F11R1_FB29_Pos (29U) \r
-#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F11R1_FB30_Pos (30U) \r
-#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F11R1_FB31_Pos (31U) \r
-#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F12R1 register ******************/\r
-#define CAN_F12R1_FB0_Pos (0U) \r
-#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F12R1_FB1_Pos (1U) \r
-#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F12R1_FB2_Pos (2U) \r
-#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F12R1_FB3_Pos (3U) \r
-#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F12R1_FB4_Pos (4U) \r
-#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F12R1_FB5_Pos (5U) \r
-#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F12R1_FB6_Pos (6U) \r
-#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F12R1_FB7_Pos (7U) \r
-#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F12R1_FB8_Pos (8U) \r
-#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F12R1_FB9_Pos (9U) \r
-#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F12R1_FB10_Pos (10U) \r
-#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F12R1_FB11_Pos (11U) \r
-#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F12R1_FB12_Pos (12U) \r
-#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F12R1_FB13_Pos (13U) \r
-#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F12R1_FB14_Pos (14U) \r
-#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F12R1_FB15_Pos (15U) \r
-#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F12R1_FB16_Pos (16U) \r
-#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F12R1_FB17_Pos (17U) \r
-#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F12R1_FB18_Pos (18U) \r
-#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F12R1_FB19_Pos (19U) \r
-#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F12R1_FB20_Pos (20U) \r
-#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F12R1_FB21_Pos (21U) \r
-#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F12R1_FB22_Pos (22U) \r
-#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F12R1_FB23_Pos (23U) \r
-#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F12R1_FB24_Pos (24U) \r
-#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F12R1_FB25_Pos (25U) \r
-#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F12R1_FB26_Pos (26U) \r
-#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F12R1_FB27_Pos (27U) \r
-#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F12R1_FB28_Pos (28U) \r
-#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F12R1_FB29_Pos (29U) \r
-#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F12R1_FB30_Pos (30U) \r
-#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F12R1_FB31_Pos (31U) \r
-#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F13R1 register ******************/\r
-#define CAN_F13R1_FB0_Pos (0U) \r
-#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F13R1_FB1_Pos (1U) \r
-#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F13R1_FB2_Pos (2U) \r
-#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F13R1_FB3_Pos (3U) \r
-#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F13R1_FB4_Pos (4U) \r
-#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F13R1_FB5_Pos (5U) \r
-#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F13R1_FB6_Pos (6U) \r
-#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F13R1_FB7_Pos (7U) \r
-#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F13R1_FB8_Pos (8U) \r
-#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F13R1_FB9_Pos (9U) \r
-#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F13R1_FB10_Pos (10U) \r
-#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F13R1_FB11_Pos (11U) \r
-#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F13R1_FB12_Pos (12U) \r
-#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F13R1_FB13_Pos (13U) \r
-#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F13R1_FB14_Pos (14U) \r
-#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F13R1_FB15_Pos (15U) \r
-#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F13R1_FB16_Pos (16U) \r
-#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F13R1_FB17_Pos (17U) \r
-#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F13R1_FB18_Pos (18U) \r
-#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F13R1_FB19_Pos (19U) \r
-#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F13R1_FB20_Pos (20U) \r
-#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F13R1_FB21_Pos (21U) \r
-#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F13R1_FB22_Pos (22U) \r
-#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F13R1_FB23_Pos (23U) \r
-#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F13R1_FB24_Pos (24U) \r
-#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F13R1_FB25_Pos (25U) \r
-#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F13R1_FB26_Pos (26U) \r
-#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F13R1_FB27_Pos (27U) \r
-#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F13R1_FB28_Pos (28U) \r
-#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F13R1_FB29_Pos (29U) \r
-#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F13R1_FB30_Pos (30U) \r
-#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F13R1_FB31_Pos (31U) \r
-#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F0R2 register *******************/\r
-#define CAN_F0R2_FB0_Pos (0U) \r
-#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F0R2_FB1_Pos (1U) \r
-#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F0R2_FB2_Pos (2U) \r
-#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F0R2_FB3_Pos (3U) \r
-#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F0R2_FB4_Pos (4U) \r
-#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F0R2_FB5_Pos (5U) \r
-#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F0R2_FB6_Pos (6U) \r
-#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F0R2_FB7_Pos (7U) \r
-#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F0R2_FB8_Pos (8U) \r
-#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F0R2_FB9_Pos (9U) \r
-#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F0R2_FB10_Pos (10U) \r
-#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F0R2_FB11_Pos (11U) \r
-#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F0R2_FB12_Pos (12U) \r
-#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F0R2_FB13_Pos (13U) \r
-#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F0R2_FB14_Pos (14U) \r
-#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F0R2_FB15_Pos (15U) \r
-#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F0R2_FB16_Pos (16U) \r
-#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F0R2_FB17_Pos (17U) \r
-#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F0R2_FB18_Pos (18U) \r
-#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F0R2_FB19_Pos (19U) \r
-#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F0R2_FB20_Pos (20U) \r
-#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F0R2_FB21_Pos (21U) \r
-#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F0R2_FB22_Pos (22U) \r
-#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F0R2_FB23_Pos (23U) \r
-#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F0R2_FB24_Pos (24U) \r
-#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F0R2_FB25_Pos (25U) \r
-#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F0R2_FB26_Pos (26U) \r
-#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F0R2_FB27_Pos (27U) \r
-#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F0R2_FB28_Pos (28U) \r
-#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F0R2_FB29_Pos (29U) \r
-#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F0R2_FB30_Pos (30U) \r
-#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F0R2_FB31_Pos (31U) \r
-#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F1R2 register *******************/\r
-#define CAN_F1R2_FB0_Pos (0U) \r
-#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F1R2_FB1_Pos (1U) \r
-#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F1R2_FB2_Pos (2U) \r
-#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F1R2_FB3_Pos (3U) \r
-#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F1R2_FB4_Pos (4U) \r
-#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F1R2_FB5_Pos (5U) \r
-#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F1R2_FB6_Pos (6U) \r
-#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F1R2_FB7_Pos (7U) \r
-#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F1R2_FB8_Pos (8U) \r
-#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F1R2_FB9_Pos (9U) \r
-#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F1R2_FB10_Pos (10U) \r
-#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F1R2_FB11_Pos (11U) \r
-#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F1R2_FB12_Pos (12U) \r
-#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F1R2_FB13_Pos (13U) \r
-#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F1R2_FB14_Pos (14U) \r
-#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F1R2_FB15_Pos (15U) \r
-#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F1R2_FB16_Pos (16U) \r
-#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F1R2_FB17_Pos (17U) \r
-#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F1R2_FB18_Pos (18U) \r
-#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F1R2_FB19_Pos (19U) \r
-#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F1R2_FB20_Pos (20U) \r
-#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F1R2_FB21_Pos (21U) \r
-#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F1R2_FB22_Pos (22U) \r
-#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F1R2_FB23_Pos (23U) \r
-#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F1R2_FB24_Pos (24U) \r
-#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F1R2_FB25_Pos (25U) \r
-#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F1R2_FB26_Pos (26U) \r
-#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F1R2_FB27_Pos (27U) \r
-#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F1R2_FB28_Pos (28U) \r
-#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F1R2_FB29_Pos (29U) \r
-#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F1R2_FB30_Pos (30U) \r
-#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F1R2_FB31_Pos (31U) \r
-#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F2R2 register *******************/\r
-#define CAN_F2R2_FB0_Pos (0U) \r
-#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F2R2_FB1_Pos (1U) \r
-#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F2R2_FB2_Pos (2U) \r
-#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F2R2_FB3_Pos (3U) \r
-#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F2R2_FB4_Pos (4U) \r
-#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F2R2_FB5_Pos (5U) \r
-#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F2R2_FB6_Pos (6U) \r
-#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F2R2_FB7_Pos (7U) \r
-#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F2R2_FB8_Pos (8U) \r
-#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F2R2_FB9_Pos (9U) \r
-#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F2R2_FB10_Pos (10U) \r
-#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F2R2_FB11_Pos (11U) \r
-#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F2R2_FB12_Pos (12U) \r
-#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F2R2_FB13_Pos (13U) \r
-#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F2R2_FB14_Pos (14U) \r
-#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F2R2_FB15_Pos (15U) \r
-#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F2R2_FB16_Pos (16U) \r
-#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F2R2_FB17_Pos (17U) \r
-#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F2R2_FB18_Pos (18U) \r
-#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F2R2_FB19_Pos (19U) \r
-#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F2R2_FB20_Pos (20U) \r
-#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F2R2_FB21_Pos (21U) \r
-#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F2R2_FB22_Pos (22U) \r
-#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F2R2_FB23_Pos (23U) \r
-#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F2R2_FB24_Pos (24U) \r
-#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F2R2_FB25_Pos (25U) \r
-#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F2R2_FB26_Pos (26U) \r
-#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F2R2_FB27_Pos (27U) \r
-#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F2R2_FB28_Pos (28U) \r
-#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F2R2_FB29_Pos (29U) \r
-#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F2R2_FB30_Pos (30U) \r
-#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F2R2_FB31_Pos (31U) \r
-#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F3R2 register *******************/\r
-#define CAN_F3R2_FB0_Pos (0U) \r
-#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F3R2_FB1_Pos (1U) \r
-#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F3R2_FB2_Pos (2U) \r
-#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F3R2_FB3_Pos (3U) \r
-#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F3R2_FB4_Pos (4U) \r
-#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F3R2_FB5_Pos (5U) \r
-#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F3R2_FB6_Pos (6U) \r
-#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F3R2_FB7_Pos (7U) \r
-#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F3R2_FB8_Pos (8U) \r
-#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F3R2_FB9_Pos (9U) \r
-#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F3R2_FB10_Pos (10U) \r
-#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F3R2_FB11_Pos (11U) \r
-#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F3R2_FB12_Pos (12U) \r
-#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F3R2_FB13_Pos (13U) \r
-#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F3R2_FB14_Pos (14U) \r
-#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F3R2_FB15_Pos (15U) \r
-#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F3R2_FB16_Pos (16U) \r
-#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F3R2_FB17_Pos (17U) \r
-#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F3R2_FB18_Pos (18U) \r
-#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F3R2_FB19_Pos (19U) \r
-#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F3R2_FB20_Pos (20U) \r
-#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F3R2_FB21_Pos (21U) \r
-#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F3R2_FB22_Pos (22U) \r
-#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F3R2_FB23_Pos (23U) \r
-#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F3R2_FB24_Pos (24U) \r
-#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F3R2_FB25_Pos (25U) \r
-#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F3R2_FB26_Pos (26U) \r
-#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F3R2_FB27_Pos (27U) \r
-#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F3R2_FB28_Pos (28U) \r
-#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F3R2_FB29_Pos (29U) \r
-#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F3R2_FB30_Pos (30U) \r
-#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F3R2_FB31_Pos (31U) \r
-#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F4R2 register *******************/\r
-#define CAN_F4R2_FB0_Pos (0U) \r
-#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F4R2_FB1_Pos (1U) \r
-#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F4R2_FB2_Pos (2U) \r
-#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F4R2_FB3_Pos (3U) \r
-#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F4R2_FB4_Pos (4U) \r
-#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F4R2_FB5_Pos (5U) \r
-#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F4R2_FB6_Pos (6U) \r
-#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F4R2_FB7_Pos (7U) \r
-#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F4R2_FB8_Pos (8U) \r
-#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F4R2_FB9_Pos (9U) \r
-#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F4R2_FB10_Pos (10U) \r
-#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F4R2_FB11_Pos (11U) \r
-#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F4R2_FB12_Pos (12U) \r
-#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F4R2_FB13_Pos (13U) \r
-#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F4R2_FB14_Pos (14U) \r
-#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F4R2_FB15_Pos (15U) \r
-#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F4R2_FB16_Pos (16U) \r
-#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F4R2_FB17_Pos (17U) \r
-#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F4R2_FB18_Pos (18U) \r
-#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F4R2_FB19_Pos (19U) \r
-#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F4R2_FB20_Pos (20U) \r
-#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F4R2_FB21_Pos (21U) \r
-#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F4R2_FB22_Pos (22U) \r
-#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F4R2_FB23_Pos (23U) \r
-#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F4R2_FB24_Pos (24U) \r
-#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F4R2_FB25_Pos (25U) \r
-#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F4R2_FB26_Pos (26U) \r
-#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F4R2_FB27_Pos (27U) \r
-#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F4R2_FB28_Pos (28U) \r
-#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F4R2_FB29_Pos (29U) \r
-#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F4R2_FB30_Pos (30U) \r
-#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F4R2_FB31_Pos (31U) \r
-#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F5R2 register *******************/\r
-#define CAN_F5R2_FB0_Pos (0U) \r
-#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F5R2_FB1_Pos (1U) \r
-#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F5R2_FB2_Pos (2U) \r
-#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F5R2_FB3_Pos (3U) \r
-#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F5R2_FB4_Pos (4U) \r
-#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F5R2_FB5_Pos (5U) \r
-#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F5R2_FB6_Pos (6U) \r
-#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F5R2_FB7_Pos (7U) \r
-#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F5R2_FB8_Pos (8U) \r
-#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F5R2_FB9_Pos (9U) \r
-#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F5R2_FB10_Pos (10U) \r
-#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F5R2_FB11_Pos (11U) \r
-#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F5R2_FB12_Pos (12U) \r
-#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F5R2_FB13_Pos (13U) \r
-#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F5R2_FB14_Pos (14U) \r
-#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F5R2_FB15_Pos (15U) \r
-#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F5R2_FB16_Pos (16U) \r
-#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F5R2_FB17_Pos (17U) \r
-#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F5R2_FB18_Pos (18U) \r
-#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F5R2_FB19_Pos (19U) \r
-#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F5R2_FB20_Pos (20U) \r
-#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F5R2_FB21_Pos (21U) \r
-#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F5R2_FB22_Pos (22U) \r
-#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F5R2_FB23_Pos (23U) \r
-#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F5R2_FB24_Pos (24U) \r
-#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F5R2_FB25_Pos (25U) \r
-#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F5R2_FB26_Pos (26U) \r
-#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F5R2_FB27_Pos (27U) \r
-#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F5R2_FB28_Pos (28U) \r
-#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F5R2_FB29_Pos (29U) \r
-#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F5R2_FB30_Pos (30U) \r
-#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F5R2_FB31_Pos (31U) \r
-#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F6R2 register *******************/\r
-#define CAN_F6R2_FB0_Pos (0U) \r
-#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F6R2_FB1_Pos (1U) \r
-#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F6R2_FB2_Pos (2U) \r
-#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F6R2_FB3_Pos (3U) \r
-#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F6R2_FB4_Pos (4U) \r
-#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F6R2_FB5_Pos (5U) \r
-#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F6R2_FB6_Pos (6U) \r
-#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F6R2_FB7_Pos (7U) \r
-#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F6R2_FB8_Pos (8U) \r
-#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F6R2_FB9_Pos (9U) \r
-#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F6R2_FB10_Pos (10U) \r
-#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F6R2_FB11_Pos (11U) \r
-#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F6R2_FB12_Pos (12U) \r
-#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F6R2_FB13_Pos (13U) \r
-#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F6R2_FB14_Pos (14U) \r
-#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F6R2_FB15_Pos (15U) \r
-#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F6R2_FB16_Pos (16U) \r
-#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F6R2_FB17_Pos (17U) \r
-#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F6R2_FB18_Pos (18U) \r
-#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F6R2_FB19_Pos (19U) \r
-#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F6R2_FB20_Pos (20U) \r
-#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F6R2_FB21_Pos (21U) \r
-#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F6R2_FB22_Pos (22U) \r
-#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F6R2_FB23_Pos (23U) \r
-#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F6R2_FB24_Pos (24U) \r
-#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F6R2_FB25_Pos (25U) \r
-#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F6R2_FB26_Pos (26U) \r
-#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F6R2_FB27_Pos (27U) \r
-#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F6R2_FB28_Pos (28U) \r
-#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F6R2_FB29_Pos (29U) \r
-#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F6R2_FB30_Pos (30U) \r
-#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F6R2_FB31_Pos (31U) \r
-#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F7R2 register *******************/\r
-#define CAN_F7R2_FB0_Pos (0U) \r
-#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F7R2_FB1_Pos (1U) \r
-#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F7R2_FB2_Pos (2U) \r
-#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F7R2_FB3_Pos (3U) \r
-#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F7R2_FB4_Pos (4U) \r
-#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F7R2_FB5_Pos (5U) \r
-#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F7R2_FB6_Pos (6U) \r
-#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F7R2_FB7_Pos (7U) \r
-#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F7R2_FB8_Pos (8U) \r
-#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F7R2_FB9_Pos (9U) \r
-#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F7R2_FB10_Pos (10U) \r
-#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F7R2_FB11_Pos (11U) \r
-#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F7R2_FB12_Pos (12U) \r
-#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F7R2_FB13_Pos (13U) \r
-#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F7R2_FB14_Pos (14U) \r
-#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F7R2_FB15_Pos (15U) \r
-#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F7R2_FB16_Pos (16U) \r
-#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F7R2_FB17_Pos (17U) \r
-#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F7R2_FB18_Pos (18U) \r
-#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F7R2_FB19_Pos (19U) \r
-#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F7R2_FB20_Pos (20U) \r
-#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F7R2_FB21_Pos (21U) \r
-#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F7R2_FB22_Pos (22U) \r
-#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F7R2_FB23_Pos (23U) \r
-#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F7R2_FB24_Pos (24U) \r
-#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F7R2_FB25_Pos (25U) \r
-#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F7R2_FB26_Pos (26U) \r
-#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F7R2_FB27_Pos (27U) \r
-#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F7R2_FB28_Pos (28U) \r
-#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F7R2_FB29_Pos (29U) \r
-#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F7R2_FB30_Pos (30U) \r
-#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F7R2_FB31_Pos (31U) \r
-#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F8R2 register *******************/\r
-#define CAN_F8R2_FB0_Pos (0U) \r
-#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F8R2_FB1_Pos (1U) \r
-#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F8R2_FB2_Pos (2U) \r
-#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F8R2_FB3_Pos (3U) \r
-#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F8R2_FB4_Pos (4U) \r
-#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F8R2_FB5_Pos (5U) \r
-#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F8R2_FB6_Pos (6U) \r
-#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F8R2_FB7_Pos (7U) \r
-#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F8R2_FB8_Pos (8U) \r
-#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F8R2_FB9_Pos (9U) \r
-#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F8R2_FB10_Pos (10U) \r
-#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F8R2_FB11_Pos (11U) \r
-#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F8R2_FB12_Pos (12U) \r
-#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F8R2_FB13_Pos (13U) \r
-#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F8R2_FB14_Pos (14U) \r
-#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F8R2_FB15_Pos (15U) \r
-#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F8R2_FB16_Pos (16U) \r
-#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F8R2_FB17_Pos (17U) \r
-#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F8R2_FB18_Pos (18U) \r
-#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F8R2_FB19_Pos (19U) \r
-#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F8R2_FB20_Pos (20U) \r
-#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F8R2_FB21_Pos (21U) \r
-#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F8R2_FB22_Pos (22U) \r
-#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F8R2_FB23_Pos (23U) \r
-#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F8R2_FB24_Pos (24U) \r
-#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F8R2_FB25_Pos (25U) \r
-#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F8R2_FB26_Pos (26U) \r
-#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F8R2_FB27_Pos (27U) \r
-#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F8R2_FB28_Pos (28U) \r
-#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F8R2_FB29_Pos (29U) \r
-#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F8R2_FB30_Pos (30U) \r
-#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F8R2_FB31_Pos (31U) \r
-#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F9R2 register *******************/\r
-#define CAN_F9R2_FB0_Pos (0U) \r
-#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F9R2_FB1_Pos (1U) \r
-#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F9R2_FB2_Pos (2U) \r
-#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F9R2_FB3_Pos (3U) \r
-#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F9R2_FB4_Pos (4U) \r
-#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F9R2_FB5_Pos (5U) \r
-#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F9R2_FB6_Pos (6U) \r
-#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F9R2_FB7_Pos (7U) \r
-#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F9R2_FB8_Pos (8U) \r
-#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F9R2_FB9_Pos (9U) \r
-#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F9R2_FB10_Pos (10U) \r
-#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F9R2_FB11_Pos (11U) \r
-#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F9R2_FB12_Pos (12U) \r
-#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F9R2_FB13_Pos (13U) \r
-#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F9R2_FB14_Pos (14U) \r
-#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F9R2_FB15_Pos (15U) \r
-#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F9R2_FB16_Pos (16U) \r
-#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F9R2_FB17_Pos (17U) \r
-#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F9R2_FB18_Pos (18U) \r
-#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F9R2_FB19_Pos (19U) \r
-#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F9R2_FB20_Pos (20U) \r
-#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F9R2_FB21_Pos (21U) \r
-#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F9R2_FB22_Pos (22U) \r
-#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F9R2_FB23_Pos (23U) \r
-#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F9R2_FB24_Pos (24U) \r
-#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F9R2_FB25_Pos (25U) \r
-#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F9R2_FB26_Pos (26U) \r
-#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F9R2_FB27_Pos (27U) \r
-#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F9R2_FB28_Pos (28U) \r
-#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F9R2_FB29_Pos (29U) \r
-#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F9R2_FB30_Pos (30U) \r
-#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F9R2_FB31_Pos (31U) \r
-#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F10R2 register ******************/\r
-#define CAN_F10R2_FB0_Pos (0U) \r
-#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F10R2_FB1_Pos (1U) \r
-#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F10R2_FB2_Pos (2U) \r
-#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F10R2_FB3_Pos (3U) \r
-#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F10R2_FB4_Pos (4U) \r
-#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F10R2_FB5_Pos (5U) \r
-#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F10R2_FB6_Pos (6U) \r
-#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F10R2_FB7_Pos (7U) \r
-#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F10R2_FB8_Pos (8U) \r
-#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F10R2_FB9_Pos (9U) \r
-#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F10R2_FB10_Pos (10U) \r
-#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F10R2_FB11_Pos (11U) \r
-#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F10R2_FB12_Pos (12U) \r
-#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F10R2_FB13_Pos (13U) \r
-#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F10R2_FB14_Pos (14U) \r
-#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F10R2_FB15_Pos (15U) \r
-#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F10R2_FB16_Pos (16U) \r
-#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F10R2_FB17_Pos (17U) \r
-#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F10R2_FB18_Pos (18U) \r
-#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F10R2_FB19_Pos (19U) \r
-#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F10R2_FB20_Pos (20U) \r
-#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F10R2_FB21_Pos (21U) \r
-#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F10R2_FB22_Pos (22U) \r
-#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F10R2_FB23_Pos (23U) \r
-#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F10R2_FB24_Pos (24U) \r
-#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F10R2_FB25_Pos (25U) \r
-#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F10R2_FB26_Pos (26U) \r
-#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F10R2_FB27_Pos (27U) \r
-#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F10R2_FB28_Pos (28U) \r
-#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F10R2_FB29_Pos (29U) \r
-#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F10R2_FB30_Pos (30U) \r
-#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F10R2_FB31_Pos (31U) \r
-#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F11R2 register ******************/\r
-#define CAN_F11R2_FB0_Pos (0U) \r
-#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F11R2_FB1_Pos (1U) \r
-#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F11R2_FB2_Pos (2U) \r
-#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F11R2_FB3_Pos (3U) \r
-#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F11R2_FB4_Pos (4U) \r
-#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F11R2_FB5_Pos (5U) \r
-#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F11R2_FB6_Pos (6U) \r
-#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F11R2_FB7_Pos (7U) \r
-#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F11R2_FB8_Pos (8U) \r
-#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F11R2_FB9_Pos (9U) \r
-#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F11R2_FB10_Pos (10U) \r
-#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F11R2_FB11_Pos (11U) \r
-#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F11R2_FB12_Pos (12U) \r
-#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F11R2_FB13_Pos (13U) \r
-#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F11R2_FB14_Pos (14U) \r
-#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F11R2_FB15_Pos (15U) \r
-#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F11R2_FB16_Pos (16U) \r
-#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F11R2_FB17_Pos (17U) \r
-#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F11R2_FB18_Pos (18U) \r
-#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F11R2_FB19_Pos (19U) \r
-#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F11R2_FB20_Pos (20U) \r
-#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F11R2_FB21_Pos (21U) \r
-#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F11R2_FB22_Pos (22U) \r
-#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F11R2_FB23_Pos (23U) \r
-#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F11R2_FB24_Pos (24U) \r
-#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F11R2_FB25_Pos (25U) \r
-#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F11R2_FB26_Pos (26U) \r
-#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F11R2_FB27_Pos (27U) \r
-#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F11R2_FB28_Pos (28U) \r
-#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F11R2_FB29_Pos (29U) \r
-#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F11R2_FB30_Pos (30U) \r
-#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F11R2_FB31_Pos (31U) \r
-#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F12R2 register ******************/\r
-#define CAN_F12R2_FB0_Pos (0U) \r
-#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F12R2_FB1_Pos (1U) \r
-#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F12R2_FB2_Pos (2U) \r
-#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F12R2_FB3_Pos (3U) \r
-#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F12R2_FB4_Pos (4U) \r
-#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F12R2_FB5_Pos (5U) \r
-#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F12R2_FB6_Pos (6U) \r
-#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F12R2_FB7_Pos (7U) \r
-#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F12R2_FB8_Pos (8U) \r
-#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F12R2_FB9_Pos (9U) \r
-#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F12R2_FB10_Pos (10U) \r
-#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F12R2_FB11_Pos (11U) \r
-#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F12R2_FB12_Pos (12U) \r
-#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F12R2_FB13_Pos (13U) \r
-#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F12R2_FB14_Pos (14U) \r
-#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F12R2_FB15_Pos (15U) \r
-#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F12R2_FB16_Pos (16U) \r
-#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F12R2_FB17_Pos (17U) \r
-#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F12R2_FB18_Pos (18U) \r
-#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F12R2_FB19_Pos (19U) \r
-#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F12R2_FB20_Pos (20U) \r
-#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F12R2_FB21_Pos (21U) \r
-#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F12R2_FB22_Pos (22U) \r
-#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F12R2_FB23_Pos (23U) \r
-#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F12R2_FB24_Pos (24U) \r
-#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F12R2_FB25_Pos (25U) \r
-#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F12R2_FB26_Pos (26U) \r
-#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F12R2_FB27_Pos (27U) \r
-#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F12R2_FB28_Pos (28U) \r
-#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F12R2_FB29_Pos (29U) \r
-#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F12R2_FB30_Pos (30U) \r
-#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F12R2_FB31_Pos (31U) \r
-#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F13R2 register ******************/\r
-#define CAN_F13R2_FB0_Pos (0U) \r
-#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */\r
-#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */\r
-#define CAN_F13R2_FB1_Pos (1U) \r
-#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */\r
-#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */\r
-#define CAN_F13R2_FB2_Pos (2U) \r
-#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */\r
-#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */\r
-#define CAN_F13R2_FB3_Pos (3U) \r
-#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */\r
-#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */\r
-#define CAN_F13R2_FB4_Pos (4U) \r
-#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */\r
-#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */\r
-#define CAN_F13R2_FB5_Pos (5U) \r
-#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */\r
-#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */\r
-#define CAN_F13R2_FB6_Pos (6U) \r
-#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */\r
-#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */\r
-#define CAN_F13R2_FB7_Pos (7U) \r
-#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */\r
-#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */\r
-#define CAN_F13R2_FB8_Pos (8U) \r
-#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */\r
-#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */\r
-#define CAN_F13R2_FB9_Pos (9U) \r
-#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */\r
-#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */\r
-#define CAN_F13R2_FB10_Pos (10U) \r
-#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */\r
-#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */\r
-#define CAN_F13R2_FB11_Pos (11U) \r
-#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */\r
-#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */\r
-#define CAN_F13R2_FB12_Pos (12U) \r
-#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */\r
-#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */\r
-#define CAN_F13R2_FB13_Pos (13U) \r
-#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */\r
-#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */\r
-#define CAN_F13R2_FB14_Pos (14U) \r
-#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */\r
-#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */\r
-#define CAN_F13R2_FB15_Pos (15U) \r
-#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */\r
-#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */\r
-#define CAN_F13R2_FB16_Pos (16U) \r
-#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */\r
-#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */\r
-#define CAN_F13R2_FB17_Pos (17U) \r
-#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */\r
-#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */\r
-#define CAN_F13R2_FB18_Pos (18U) \r
-#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */\r
-#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */\r
-#define CAN_F13R2_FB19_Pos (19U) \r
-#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */\r
-#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */\r
-#define CAN_F13R2_FB20_Pos (20U) \r
-#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */\r
-#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */\r
-#define CAN_F13R2_FB21_Pos (21U) \r
-#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */\r
-#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */\r
-#define CAN_F13R2_FB22_Pos (22U) \r
-#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */\r
-#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */\r
-#define CAN_F13R2_FB23_Pos (23U) \r
-#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */\r
-#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */\r
-#define CAN_F13R2_FB24_Pos (24U) \r
-#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */\r
-#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */\r
-#define CAN_F13R2_FB25_Pos (25U) \r
-#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */\r
-#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */\r
-#define CAN_F13R2_FB26_Pos (26U) \r
-#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */\r
-#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */\r
-#define CAN_F13R2_FB27_Pos (27U) \r
-#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */\r
-#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */\r
-#define CAN_F13R2_FB28_Pos (28U) \r
-#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */\r
-#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */\r
-#define CAN_F13R2_FB29_Pos (29U) \r
-#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */\r
-#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */\r
-#define CAN_F13R2_FB30_Pos (30U) \r
-#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */\r
-#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */\r
-#define CAN_F13R2_FB31_Pos (31U) \r
-#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */\r
-#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Serial Peripheral Interface */\r
-/* */\r
-/******************************************************************************/\r
-/*\r
- * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)\r
- */\r
-#define SPI_I2S_SUPPORT /*!< I2S support */\r
-/******************* Bit definition for SPI_CR1 register ********************/\r
-#define SPI_CR1_CPHA_Pos (0U) \r
-#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */\r
-#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */\r
-#define SPI_CR1_CPOL_Pos (1U) \r
-#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */\r
-#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */\r
-#define SPI_CR1_MSTR_Pos (2U) \r
-#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */\r
-#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */\r
-\r
-#define SPI_CR1_BR_Pos (3U) \r
-#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */\r
-#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */\r
-#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */\r
-#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */\r
-#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */\r
-\r
-#define SPI_CR1_SPE_Pos (6U) \r
-#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */\r
-#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */\r
-#define SPI_CR1_LSBFIRST_Pos (7U) \r
-#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */\r
-#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */\r
-#define SPI_CR1_SSI_Pos (8U) \r
-#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */\r
-#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */\r
-#define SPI_CR1_SSM_Pos (9U) \r
-#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */\r
-#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */\r
-#define SPI_CR1_RXONLY_Pos (10U) \r
-#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */\r
-#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */\r
-#define SPI_CR1_DFF_Pos (11U) \r
-#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */\r
-#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */\r
-#define SPI_CR1_CRCNEXT_Pos (12U) \r
-#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */\r
-#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */\r
-#define SPI_CR1_CRCEN_Pos (13U) \r
-#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */\r
-#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */\r
-#define SPI_CR1_BIDIOE_Pos (14U) \r
-#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */\r
-#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */\r
-#define SPI_CR1_BIDIMODE_Pos (15U) \r
-#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */\r
-#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */\r
-\r
-/******************* Bit definition for SPI_CR2 register ********************/\r
-#define SPI_CR2_RXDMAEN_Pos (0U) \r
-#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */\r
-#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */\r
-#define SPI_CR2_TXDMAEN_Pos (1U) \r
-#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */\r
-#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */\r
-#define SPI_CR2_SSOE_Pos (2U) \r
-#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */\r
-#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */\r
-#define SPI_CR2_ERRIE_Pos (5U) \r
-#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */\r
-#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */\r
-#define SPI_CR2_RXNEIE_Pos (6U) \r
-#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */\r
-#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */\r
-#define SPI_CR2_TXEIE_Pos (7U) \r
-#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */\r
-#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */\r
-\r
-/******************** Bit definition for SPI_SR register ********************/\r
-#define SPI_SR_RXNE_Pos (0U) \r
-#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */\r
-#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */\r
-#define SPI_SR_TXE_Pos (1U) \r
-#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */\r
-#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */\r
-#define SPI_SR_CHSIDE_Pos (2U) \r
-#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */\r
-#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */\r
-#define SPI_SR_UDR_Pos (3U) \r
-#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */\r
-#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */\r
-#define SPI_SR_CRCERR_Pos (4U) \r
-#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */\r
-#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */\r
-#define SPI_SR_MODF_Pos (5U) \r
-#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */\r
-#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */\r
-#define SPI_SR_OVR_Pos (6U) \r
-#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */\r
-#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */\r
-#define SPI_SR_BSY_Pos (7U) \r
-#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */\r
-#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */\r
-\r
-/******************** Bit definition for SPI_DR register ********************/\r
-#define SPI_DR_DR_Pos (0U) \r
-#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */\r
-#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */\r
-\r
-/******************* Bit definition for SPI_CRCPR register ******************/\r
-#define SPI_CRCPR_CRCPOLY_Pos (0U) \r
-#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */\r
-#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */\r
-\r
-/****************** Bit definition for SPI_RXCRCR register ******************/\r
-#define SPI_RXCRCR_RXCRC_Pos (0U) \r
-#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */\r
-#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */\r
-\r
-/****************** Bit definition for SPI_TXCRCR register ******************/\r
-#define SPI_TXCRCR_TXCRC_Pos (0U) \r
-#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */\r
-#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */\r
-\r
-/****************** Bit definition for SPI_I2SCFGR register *****************/\r
-#define SPI_I2SCFGR_CHLEN_Pos (0U) \r
-#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */\r
-#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */\r
-\r
-#define SPI_I2SCFGR_DATLEN_Pos (1U) \r
-#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */\r
-#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */\r
-#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */\r
-#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */\r
-\r
-#define SPI_I2SCFGR_CKPOL_Pos (3U) \r
-#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */\r
-#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */\r
-\r
-#define SPI_I2SCFGR_I2SSTD_Pos (4U) \r
-#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */\r
-#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */\r
-#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */\r
-#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */\r
-\r
-#define SPI_I2SCFGR_PCMSYNC_Pos (7U) \r
-#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */\r
-#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */\r
-\r
-#define SPI_I2SCFGR_I2SCFG_Pos (8U) \r
-#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */\r
-#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */\r
-#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */\r
-#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */\r
-\r
-#define SPI_I2SCFGR_I2SE_Pos (10U) \r
-#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */\r
-#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */\r
-#define SPI_I2SCFGR_I2SMOD_Pos (11U) \r
-#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */\r
-#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */\r
-\r
-/****************** Bit definition for SPI_I2SPR register *******************/\r
-#define SPI_I2SPR_I2SDIV_Pos (0U) \r
-#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */\r
-#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */\r
-#define SPI_I2SPR_ODD_Pos (8U) \r
-#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */\r
-#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */\r
-#define SPI_I2SPR_MCKOE_Pos (9U) \r
-#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */\r
-#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Inter-integrated Circuit Interface */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for I2C_CR1 register ********************/\r
-#define I2C_CR1_PE_Pos (0U) \r
-#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */\r
-#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */\r
-#define I2C_CR1_SMBUS_Pos (1U) \r
-#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */\r
-#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */\r
-#define I2C_CR1_SMBTYPE_Pos (3U) \r
-#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */\r
-#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */\r
-#define I2C_CR1_ENARP_Pos (4U) \r
-#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */\r
-#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */\r
-#define I2C_CR1_ENPEC_Pos (5U) \r
-#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */\r
-#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */\r
-#define I2C_CR1_ENGC_Pos (6U) \r
-#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */\r
-#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */\r
-#define I2C_CR1_NOSTRETCH_Pos (7U) \r
-#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */\r
-#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */\r
-#define I2C_CR1_START_Pos (8U) \r
-#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */\r
-#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */\r
-#define I2C_CR1_STOP_Pos (9U) \r
-#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */\r
-#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */\r
-#define I2C_CR1_ACK_Pos (10U) \r
-#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */\r
-#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */\r
-#define I2C_CR1_POS_Pos (11U) \r
-#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */\r
-#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */\r
-#define I2C_CR1_PEC_Pos (12U) \r
-#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */\r
-#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */\r
-#define I2C_CR1_ALERT_Pos (13U) \r
-#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */\r
-#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */\r
-#define I2C_CR1_SWRST_Pos (15U) \r
-#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */\r
-#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */\r
-\r
-/******************* Bit definition for I2C_CR2 register ********************/\r
-#define I2C_CR2_FREQ_Pos (0U) \r
-#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */\r
-#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */\r
-#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */\r
-#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */\r
-#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */\r
-#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */\r
-#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */\r
-#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */\r
-\r
-#define I2C_CR2_ITERREN_Pos (8U) \r
-#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */\r
-#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */\r
-#define I2C_CR2_ITEVTEN_Pos (9U) \r
-#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */\r
-#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */\r
-#define I2C_CR2_ITBUFEN_Pos (10U) \r
-#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */\r
-#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */\r
-#define I2C_CR2_DMAEN_Pos (11U) \r
-#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */\r
-#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */\r
-#define I2C_CR2_LAST_Pos (12U) \r
-#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */\r
-#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */\r
-\r
-/******************* Bit definition for I2C_OAR1 register *******************/\r
-#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */\r
-#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */\r
-\r
-#define I2C_OAR1_ADD0_Pos (0U) \r
-#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */\r
-#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */\r
-#define I2C_OAR1_ADD1_Pos (1U) \r
-#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */\r
-#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */\r
-#define I2C_OAR1_ADD2_Pos (2U) \r
-#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */\r
-#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */\r
-#define I2C_OAR1_ADD3_Pos (3U) \r
-#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */\r
-#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */\r
-#define I2C_OAR1_ADD4_Pos (4U) \r
-#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */\r
-#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */\r
-#define I2C_OAR1_ADD5_Pos (5U) \r
-#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */\r
-#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */\r
-#define I2C_OAR1_ADD6_Pos (6U) \r
-#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */\r
-#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */\r
-#define I2C_OAR1_ADD7_Pos (7U) \r
-#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */\r
-#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */\r
-#define I2C_OAR1_ADD8_Pos (8U) \r
-#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */\r
-#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */\r
-#define I2C_OAR1_ADD9_Pos (9U) \r
-#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */\r
-#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */\r
-\r
-#define I2C_OAR1_ADDMODE_Pos (15U) \r
-#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */\r
-#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */\r
-\r
-/******************* Bit definition for I2C_OAR2 register *******************/\r
-#define I2C_OAR2_ENDUAL_Pos (0U) \r
-#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */\r
-#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */\r
-#define I2C_OAR2_ADD2_Pos (1U) \r
-#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */\r
-#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */\r
-\r
-/******************** Bit definition for I2C_DR register ********************/\r
-#define I2C_DR_DR_Pos (0U) \r
-#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */\r
-#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */\r
-\r
-/******************* Bit definition for I2C_SR1 register ********************/\r
-#define I2C_SR1_SB_Pos (0U) \r
-#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */\r
-#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */\r
-#define I2C_SR1_ADDR_Pos (1U) \r
-#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */\r
-#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */\r
-#define I2C_SR1_BTF_Pos (2U) \r
-#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */\r
-#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */\r
-#define I2C_SR1_ADD10_Pos (3U) \r
-#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */\r
-#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */\r
-#define I2C_SR1_STOPF_Pos (4U) \r
-#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */\r
-#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */\r
-#define I2C_SR1_RXNE_Pos (6U) \r
-#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */\r
-#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */\r
-#define I2C_SR1_TXE_Pos (7U) \r
-#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */\r
-#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */\r
-#define I2C_SR1_BERR_Pos (8U) \r
-#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */\r
-#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */\r
-#define I2C_SR1_ARLO_Pos (9U) \r
-#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */\r
-#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */\r
-#define I2C_SR1_AF_Pos (10U) \r
-#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */\r
-#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */\r
-#define I2C_SR1_OVR_Pos (11U) \r
-#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */\r
-#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */\r
-#define I2C_SR1_PECERR_Pos (12U) \r
-#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */\r
-#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */\r
-#define I2C_SR1_TIMEOUT_Pos (14U) \r
-#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */\r
-#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */\r
-#define I2C_SR1_SMBALERT_Pos (15U) \r
-#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */\r
-#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */\r
-\r
-/******************* Bit definition for I2C_SR2 register ********************/\r
-#define I2C_SR2_MSL_Pos (0U) \r
-#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */\r
-#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */\r
-#define I2C_SR2_BUSY_Pos (1U) \r
-#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */\r
-#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */\r
-#define I2C_SR2_TRA_Pos (2U) \r
-#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */\r
-#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */\r
-#define I2C_SR2_GENCALL_Pos (4U) \r
-#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */\r
-#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */\r
-#define I2C_SR2_SMBDEFAULT_Pos (5U) \r
-#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */\r
-#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */\r
-#define I2C_SR2_SMBHOST_Pos (6U) \r
-#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */\r
-#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */\r
-#define I2C_SR2_DUALF_Pos (7U) \r
-#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */\r
-#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */\r
-#define I2C_SR2_PEC_Pos (8U) \r
-#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */\r
-#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */\r
-\r
-/******************* Bit definition for I2C_CCR register ********************/\r
-#define I2C_CCR_CCR_Pos (0U) \r
-#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */\r
-#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */\r
-#define I2C_CCR_DUTY_Pos (14U) \r
-#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */\r
-#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */\r
-#define I2C_CCR_FS_Pos (15U) \r
-#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */\r
-#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */\r
-\r
-/****************** Bit definition for I2C_TRISE register *******************/\r
-#define I2C_TRISE_TRISE_Pos (0U) \r
-#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */\r
-#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Universal Synchronous Asynchronous Receiver Transmitter */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************* Bit definition for USART_SR register *******************/\r
-#define USART_SR_PE_Pos (0U) \r
-#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */\r
-#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */\r
-#define USART_SR_FE_Pos (1U) \r
-#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */\r
-#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */\r
-#define USART_SR_NE_Pos (2U) \r
-#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */\r
-#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */\r
-#define USART_SR_ORE_Pos (3U) \r
-#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */\r
-#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */\r
-#define USART_SR_IDLE_Pos (4U) \r
-#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */\r
-#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */\r
-#define USART_SR_RXNE_Pos (5U) \r
-#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */\r
-#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */\r
-#define USART_SR_TC_Pos (6U) \r
-#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */\r
-#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */\r
-#define USART_SR_TXE_Pos (7U) \r
-#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */\r
-#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */\r
-#define USART_SR_LBD_Pos (8U) \r
-#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */\r
-#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */\r
-#define USART_SR_CTS_Pos (9U) \r
-#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */\r
-#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */\r
-\r
-/******************* Bit definition for USART_DR register *******************/\r
-#define USART_DR_DR_Pos (0U) \r
-#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */\r
-#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */\r
-\r
-/****************** Bit definition for USART_BRR register *******************/\r
-#define USART_BRR_DIV_Fraction_Pos (0U) \r
-#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */\r
-#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */\r
-#define USART_BRR_DIV_Mantissa_Pos (4U) \r
-#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */\r
-#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */\r
-\r
-/****************** Bit definition for USART_CR1 register *******************/\r
-#define USART_CR1_SBK_Pos (0U) \r
-#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */\r
-#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */\r
-#define USART_CR1_RWU_Pos (1U) \r
-#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */\r
-#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */\r
-#define USART_CR1_RE_Pos (2U) \r
-#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */\r
-#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */\r
-#define USART_CR1_TE_Pos (3U) \r
-#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */\r
-#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */\r
-#define USART_CR1_IDLEIE_Pos (4U) \r
-#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */\r
-#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */\r
-#define USART_CR1_RXNEIE_Pos (5U) \r
-#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */\r
-#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */\r
-#define USART_CR1_TCIE_Pos (6U) \r
-#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */\r
-#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */\r
-#define USART_CR1_TXEIE_Pos (7U) \r
-#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */\r
-#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */\r
-#define USART_CR1_PEIE_Pos (8U) \r
-#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */\r
-#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */\r
-#define USART_CR1_PS_Pos (9U) \r
-#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */\r
-#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */\r
-#define USART_CR1_PCE_Pos (10U) \r
-#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */\r
-#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */\r
-#define USART_CR1_WAKE_Pos (11U) \r
-#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */\r
-#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */\r
-#define USART_CR1_M_Pos (12U) \r
-#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */\r
-#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */\r
-#define USART_CR1_UE_Pos (13U) \r
-#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */\r
-#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */\r
-\r
-/****************** Bit definition for USART_CR2 register *******************/\r
-#define USART_CR2_ADD_Pos (0U) \r
-#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */\r
-#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */\r
-#define USART_CR2_LBDL_Pos (5U) \r
-#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */\r
-#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */\r
-#define USART_CR2_LBDIE_Pos (6U) \r
-#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */\r
-#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */\r
-#define USART_CR2_LBCL_Pos (8U) \r
-#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */\r
-#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */\r
-#define USART_CR2_CPHA_Pos (9U) \r
-#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */\r
-#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */\r
-#define USART_CR2_CPOL_Pos (10U) \r
-#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */\r
-#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */\r
-#define USART_CR2_CLKEN_Pos (11U) \r
-#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */\r
-#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */\r
-\r
-#define USART_CR2_STOP_Pos (12U) \r
-#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */\r
-#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */\r
-#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */\r
-#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */\r
-\r
-#define USART_CR2_LINEN_Pos (14U) \r
-#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */\r
-#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */\r
-\r
-/****************** Bit definition for USART_CR3 register *******************/\r
-#define USART_CR3_EIE_Pos (0U) \r
-#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */\r
-#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */\r
-#define USART_CR3_IREN_Pos (1U) \r
-#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */\r
-#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */\r
-#define USART_CR3_IRLP_Pos (2U) \r
-#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */\r
-#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */\r
-#define USART_CR3_HDSEL_Pos (3U) \r
-#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */\r
-#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */\r
-#define USART_CR3_NACK_Pos (4U) \r
-#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */\r
-#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */\r
-#define USART_CR3_SCEN_Pos (5U) \r
-#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */\r
-#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */\r
-#define USART_CR3_DMAR_Pos (6U) \r
-#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */\r
-#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */\r
-#define USART_CR3_DMAT_Pos (7U) \r
-#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */\r
-#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */\r
-#define USART_CR3_RTSE_Pos (8U) \r
-#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */\r
-#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */\r
-#define USART_CR3_CTSE_Pos (9U) \r
-#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */\r
-#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */\r
-#define USART_CR3_CTSIE_Pos (10U) \r
-#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */\r
-#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */\r
-\r
-/****************** Bit definition for USART_GTPR register ******************/\r
-#define USART_GTPR_PSC_Pos (0U) \r
-#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */\r
-#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */\r
-#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */\r
-#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */\r
-#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */\r
-#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */\r
-#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */\r
-#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */\r
-#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */\r
-#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */\r
-\r
-#define USART_GTPR_GT_Pos (8U) \r
-#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */\r
-#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Debug MCU */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/**************** Bit definition for DBGMCU_IDCODE register *****************/\r
-#define DBGMCU_IDCODE_DEV_ID_Pos (0U) \r
-#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r
-#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */\r
-\r
-#define DBGMCU_IDCODE_REV_ID_Pos (16U) \r
-#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r
-#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */\r
-#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */\r
-#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */\r
-#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */\r
-#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */\r
-#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */\r
-#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */\r
-#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */\r
-#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */\r
-#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */\r
-#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */\r
-#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */\r
-#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */\r
-#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */\r
-#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */\r
-#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */\r
-#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */\r
-\r
-/****************** Bit definition for DBGMCU_CR register *******************/\r
-#define DBGMCU_CR_DBG_SLEEP_Pos (0U) \r
-#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\r
-#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */\r
-#define DBGMCU_CR_DBG_STOP_Pos (1U) \r
-#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\r
-#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */\r
-#define DBGMCU_CR_DBG_STANDBY_Pos (2U) \r
-#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\r
-#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */\r
-#define DBGMCU_CR_TRACE_IOEN_Pos (5U) \r
-#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\r
-#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */\r
-\r
-#define DBGMCU_CR_TRACE_MODE_Pos (6U) \r
-#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\r
-#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\r
-#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\r
-#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\r
-\r
-#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) \r
-#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */\r
-#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) \r
-#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */\r
-#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) \r
-#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */\r
-#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) \r
-#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */\r
-#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) \r
-#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */\r
-#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U) \r
-#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */\r
-#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U) \r
-#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */\r
-#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) \r
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */\r
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) \r
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */\r
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */\r
-#define DBGMCU_CR_DBG_TIM8_STOP_Pos (17U) \r
-#define DBGMCU_CR_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM8_STOP_Pos) /*!< 0x00020000 */\r
-#define DBGMCU_CR_DBG_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP_Msk /*!< TIM8 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U) \r
-#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */\r
-#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U) \r
-#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */\r
-#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */\r
-#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U) \r
-#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */\r
-#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* FLASH and Option Bytes Registers */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for FLASH_ACR register ******************/\r
-#define FLASH_ACR_LATENCY_Pos (0U) \r
-#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */\r
-#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */\r
-#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */\r
-#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */\r
-#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */\r
-\r
-#define FLASH_ACR_HLFCYA_Pos (3U) \r
-#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */\r
-#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */\r
-#define FLASH_ACR_PRFTBE_Pos (4U) \r
-#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */\r
-#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */\r
-#define FLASH_ACR_PRFTBS_Pos (5U) \r
-#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */\r
-#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */\r
-\r
-/****************** Bit definition for FLASH_KEYR register ******************/\r
-#define FLASH_KEYR_FKEYR_Pos (0U) \r
-#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */\r
-#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */\r
-\r
-#define RDP_KEY_Pos (0U) \r
-#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */\r
-#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */\r
-#define FLASH_KEY1_Pos (0U) \r
-#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */\r
-#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */\r
-#define FLASH_KEY2_Pos (0U) \r
-#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */\r
-#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */\r
-\r
-/***************** Bit definition for FLASH_OPTKEYR register ****************/\r
-#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) \r
-#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */\r
-#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */\r
-\r
-#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */\r
-#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */\r
-\r
-/****************** Bit definition for FLASH_SR register ********************/\r
-#define FLASH_SR_BSY_Pos (0U) \r
-#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */\r
-#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */\r
-#define FLASH_SR_PGERR_Pos (2U) \r
-#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */\r
-#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */\r
-#define FLASH_SR_WRPRTERR_Pos (4U) \r
-#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */\r
-#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */\r
-#define FLASH_SR_EOP_Pos (5U) \r
-#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */\r
-#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */\r
-\r
-/******************* Bit definition for FLASH_CR register *******************/\r
-#define FLASH_CR_PG_Pos (0U) \r
-#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */\r
-#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */\r
-#define FLASH_CR_PER_Pos (1U) \r
-#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */\r
-#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */\r
-#define FLASH_CR_MER_Pos (2U) \r
-#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */\r
-#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */\r
-#define FLASH_CR_OPTPG_Pos (4U) \r
-#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */\r
-#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */\r
-#define FLASH_CR_OPTER_Pos (5U) \r
-#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */\r
-#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */\r
-#define FLASH_CR_STRT_Pos (6U) \r
-#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */\r
-#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */\r
-#define FLASH_CR_LOCK_Pos (7U) \r
-#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */\r
-#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */\r
-#define FLASH_CR_OPTWRE_Pos (9U) \r
-#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */\r
-#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */\r
-#define FLASH_CR_ERRIE_Pos (10U) \r
-#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */\r
-#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */\r
-#define FLASH_CR_EOPIE_Pos (12U) \r
-#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */\r
-#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */\r
-\r
-/******************* Bit definition for FLASH_AR register *******************/\r
-#define FLASH_AR_FAR_Pos (0U) \r
-#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */\r
-#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */\r
-\r
-/****************** Bit definition for FLASH_OBR register *******************/\r
-#define FLASH_OBR_OPTERR_Pos (0U) \r
-#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */\r
-#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */\r
-#define FLASH_OBR_RDPRT_Pos (1U) \r
-#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */\r
-#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */\r
-\r
-#define FLASH_OBR_IWDG_SW_Pos (2U) \r
-#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */\r
-#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */\r
-#define FLASH_OBR_nRST_STOP_Pos (3U) \r
-#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */\r
-#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */\r
-#define FLASH_OBR_nRST_STDBY_Pos (4U) \r
-#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */\r
-#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */\r
-#define FLASH_OBR_USER_Pos (2U) \r
-#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */\r
-#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */\r
-#define FLASH_OBR_DATA0_Pos (10U) \r
-#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */\r
-#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */\r
-#define FLASH_OBR_DATA1_Pos (18U) \r
-#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */\r
-#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */\r
-\r
-/****************** Bit definition for FLASH_WRPR register ******************/\r
-#define FLASH_WRPR_WRP_Pos (0U) \r
-#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */\r
-#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/****************** Bit definition for FLASH_RDP register *******************/\r
-#define FLASH_RDP_RDP_Pos (0U) \r
-#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */\r
-#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */\r
-#define FLASH_RDP_nRDP_Pos (8U) \r
-#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */\r
-#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */\r
-\r
-/****************** Bit definition for FLASH_USER register ******************/\r
-#define FLASH_USER_USER_Pos (16U) \r
-#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */\r
-#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */\r
-#define FLASH_USER_nUSER_Pos (24U) \r
-#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */\r
-#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */\r
-\r
-/****************** Bit definition for FLASH_Data0 register *****************/\r
-#define FLASH_DATA0_DATA0_Pos (0U) \r
-#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */\r
-#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */\r
-#define FLASH_DATA0_nDATA0_Pos (8U) \r
-#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */\r
-#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */\r
-\r
-/****************** Bit definition for FLASH_Data1 register *****************/\r
-#define FLASH_DATA1_DATA1_Pos (16U) \r
-#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */\r
-#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */\r
-#define FLASH_DATA1_nDATA1_Pos (24U) \r
-#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */\r
-#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */\r
-\r
-/****************** Bit definition for FLASH_WRP0 register ******************/\r
-#define FLASH_WRP0_WRP0_Pos (0U) \r
-#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */\r
-#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */\r
-#define FLASH_WRP0_nWRP0_Pos (8U) \r
-#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */\r
-#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */\r
-\r
-/****************** Bit definition for FLASH_WRP1 register ******************/\r
-#define FLASH_WRP1_WRP1_Pos (16U) \r
-#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */\r
-#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */\r
-#define FLASH_WRP1_nWRP1_Pos (24U) \r
-#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */\r
-#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */\r
-\r
-/****************** Bit definition for FLASH_WRP2 register ******************/\r
-#define FLASH_WRP2_WRP2_Pos (0U) \r
-#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */\r
-#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */\r
-#define FLASH_WRP2_nWRP2_Pos (8U) \r
-#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */\r
-#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */\r
-\r
-/****************** Bit definition for FLASH_WRP3 register ******************/\r
-#define FLASH_WRP3_WRP3_Pos (16U) \r
-#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */\r
-#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */\r
-#define FLASH_WRP3_nWRP3_Pos (24U) \r
-#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */\r
-#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */\r
-\r
-\r
-\r
-/**\r
- * @}\r
-*/\r
-\r
-/**\r
- * @}\r
-*/ \r
-\r
-/** @addtogroup Exported_macro\r
- * @{\r
- */\r
-\r
-/****************************** ADC Instances *********************************/\r
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\r
- ((INSTANCE) == ADC2) || \\r
- ((INSTANCE) == ADC3))\r
- \r
-#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r
-\r
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)\r
-\r
-#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\r
- ((INSTANCE) == ADC3))\r
-\r
-/****************************** CAN Instances *********************************/ \r
-#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)\r
-\r
-/****************************** CRC Instances *********************************/\r
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\r
-\r
-/****************************** DAC Instances *********************************/\r
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\r
-\r
-/****************************** DMA Instances *********************************/\r
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \\r
- ((INSTANCE) == DMA1_Channel2) || \\r
- ((INSTANCE) == DMA1_Channel3) || \\r
- ((INSTANCE) == DMA1_Channel4) || \\r
- ((INSTANCE) == DMA1_Channel5) || \\r
- ((INSTANCE) == DMA1_Channel6) || \\r
- ((INSTANCE) == DMA1_Channel7) || \\r
- ((INSTANCE) == DMA2_Channel1) || \\r
- ((INSTANCE) == DMA2_Channel2) || \\r
- ((INSTANCE) == DMA2_Channel3) || \\r
- ((INSTANCE) == DMA2_Channel4) || \\r
- ((INSTANCE) == DMA2_Channel5))\r
- \r
-/******************************* GPIO Instances *******************************/\r
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\r
- ((INSTANCE) == GPIOB) || \\r
- ((INSTANCE) == GPIOC) || \\r
- ((INSTANCE) == GPIOD) || \\r
- ((INSTANCE) == GPIOE) || \\r
- ((INSTANCE) == GPIOF) || \\r
- ((INSTANCE) == GPIOG))\r
-\r
-/**************************** GPIO Alternate Function Instances ***************/\r
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r
-\r
-/**************************** GPIO Lock Instances *****************************/\r
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r
-\r
-/******************************** I2C Instances *******************************/\r
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\r
- ((INSTANCE) == I2C2))\r
-\r
-/******************************* SMBUS Instances ******************************/\r
-#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE\r
-\r
-/******************************** I2S Instances *******************************/\r
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \\r
- ((INSTANCE) == SPI3))\r
-\r
-/****************************** IWDG Instances ********************************/\r
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)\r
-\r
-/****************************** SDIO Instances *********************************/\r
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\r
-\r
-/******************************** SPI Instances *******************************/\r
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\r
- ((INSTANCE) == SPI2) || \\r
- ((INSTANCE) == SPI3))\r
-\r
-/****************************** START TIM Instances ***************************/\r
-/****************************** TIM Instances *********************************/\r
-#define IS_TIM_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5) || \\r
- ((INSTANCE) == TIM6) || \\r
- ((INSTANCE) == TIM7))\r
-\r
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8))\r
-\r
-#define IS_TIM_CC1_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_CC2_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_CC3_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_CC4_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_XOR_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5) || \\r
- ((INSTANCE) == TIM6) || \\r
- ((INSTANCE) == TIM7))\r
-\r
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)\r
-\r
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8))\r
-\r
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\r
- ((((INSTANCE) == TIM1) && \\r
- (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3) || \\r
- ((CHANNEL) == TIM_CHANNEL_4))) \\r
- || \\r
- (((INSTANCE) == TIM8) && \\r
- (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3) || \\r
- ((CHANNEL) == TIM_CHANNEL_4))) \\r
- || \\r
- (((INSTANCE) == TIM2) && \\r
- (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3) || \\r
- ((CHANNEL) == TIM_CHANNEL_4))) \\r
- || \\r
- (((INSTANCE) == TIM3) && \\r
- (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3) || \\r
- ((CHANNEL) == TIM_CHANNEL_4))) \\r
- || \\r
- (((INSTANCE) == TIM4) && \\r
- (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3) || \\r
- ((CHANNEL) == TIM_CHANNEL_4))) \\r
- || \\r
- (((INSTANCE) == TIM5) && \\r
- (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3) || \\r
- ((CHANNEL) == TIM_CHANNEL_4))))\r
-\r
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\r
- ((((INSTANCE) == TIM1) && \\r
- (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3))) \\r
- || \\r
- (((INSTANCE) == TIM8) && \\r
- (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3))))\r
-\r
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8))\r
-\r
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
-\r
-#define IS_TIM_DMA_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5) || \\r
- ((INSTANCE) == TIM6) || \\r
- ((INSTANCE) == TIM7))\r
- \r
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5))\r
- \r
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\\r
- (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM8))\r
-\r
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5) || \\r
- ((INSTANCE) == TIM8))\r
-\r
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
- ((INSTANCE) == TIM2) || \\r
- ((INSTANCE) == TIM3) || \\r
- ((INSTANCE) == TIM4) || \\r
- ((INSTANCE) == TIM5) || \\r
- ((INSTANCE) == TIM8))\r
-\r
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U\r
-\r
-/****************************** END TIM Instances *****************************/\r
-\r
-\r
-/******************** USART Instances : Synchronous mode **********************/ \r
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
- ((INSTANCE) == USART2) || \\r
- ((INSTANCE) == USART3))\r
-\r
-/******************** UART Instances : Asynchronous mode **********************/\r
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
- ((INSTANCE) == USART2) || \\r
- ((INSTANCE) == USART3) || \\r
- ((INSTANCE) == UART4) || \\r
- ((INSTANCE) == UART5))\r
-\r
-/******************** UART Instances : Half-Duplex mode **********************/\r
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
- ((INSTANCE) == USART2) || \\r
- ((INSTANCE) == USART3) || \\r
- ((INSTANCE) == UART4) || \\r
- ((INSTANCE) == UART5))\r
-\r
-/******************** UART Instances : LIN mode **********************/\r
-#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
- ((INSTANCE) == USART2) || \\r
- ((INSTANCE) == USART3) || \\r
- ((INSTANCE) == UART4) || \\r
- ((INSTANCE) == UART5))\r
-\r
-/****************** UART Instances : Hardware Flow control ********************/ \r
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
- ((INSTANCE) == USART2) || \\r
- ((INSTANCE) == USART3))\r
-\r
-/********************* UART Instances : Smard card mode ***********************/\r
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
- ((INSTANCE) == USART2) || \\r
- ((INSTANCE) == USART3))\r
-\r
-/*********************** UART Instances : IRDA mode ***************************/\r
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
- ((INSTANCE) == USART2) || \\r
- ((INSTANCE) == USART3) || \\r
- ((INSTANCE) == UART4) || \\r
- ((INSTANCE) == UART5))\r
-\r
-/***************** UART Instances : Multi-Processor mode **********************/\r
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
- ((INSTANCE) == USART2) || \\r
- ((INSTANCE) == USART3) || \\r
- ((INSTANCE) == UART4) || \\r
- ((INSTANCE) == UART5))\r
-\r
-/***************** UART Instances : DMA mode available **********************/\r
-#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
- ((INSTANCE) == USART2) || \\r
- ((INSTANCE) == USART3) || \\r
- ((INSTANCE) == UART4))\r
-\r
-/****************************** RTC Instances *********************************/\r
-#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)\r
-\r
-/**************************** WWDG Instances *****************************/\r
-#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)\r
-\r
-/****************************** USB Instances ********************************/\r
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)\r
-\r
-\r
-\r
-#define RCC_HSE_MIN 4000000U\r
-#define RCC_HSE_MAX 16000000U\r
-\r
-#define RCC_MAX_FREQUENCY 72000000U\r
-\r
-/**\r
- * @}\r
- */ \r
-/******************************************************************************/\r
-/* For a painless codes migration between the STM32F1xx device product */\r
-/* lines, the aliases defined below are put in place to overcome the */\r
-/* differences in the interrupt handlers and IRQn definitions. */\r
-/* No need to update developed interrupt code when moving across */ \r
-/* product lines within the same STM32F1 Family */\r
-/******************************************************************************/\r
-\r
-/* Aliases for __IRQn */\r
-#define ADC1_IRQn ADC1_2_IRQn\r
-#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn\r
-#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn\r
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn\r
-#define TIM9_IRQn TIM1_BRK_IRQn\r
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn\r
-#define TIM11_IRQn TIM1_TRG_COM_IRQn\r
-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn\r
-#define TIM10_IRQn TIM1_UP_IRQn\r
-#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn\r
-#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn\r
-#define TIM6_DAC_IRQn TIM6_IRQn\r
-#define TIM12_IRQn TIM8_BRK_IRQn\r
-#define TIM8_BRK_TIM12_IRQn TIM8_BRK_IRQn\r
-#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn\r
-#define TIM14_IRQn TIM8_TRG_COM_IRQn\r
-#define TIM8_UP_TIM13_IRQn TIM8_UP_IRQn\r
-#define TIM13_IRQn TIM8_UP_IRQn\r
-#define CEC_IRQn USBWakeUp_IRQn\r
-#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn\r
-#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn\r
-#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn\r
-#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn\r
-#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn\r
-\r
-\r
-/* Aliases for __IRQHandler */\r
-#define ADC1_IRQHandler ADC1_2_IRQHandler\r
-#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler\r
-#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler\r
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler\r
-#define TIM9_IRQHandler TIM1_BRK_IRQHandler\r
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler\r
-#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler\r
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler\r
-#define TIM10_IRQHandler TIM1_UP_IRQHandler\r
-#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler\r
-#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler\r
-#define TIM6_DAC_IRQHandler TIM6_IRQHandler\r
-#define TIM12_IRQHandler TIM8_BRK_IRQHandler\r
-#define TIM8_BRK_TIM12_IRQHandler TIM8_BRK_IRQHandler\r
-#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler\r
-#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler\r
-#define TIM8_UP_TIM13_IRQHandler TIM8_UP_IRQHandler\r
-#define TIM13_IRQHandler TIM8_UP_IRQHandler\r
-#define CEC_IRQHandler USBWakeUp_IRQHandler\r
-#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler\r
-#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler\r
-#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler\r
-#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler\r
-#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
- }\r
-#endif /* __cplusplus */\r
- \r
-#endif /* __STM32F103xE_H */\r
- \r
- \r
- \r
- /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx.h\r
- * @author MCD Application Team\r
- * @version V4.2.0\r
- * @date 31-March-2017\r
- * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File. \r
- *\r
- * The file is the unique include file that the application programmer\r
- * is using in the C source code, usually in main.c. This file contains:\r
- * - Configuration section that allows to select:\r
- * - The STM32F1xx device used in the target application\r
- * - To use or not the peripheral\92s drivers in application code(i.e. \r
- * code will be based on direct access to peripheral\92s registers \r
- * rather than drivers API), this option is controlled by \r
- * "#define USE_HAL_DRIVER"\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f1xx\r
- * @{\r
- */\r
- \r
-#ifndef __STM32F1XX_H\r
-#define __STM32F1XX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif /* __cplusplus */\r
- \r
-/** @addtogroup Library_configuration_section\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief STM32 Family\r
- */\r
-#if !defined (STM32F1)\r
-#define STM32F1\r
-#endif /* STM32F1 */\r
-\r
-/* Uncomment the line below according to the target STM32L device used in your \r
- application \r
- */\r
-\r
-#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \\r
- !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \\r
- !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)\r
- /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */\r
- /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */\r
- /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */\r
- /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */\r
- /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ \r
- /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */\r
- /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */\r
- /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */\r
- /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */\r
- /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */\r
- /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */\r
- /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */\r
- /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */\r
- /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ \r
-#endif\r
-\r
-/* Tip: To avoid modifying this file each time you need to switch between these\r
- devices, you can define the device in your toolchain compiler preprocessor.\r
- */\r
- \r
-#if !defined (USE_HAL_DRIVER)\r
-/**\r
- * @brief Comment the line below if you will not use the peripherals drivers.\r
- In this case, these drivers will not be included and the application code will \r
- be based on direct access to peripherals registers \r
- */\r
- /*#define USE_HAL_DRIVER */\r
-#endif /* USE_HAL_DRIVER */\r
-\r
-/**\r
- * @brief CMSIS Device version number V4.2.0\r
- */\r
-#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */\r
-#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */\r
-#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
-#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
-#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\\r
- |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\\r
- |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\\r
- |(__STM32F1_CMSIS_VERSION_RC))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Device_Included\r
- * @{\r
- */\r
-\r
-#if defined(STM32F100xB)\r
- #include "stm32f100xb.h"\r
-#elif defined(STM32F100xE)\r
- #include "stm32f100xe.h"\r
-#elif defined(STM32F101x6)\r
- #include "stm32f101x6.h"\r
-#elif defined(STM32F101xB)\r
- #include "stm32f101xb.h"\r
-#elif defined(STM32F101xE)\r
- #include "stm32f101xe.h"\r
-#elif defined(STM32F101xG)\r
- #include "stm32f101xg.h"\r
-#elif defined(STM32F102x6)\r
- #include "stm32f102x6.h"\r
-#elif defined(STM32F102xB)\r
- #include "stm32f102xb.h"\r
-#elif defined(STM32F103x6)\r
- #include "stm32f103x6.h"\r
-#elif defined(STM32F103xB)\r
- #include "stm32f103xb.h"\r
-#elif defined(STM32F103xE)\r
- #include "stm32f103xe.h"\r
-#elif defined(STM32F103xG)\r
- #include "stm32f103xg.h"\r
-#elif defined(STM32F105xC)\r
- #include "stm32f105xc.h"\r
-#elif defined(STM32F107xC)\r
- #include "stm32f107xc.h"\r
-#else\r
- #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Exported_types\r
- * @{\r
- */ \r
-typedef enum \r
-{\r
- RESET = 0, \r
- SET = !RESET\r
-} FlagStatus, ITStatus;\r
-\r
-typedef enum \r
-{\r
- DISABLE = 0, \r
- ENABLE = !DISABLE\r
-} FunctionalState;\r
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
-\r
-typedef enum \r
-{\r
- ERROR = 0, \r
- SUCCESS = !ERROR\r
-} ErrorStatus;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @addtogroup Exported_macros\r
- * @{\r
- */\r
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
-\r
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
-\r
-#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
-\r
-#define CLEAR_REG(REG) ((REG) = (0x0))\r
-\r
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
-\r
-#define READ_REG(REG) ((REG))\r
-\r
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
-\r
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) \r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined (USE_HAL_DRIVER)\r
- #include "stm32f1xx_hal.h"\r
-#endif /* USE_HAL_DRIVER */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif /* __cplusplus */\r
-\r
-#endif /* __STM32F1xx_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-\r
-\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32f10x.h\r
- * @author MCD Application Team\r
- * @version V4.2.0\r
- * @date 31-March-2017\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f10x_system\r
- * @{\r
- */ \r
- \r
-/**\r
- * @brief Define to prevent recursive inclusion\r
- */\r
-#ifndef __SYSTEM_STM32F10X_H\r
-#define __SYSTEM_STM32F10X_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/** @addtogroup STM32F10x_System_Includes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @addtogroup STM32F10x_System_Exported_types\r
- * @{\r
- */\r
-\r
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
-extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */\r
-extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Functions\r
- * @{\r
- */\r
- \r
-extern void SystemInit(void);\r
-extern void SystemCoreClockUpdate(void);\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__SYSTEM_STM32F10X_H */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/* ----------------------------------------------------------------------\r
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
-*\r
-* $Date: 19. October 2015\r
-* $Revision: V.1.4.5 a\r
-*\r
-* Project: CMSIS DSP Library\r
-* Title: arm_common_tables.h\r
-*\r
-* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions\r
-*\r
-* Target Processor: Cortex-M4/Cortex-M3\r
-*\r
-* Redistribution and use in source and binary forms, with or without\r
-* modification, are permitted provided that the following conditions\r
-* are met:\r
-* - Redistributions of source code must retain the above copyright\r
-* notice, this list of conditions and the following disclaimer.\r
-* - Redistributions in binary form must reproduce the above copyright\r
-* notice, this list of conditions and the following disclaimer in\r
-* the documentation and/or other materials provided with the\r
-* distribution.\r
-* - Neither the name of ARM LIMITED nor the names of its contributors\r
-* may be used to endorse or promote products derived from this\r
-* software without specific prior written permission.\r
-*\r
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
-* POSSIBILITY OF SUCH DAMAGE.\r
-* -------------------------------------------------------------------- */\r
-\r
-#ifndef _ARM_COMMON_TABLES_H\r
-#define _ARM_COMMON_TABLES_H\r
-\r
-#include "arm_math.h"\r
-\r
-extern const uint16_t armBitRevTable[1024];\r
-extern const q15_t armRecipTableQ15[64];\r
-extern const q31_t armRecipTableQ31[64];\r
-/* extern const q31_t realCoefAQ31[1024]; */\r
-/* extern const q31_t realCoefBQ31[1024]; */\r
-extern const float32_t twiddleCoef_16[32];\r
-extern const float32_t twiddleCoef_32[64];\r
-extern const float32_t twiddleCoef_64[128];\r
-extern const float32_t twiddleCoef_128[256];\r
-extern const float32_t twiddleCoef_256[512];\r
-extern const float32_t twiddleCoef_512[1024];\r
-extern const float32_t twiddleCoef_1024[2048];\r
-extern const float32_t twiddleCoef_2048[4096];\r
-extern const float32_t twiddleCoef_4096[8192];\r
-#define twiddleCoef twiddleCoef_4096\r
-extern const q31_t twiddleCoef_16_q31[24];\r
-extern const q31_t twiddleCoef_32_q31[48];\r
-extern const q31_t twiddleCoef_64_q31[96];\r
-extern const q31_t twiddleCoef_128_q31[192];\r
-extern const q31_t twiddleCoef_256_q31[384];\r
-extern const q31_t twiddleCoef_512_q31[768];\r
-extern const q31_t twiddleCoef_1024_q31[1536];\r
-extern const q31_t twiddleCoef_2048_q31[3072];\r
-extern const q31_t twiddleCoef_4096_q31[6144];\r
-extern const q15_t twiddleCoef_16_q15[24];\r
-extern const q15_t twiddleCoef_32_q15[48];\r
-extern const q15_t twiddleCoef_64_q15[96];\r
-extern const q15_t twiddleCoef_128_q15[192];\r
-extern const q15_t twiddleCoef_256_q15[384];\r
-extern const q15_t twiddleCoef_512_q15[768];\r
-extern const q15_t twiddleCoef_1024_q15[1536];\r
-extern const q15_t twiddleCoef_2048_q15[3072];\r
-extern const q15_t twiddleCoef_4096_q15[6144];\r
-extern const float32_t twiddleCoef_rfft_32[32];\r
-extern const float32_t twiddleCoef_rfft_64[64];\r
-extern const float32_t twiddleCoef_rfft_128[128];\r
-extern const float32_t twiddleCoef_rfft_256[256];\r
-extern const float32_t twiddleCoef_rfft_512[512];\r
-extern const float32_t twiddleCoef_rfft_1024[1024];\r
-extern const float32_t twiddleCoef_rfft_2048[2048];\r
-extern const float32_t twiddleCoef_rfft_4096[4096];\r
-\r
-\r
-/* floating-point bit reversal tables */\r
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )\r
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )\r
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )\r
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )\r
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )\r
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )\r
-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)\r
-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)\r
-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)\r
-\r
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];\r
-\r
-/* fixed-point bit reversal tables */\r
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )\r
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )\r
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )\r
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )\r
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )\r
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )\r
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )\r
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)\r
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)\r
-\r
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];\r
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];\r
-\r
-/* Tables for Fast Math Sine and Cosine */\r
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\r
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\r
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\r
-\r
-#endif /* ARM_COMMON_TABLES_H */\r
+++ /dev/null
-/* ----------------------------------------------------------------------\r
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
-*\r
-* $Date: 19. March 2015\r
-* $Revision: V.1.4.5\r
-*\r
-* Project: CMSIS DSP Library\r
-* Title: arm_const_structs.h\r
-*\r
-* Description: This file has constant structs that are initialized for\r
-* user convenience. For example, some can be given as\r
-* arguments to the arm_cfft_f32() function.\r
-*\r
-* Target Processor: Cortex-M4/Cortex-M3\r
-*\r
-* Redistribution and use in source and binary forms, with or without\r
-* modification, are permitted provided that the following conditions\r
-* are met:\r
-* - Redistributions of source code must retain the above copyright\r
-* notice, this list of conditions and the following disclaimer.\r
-* - Redistributions in binary form must reproduce the above copyright\r
-* notice, this list of conditions and the following disclaimer in\r
-* the documentation and/or other materials provided with the\r
-* distribution.\r
-* - Neither the name of ARM LIMITED nor the names of its contributors\r
-* may be used to endorse or promote products derived from this\r
-* software without specific prior written permission.\r
-*\r
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
-* POSSIBILITY OF SUCH DAMAGE.\r
-* -------------------------------------------------------------------- */\r
-\r
-#ifndef _ARM_CONST_STRUCTS_H\r
-#define _ARM_CONST_STRUCTS_H\r
-\r
-#include "arm_math.h"\r
-#include "arm_common_tables.h"\r
-\r
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\r
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\r
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\r
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\r
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\r
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\r
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\r
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\r
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\r
-\r
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;\r
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;\r
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;\r
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;\r
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;\r
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;\r
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;\r
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;\r
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;\r
-\r
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;\r
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;\r
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;\r
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;\r
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;\r
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;\r
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;\r
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;\r
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;\r
-\r
-#endif\r
+++ /dev/null
-/* ----------------------------------------------------------------------\r
-* Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r
-*\r
-* $Date: 20. October 2015\r
-* $Revision: V1.4.5 b\r
-*\r
-* Project: CMSIS DSP Library\r
-* Title: arm_math.h\r
-*\r
-* Description: Public header file for CMSIS DSP Library\r
-*\r
-* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0\r
-*\r
-* Redistribution and use in source and binary forms, with or without\r
-* modification, are permitted provided that the following conditions\r
-* are met:\r
-* - Redistributions of source code must retain the above copyright\r
-* notice, this list of conditions and the following disclaimer.\r
-* - Redistributions in binary form must reproduce the above copyright\r
-* notice, this list of conditions and the following disclaimer in\r
-* the documentation and/or other materials provided with the\r
-* distribution.\r
-* - Neither the name of ARM LIMITED nor the names of its contributors\r
-* may be used to endorse or promote products derived from this\r
-* software without specific prior written permission.\r
-*\r
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
-* POSSIBILITY OF SUCH DAMAGE.\r
- * -------------------------------------------------------------------- */\r
-\r
-/**\r
- \mainpage CMSIS DSP Software Library\r
- *\r
- * Introduction\r
- * ------------\r
- *\r
- * This user manual describes the CMSIS DSP software library,\r
- * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
- *\r
- * The library is divided into a number of functions each covering a specific category:\r
- * - Basic math functions\r
- * - Fast math functions\r
- * - Complex math functions\r
- * - Filters\r
- * - Matrix functions\r
- * - Transforms\r
- * - Motor control functions\r
- * - Statistical functions\r
- * - Support functions\r
- * - Interpolation functions\r
- *\r
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
- * 32-bit integer and 32-bit floating-point values.\r
- *\r
- * Using the Library\r
- * ------------\r
- *\r
- * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
- * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)\r
- * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)\r
- * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)\r
- * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)\r
- * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)\r
- * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)\r
- * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r
- * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r
- * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r
- * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r
- * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r
- * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r
- * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)\r
- * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)\r
- *\r
- * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
- * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
- * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or\r
- * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r
- *\r
- * Examples\r
- * --------\r
- *\r
- * The library ships with a number of examples which demonstrate how to use the library functions.\r
- *\r
- * Toolchain Support\r
- * ------------\r
- *\r
- * The library has been developed and tested with MDK-ARM version 5.14.0.0\r
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
- *\r
- * Building the Library\r
- * ------------\r
- *\r
- * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
- * - arm_cortexM_math.uvprojx\r
- *\r
- *\r
- * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r
- *\r
- * Pre-processor Macros\r
- * ------------\r
- *\r
- * Each library project have differant pre-processor macros.\r
- *\r
- * - UNALIGNED_SUPPORT_DISABLE:\r
- *\r
- * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r
- *\r
- * - ARM_MATH_BIG_ENDIAN:\r
- *\r
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
- *\r
- * - ARM_MATH_MATRIX_CHECK:\r
- *\r
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r
- *\r
- * - ARM_MATH_ROUNDING:\r
- *\r
- * Define macro ARM_MATH_ROUNDING for rounding on support functions\r
- *\r
- * - ARM_MATH_CMx:\r
- *\r
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
- * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\r
- * ARM_MATH_CM7 for building the library on cortex-M7.\r
- *\r
- * - __FPU_PRESENT:\r
- *\r
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries\r
- *\r
- * <hr>\r
- * CMSIS-DSP in ARM::CMSIS Pack\r
- * -----------------------------\r
- *\r
- * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r
- * |File/Folder |Content |\r
- * |------------------------------|------------------------------------------------------------------------|\r
- * |\b CMSIS\\Documentation\\DSP | This documentation |\r
- * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |\r
- * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |\r
- * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |\r
- *\r
- * <hr>\r
- * Revision History of CMSIS-DSP\r
- * ------------\r
- * Please refer to \ref ChangeLog_pg.\r
- *\r
- * Copyright Notice\r
- * ------------\r
- *\r
- * Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r
- */\r
-\r
-\r
-/**\r
- * @defgroup groupMath Basic Math Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupFastMath Fast Math Functions\r
- * This set of functions provides a fast approximation to sine, cosine, and square root.\r
- * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
- * operate on individual values and not arrays.\r
- * There are separate functions for Q15, Q31, and floating-point data.\r
- *\r
- */\r
-\r
-/**\r
- * @defgroup groupCmplxMath Complex Math Functions\r
- * This set of functions operates on complex data vectors.\r
- * The data in the complex arrays is stored in an interleaved fashion\r
- * (real, imag, real, imag, ...).\r
- * In the API functions, the number of samples in a complex array refers\r
- * to the number of complex values; the array contains twice this number of\r
- * real values.\r
- */\r
-\r
-/**\r
- * @defgroup groupFilters Filtering Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupMatrix Matrix Functions\r
- *\r
- * This set of functions provides basic matrix math operations.\r
- * The functions operate on matrix data structures. For example,\r
- * the type\r
- * definition for the floating-point matrix structure is shown\r
- * below:\r
- * <pre>\r
- * typedef struct\r
- * {\r
- * uint16_t numRows; // number of rows of the matrix.\r
- * uint16_t numCols; // number of columns of the matrix.\r
- * float32_t *pData; // points to the data of the matrix.\r
- * } arm_matrix_instance_f32;\r
- * </pre>\r
- * There are similar definitions for Q15 and Q31 data types.\r
- *\r
- * The structure specifies the size of the matrix and then points to\r
- * an array of data. The array is of size <code>numRows X numCols</code>\r
- * and the values are arranged in row order. That is, the\r
- * matrix element (i, j) is stored at:\r
- * <pre>\r
- * pData[i*numCols + j]\r
- * </pre>\r
- *\r
- * \par Init Functions\r
- * There is an associated initialization function for each type of matrix\r
- * data structure.\r
- * The initialization function sets the values of the internal structure fields.\r
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
- *\r
- * \par\r
- * Use of the initialization function is optional. However, if initialization function is used\r
- * then the instance structure cannot be placed into a const data section.\r
- * To place the instance structure in a const data\r
- * section, manually initialize the data structure. For example:\r
- * <pre>\r
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
- * </pre>\r
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
- * specifies the number of columns, and <code>pData</code> points to the\r
- * data array.\r
- *\r
- * \par Size Checking\r
- * By default all of the matrix functions perform size checking on the input and\r
- * output matrices. For example, the matrix addition function verifies that the\r
- * two input matrices and the output matrix all have the same number of rows and\r
- * columns. If the size check fails the functions return:\r
- * <pre>\r
- * ARM_MATH_SIZE_MISMATCH\r
- * </pre>\r
- * Otherwise the functions return\r
- * <pre>\r
- * ARM_MATH_SUCCESS\r
- * </pre>\r
- * There is some overhead associated with this matrix size checking.\r
- * The matrix size checking is enabled via the \#define\r
- * <pre>\r
- * ARM_MATH_MATRIX_CHECK\r
- * </pre>\r
- * within the library project settings. By default this macro is defined\r
- * and size checking is enabled. By changing the project settings and\r
- * undefining this macro size checking is eliminated and the functions\r
- * run a bit faster. With size checking disabled the functions always\r
- * return <code>ARM_MATH_SUCCESS</code>.\r
- */\r
-\r
-/**\r
- * @defgroup groupTransforms Transform Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupController Controller Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupStats Statistics Functions\r
- */\r
-/**\r
- * @defgroup groupSupport Support Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupInterpolation Interpolation Functions\r
- * These functions perform 1- and 2-dimensional interpolation of data.\r
- * Linear interpolation is used for 1-dimensional data and\r
- * bilinear interpolation is used for 2-dimensional data.\r
- */\r
-\r
-/**\r
- * @defgroup groupExamples Examples\r
- */\r
-#ifndef _ARM_MATH_H\r
-#define _ARM_MATH_H\r
-\r
-/* ignore some GCC warnings */\r
-#if defined ( __GNUC__ )\r
-#pragma GCC diagnostic push\r
-#pragma GCC diagnostic ignored "-Wsign-conversion"\r
-#pragma GCC diagnostic ignored "-Wconversion"\r
-#pragma GCC diagnostic ignored "-Wunused-parameter"\r
-#endif\r
-\r
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
-\r
-#if defined(ARM_MATH_CM7)\r
- #include "core_cm7.h"\r
-#elif defined (ARM_MATH_CM4)\r
- #include "core_cm4.h"\r
-#elif defined (ARM_MATH_CM3)\r
- #include "core_cm3.h"\r
-#elif defined (ARM_MATH_CM0)\r
- #include "core_cm0.h"\r
- #define ARM_MATH_CM0_FAMILY\r
-#elif defined (ARM_MATH_CM0PLUS)\r
- #include "core_cm0plus.h"\r
- #define ARM_MATH_CM0_FAMILY\r
-#else\r
- #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"\r
-#endif\r
-\r
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
-#include "string.h"\r
-#include "math.h"\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
- /**\r
- * @brief Macros required for reciprocal calculation in Normalized LMS\r
- */\r
-\r
-#define DELTA_Q31 (0x100)\r
-#define DELTA_Q15 0x5\r
-#define INDEX_MASK 0x0000003F\r
-#ifndef PI\r
-#define PI 3.14159265358979f\r
-#endif\r
-\r
- /**\r
- * @brief Macros required for SINE and COSINE Fast math approximations\r
- */\r
-\r
-#define FAST_MATH_TABLE_SIZE 512\r
-#define FAST_MATH_Q31_SHIFT (32 - 10)\r
-#define FAST_MATH_Q15_SHIFT (16 - 10)\r
-#define CONTROLLER_Q31_SHIFT (32 - 9)\r
-#define TABLE_SIZE 256\r
-#define TABLE_SPACING_Q31 0x400000\r
-#define TABLE_SPACING_Q15 0x80\r
-\r
- /**\r
- * @brief Macros required for SINE and COSINE Controller functions\r
- */\r
- /* 1.31(q31) Fixed value of 2/360 */\r
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
-#define INPUT_SPACING 0xB60B61\r
-\r
- /**\r
- * @brief Macro for Unaligned Support\r
- */\r
-#ifndef UNALIGNED_SUPPORT_DISABLE\r
- #define ALIGN4\r
-#else\r
- #if defined (__GNUC__)\r
- #define ALIGN4 __attribute__((aligned(4)))\r
- #else\r
- #define ALIGN4 __align(4)\r
- #endif\r
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r
-\r
- /**\r
- * @brief Error status returned by some functions in the library.\r
- */\r
-\r
- typedef enum\r
- {\r
- ARM_MATH_SUCCESS = 0, /**< No error */\r
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
- } arm_status;\r
-\r
- /**\r
- * @brief 8-bit fractional data type in 1.7 format.\r
- */\r
- typedef int8_t q7_t;\r
-\r
- /**\r
- * @brief 16-bit fractional data type in 1.15 format.\r
- */\r
- typedef int16_t q15_t;\r
-\r
- /**\r
- * @brief 32-bit fractional data type in 1.31 format.\r
- */\r
- typedef int32_t q31_t;\r
-\r
- /**\r
- * @brief 64-bit fractional data type in 1.63 format.\r
- */\r
- typedef int64_t q63_t;\r
-\r
- /**\r
- * @brief 32-bit floating-point type definition.\r
- */\r
- typedef float float32_t;\r
-\r
- /**\r
- * @brief 64-bit floating-point type definition.\r
- */\r
- typedef double float64_t;\r
-\r
- /**\r
- * @brief definition to read/write two 16 bit values.\r
- */\r
-#if defined __CC_ARM\r
- #define __SIMD32_TYPE int32_t __packed\r
- #define CMSIS_UNUSED __attribute__((unused))\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED __attribute__((unused))\r
-\r
-#elif defined __GNUC__\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED __attribute__((unused))\r
-\r
-#elif defined __ICCARM__\r
- #define __SIMD32_TYPE int32_t __packed\r
- #define CMSIS_UNUSED\r
-\r
-#elif defined __CSMC__\r
- #define __SIMD32_TYPE int32_t\r
- #define CMSIS_UNUSED\r
-\r
-#elif defined __TASKING__\r
- #define __SIMD32_TYPE __unaligned int32_t\r
- #define CMSIS_UNUSED\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
-#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))\r
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))\r
-#define __SIMD64(addr) (*(int64_t **) & (addr))\r
-\r
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r
- /**\r
- * @brief definition to pack two 16 bit values.\r
- */\r
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \\r
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )\r
-\r
-#endif\r
-\r
-\r
- /**\r
- * @brief definition to pack four 8 bit values.\r
- */\r
-#ifndef ARM_MATH_BIG_ENDIAN\r
-\r
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
-#else\r
-\r
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
-\r
-#endif\r
-\r
-\r
- /**\r
- * @brief Clips Q63 to Q31 values.\r
- */\r
- static __INLINE q31_t clip_q63_to_q31(\r
- q63_t x)\r
- {\r
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
- }\r
-\r
- /**\r
- * @brief Clips Q63 to Q15 values.\r
- */\r
- static __INLINE q15_t clip_q63_to_q15(\r
- q63_t x)\r
- {\r
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
- }\r
-\r
- /**\r
- * @brief Clips Q31 to Q7 values.\r
- */\r
- static __INLINE q7_t clip_q31_to_q7(\r
- q31_t x)\r
- {\r
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
- }\r
-\r
- /**\r
- * @brief Clips Q31 to Q15 values.\r
- */\r
- static __INLINE q15_t clip_q31_to_q15(\r
- q31_t x)\r
- {\r
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
- }\r
-\r
- /**\r
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
- */\r
-\r
- static __INLINE q63_t mult32x64(\r
- q63_t x,\r
- q31_t y)\r
- {\r
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
- (((q63_t) (x >> 32) * y)));\r
- }\r
-\r
-/*\r
- #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )\r
- #define __CLZ __clz\r
- #endif\r
- */\r
-/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */\r
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )\r
- static __INLINE uint32_t __CLZ(\r
- q31_t data);\r
-\r
- static __INLINE uint32_t __CLZ(\r
- q31_t data)\r
- {\r
- uint32_t count = 0;\r
- uint32_t mask = 0x80000000;\r
-\r
- while((data & mask) == 0)\r
- {\r
- count += 1u;\r
- mask = mask >> 1u;\r
- }\r
-\r
- return (count);\r
- }\r
-#endif\r
-\r
- /**\r
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r
- */\r
-\r
- static __INLINE uint32_t arm_recip_q31(\r
- q31_t in,\r
- q31_t * dst,\r
- q31_t * pRecipTable)\r
- {\r
- q31_t out;\r
- uint32_t tempVal;\r
- uint32_t index, i;\r
- uint32_t signBits;\r
-\r
- if(in > 0)\r
- {\r
- signBits = ((uint32_t) (__CLZ( in) - 1));\r
- }\r
- else\r
- {\r
- signBits = ((uint32_t) (__CLZ(-in) - 1));\r
- }\r
-\r
- /* Convert input sample to 1.31 format */\r
- in = (in << signBits);\r
-\r
- /* calculation of index for initial approximated Val */\r
- index = (uint32_t)(in >> 24);\r
- index = (index & INDEX_MASK);\r
-\r
- /* 1.31 with exp 1 */\r
- out = pRecipTable[index];\r
-\r
- /* calculation of reciprocal value */\r
- /* running approximation for two iterations */\r
- for (i = 0u; i < 2u; i++)\r
- {\r
- tempVal = (uint32_t) (((q63_t) in * out) >> 31);\r
- tempVal = 0x7FFFFFFFu - tempVal;\r
- /* 1.31 with exp 1 */\r
- /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\r
- out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\r
- }\r
-\r
- /* write output */\r
- *dst = out;\r
-\r
- /* return num of signbits of out = 1/in value */\r
- return (signBits + 1u);\r
- }\r
-\r
-\r
- /**\r
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r
- */\r
- static __INLINE uint32_t arm_recip_q15(\r
- q15_t in,\r
- q15_t * dst,\r
- q15_t * pRecipTable)\r
- {\r
- q15_t out = 0;\r
- uint32_t tempVal = 0;\r
- uint32_t index = 0, i = 0;\r
- uint32_t signBits = 0;\r
-\r
- if(in > 0)\r
- {\r
- signBits = ((uint32_t)(__CLZ( in) - 17));\r
- }\r
- else\r
- {\r
- signBits = ((uint32_t)(__CLZ(-in) - 17));\r
- }\r
-\r
- /* Convert input sample to 1.15 format */\r
- in = (in << signBits);\r
-\r
- /* calculation of index for initial approximated Val */\r
- index = (uint32_t)(in >> 8);\r
- index = (index & INDEX_MASK);\r
-\r
- /* 1.15 with exp 1 */\r
- out = pRecipTable[index];\r
-\r
- /* calculation of reciprocal value */\r
- /* running approximation for two iterations */\r
- for (i = 0u; i < 2u; i++)\r
- {\r
- tempVal = (uint32_t) (((q31_t) in * out) >> 15);\r
- tempVal = 0x7FFFu - tempVal;\r
- /* 1.15 with exp 1 */\r
- out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
- /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\r
- }\r
-\r
- /* write output */\r
- *dst = out;\r
-\r
- /* return num of signbits of out = 1/in value */\r
- return (signBits + 1);\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined intrinisic function for only M0 processors\r
- */\r
-#if defined(ARM_MATH_CM0_FAMILY)\r
- static __INLINE q31_t __SSAT(\r
- q31_t x,\r
- uint32_t y)\r
- {\r
- int32_t posMax, negMin;\r
- uint32_t i;\r
-\r
- posMax = 1;\r
- for (i = 0; i < (y - 1); i++)\r
- {\r
- posMax = posMax * 2;\r
- }\r
-\r
- if(x > 0)\r
- {\r
- posMax = (posMax - 1);\r
-\r
- if(x > posMax)\r
- {\r
- x = posMax;\r
- }\r
- }\r
- else\r
- {\r
- negMin = -posMax;\r
-\r
- if(x < negMin)\r
- {\r
- x = negMin;\r
- }\r
- }\r
- return (x);\r
- }\r
-#endif /* end of ARM_MATH_CM0_FAMILY */\r
-\r
-\r
- /*\r
- * @brief C custom defined intrinsic function for M3 and M0 processors\r
- */\r
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r
-\r
- /*\r
- * @brief C custom defined QADD8 for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __QADD8(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s, t, u;\r
-\r
- r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
- s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
- t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
- u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
-\r
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSUB8 for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __QSUB8(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s, t, u;\r
-\r
- r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
- s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
- t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
- u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
-\r
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QADD16 for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __QADD16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
-/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */\r
- q31_t r = 0, s = 0;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHADD16 for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SHADD16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSUB16 for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __QSUB16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHSUB16 for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SHSUB16(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QASX for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __QASX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHASX for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SHASX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSAX for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __QSAX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SHSAX for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SHSAX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- q31_t r, s;\r
-\r
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
- s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
-\r
- return ((uint32_t)((s << 16) | (r )));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMUSDX for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SMUSDX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMUADX for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SMUADX(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QADD for M3 and M0 processors\r
- */\r
- static __INLINE int32_t __QADD(\r
- int32_t x,\r
- int32_t y)\r
- {\r
- return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSUB for M3 and M0 processors\r
- */\r
- static __INLINE int32_t __QSUB(\r
- int32_t x,\r
- int32_t y)\r
- {\r
- return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLAD for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SMLAD(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t sum)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
- ( ((q31_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLADX for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SMLADX(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t sum)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ( ((q31_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLSDX for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SMLSDX(\r
- uint32_t x,\r
- uint32_t y,\r
- uint32_t sum)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ( ((q31_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLALD for M3 and M0 processors\r
- */\r
- static __INLINE uint64_t __SMLALD(\r
- uint32_t x,\r
- uint32_t y,\r
- uint64_t sum)\r
- {\r
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\r
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
- ( ((q63_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMLALDX for M3 and M0 processors\r
- */\r
- static __INLINE uint64_t __SMLALDX(\r
- uint32_t x,\r
- uint32_t y,\r
- uint64_t sum)\r
- {\r
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\r
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ( ((q63_t)sum ) ) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMUAD for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SMUAD(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SMUSD for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SMUSD(\r
- uint32_t x,\r
- uint32_t y)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\r
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SXTB16 for M3 and M0 processors\r
- */\r
- static __INLINE uint32_t __SXTB16(\r
- uint32_t x)\r
- {\r
- return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\r
- ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));\r
- }\r
-\r
-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q7 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- } arm_fir_instance_q7;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- } arm_fir_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- } arm_fir_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- } arm_fir_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q7 FIR filter.\r
- * @param[in] S points to an instance of the Q7 FIR filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_q7(\r
- const arm_fir_instance_q7 * S,\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q7 FIR filter.\r
- * @param[in,out] S points to an instance of the Q7 FIR structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed.\r
- */\r
- void arm_fir_init_q7(\r
- arm_fir_instance_q7 * S,\r
- uint16_t numTaps,\r
- q7_t * pCoeffs,\r
- q7_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR filter.\r
- * @param[in] S points to an instance of the Q15 FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_q15(\r
- const arm_fir_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q15 FIR filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_fast_q15(\r
- const arm_fir_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR filter.\r
- * @param[in,out] S points to an instance of the Q15 FIR filter structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>numTaps</code> is not a supported value.\r
- */\r
- arm_status arm_fir_init_q15(\r
- arm_fir_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR filter.\r
- * @param[in] S points to an instance of the Q31 FIR filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_q31(\r
- const arm_fir_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q31 FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_fast_q31(\r
- const arm_fir_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR filter.\r
- * @param[in,out] S points to an instance of the Q31 FIR structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- */\r
- void arm_fir_init_q31(\r
- arm_fir_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR filter.\r
- * @param[in] S points to an instance of the floating-point FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_f32(\r
- const arm_fir_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR filter.\r
- * @param[in,out] S points to an instance of the floating-point FIR filter structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- */\r
- void arm_fir_init_f32(\r
- arm_fir_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
- } arm_biquad_casd_df1_inst_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
- } arm_biquad_casd_df1_inst_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_casd_df1_inst_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 Biquad cascade filter.\r
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_q15(\r
- const arm_biquad_casd_df1_inst_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
- */\r
- void arm_biquad_cascade_df1_init_q15(\r
- arm_biquad_casd_df1_inst_q15 * S,\r
- uint8_t numStages,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- int8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_fast_q15(\r
- const arm_biquad_casd_df1_inst_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 Biquad cascade filter\r
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_q31(\r
- const arm_biquad_casd_df1_inst_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_fast_q31(\r
- const arm_biquad_casd_df1_inst_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
- */\r
- void arm_biquad_cascade_df1_init_q31(\r
- arm_biquad_casd_df1_inst_q31 * S,\r
- uint8_t numStages,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- int8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point Biquad cascade filter.\r
- * @param[in] S points to an instance of the floating-point Biquad cascade structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df1_f32(\r
- const arm_biquad_casd_df1_inst_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_df1_init_f32(\r
- arm_biquad_casd_df1_inst_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- float32_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- float64_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_f64;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- q15_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 matrix structure.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- q31_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix addition.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_add_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix addition.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_add_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix addition.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_add_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point, complex, matrix multiplication.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_cmplx_mult_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15, complex, matrix multiplication.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_cmplx_mult_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Q31, complex, matrix multiplication.\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_cmplx_mult_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix transpose.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_trans_f32(\r
- const arm_matrix_instance_f32 * pSrc,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix transpose.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_trans_q15(\r
- const arm_matrix_instance_q15 * pSrc,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix transpose.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_trans_q31(\r
- const arm_matrix_instance_q31 * pSrc,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix multiplication\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix multiplication\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @param[in] pState points to the array for storing intermediate results\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @param[in] pState points to the array for storing intermediate results\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_fast_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix multiplication\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_mult_fast_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix subtraction\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_sub_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix subtraction\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_sub_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix subtraction\r
- * @param[in] pSrcA points to the first input matrix structure\r
- * @param[in] pSrcB points to the second input matrix structure\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_sub_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix scaling.\r
- * @param[in] pSrc points to the input matrix\r
- * @param[in] scale scale factor\r
- * @param[out] pDst points to the output matrix\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_scale_f32(\r
- const arm_matrix_instance_f32 * pSrc,\r
- float32_t scale,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix scaling.\r
- * @param[in] pSrc points to input matrix\r
- * @param[in] scaleFract fractional portion of the scale factor\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to output matrix\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_scale_q15(\r
- const arm_matrix_instance_q15 * pSrc,\r
- q15_t scaleFract,\r
- int32_t shift,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix scaling.\r
- * @param[in] pSrc points to input matrix\r
- * @param[in] scaleFract fractional portion of the scale factor\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
- arm_status arm_mat_scale_q31(\r
- const arm_matrix_instance_q31 * pSrc,\r
- q31_t scaleFract,\r
- int32_t shift,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix initialization.\r
- * @param[in,out] S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] pData points to the matrix data array.\r
- */\r
- void arm_mat_init_q31(\r
- arm_matrix_instance_q31 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- q31_t * pData);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix initialization.\r
- * @param[in,out] S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] pData points to the matrix data array.\r
- */\r
- void arm_mat_init_q15(\r
- arm_matrix_instance_q15 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- q15_t * pData);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix initialization.\r
- * @param[in,out] S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] pData points to the matrix data array.\r
- */\r
- void arm_mat_init_f32(\r
- arm_matrix_instance_f32 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- float32_t * pData);\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 PID Control.\r
- */\r
- typedef struct\r
- {\r
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
-#ifdef ARM_MATH_CM0_FAMILY\r
- q15_t A1;\r
- q15_t A2;\r
-#else\r
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
-#endif\r
- q15_t state[3]; /**< The state array of length 3. */\r
- q15_t Kp; /**< The proportional gain. */\r
- q15_t Ki; /**< The integral gain. */\r
- q15_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 PID Control.\r
- */\r
- typedef struct\r
- {\r
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
- q31_t A2; /**< The derived gain, A2 = Kd . */\r
- q31_t state[3]; /**< The state array of length 3. */\r
- q31_t Kp; /**< The proportional gain. */\r
- q31_t Ki; /**< The integral gain. */\r
- q31_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point PID Control.\r
- */\r
- typedef struct\r
- {\r
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
- float32_t A2; /**< The derived gain, A2 = Kd . */\r
- float32_t state[3]; /**< The state array of length 3. */\r
- float32_t Kp; /**< The proportional gain. */\r
- float32_t Ki; /**< The integral gain. */\r
- float32_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_f32;\r
-\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point PID Control.\r
- * @param[in,out] S points to an instance of the PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- */\r
- void arm_pid_init_f32(\r
- arm_pid_instance_f32 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the floating-point PID Control.\r
- * @param[in,out] S is an instance of the floating-point PID Control structure\r
- */\r
- void arm_pid_reset_f32(\r
- arm_pid_instance_f32 * S);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 PID Control.\r
- * @param[in,out] S points to an instance of the Q15 PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- */\r
- void arm_pid_init_q31(\r
- arm_pid_instance_q31 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the Q31 PID Control.\r
- * @param[in,out] S points to an instance of the Q31 PID Control structure\r
- */\r
-\r
- void arm_pid_reset_q31(\r
- arm_pid_instance_q31 * S);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 PID Control.\r
- * @param[in,out] S points to an instance of the Q15 PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- */\r
- void arm_pid_init_q15(\r
- arm_pid_instance_q15 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the Q15 PID Control.\r
- * @param[in,out] S points to an instance of the q15 PID Control structure\r
- */\r
- void arm_pid_reset_q15(\r
- arm_pid_instance_q15 * S);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point Linear Interpolate function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t nValues; /**< nValues */\r
- float32_t x1; /**< x1 */\r
- float32_t xSpacing; /**< xSpacing */\r
- float32_t *pYData; /**< pointer to the table of Y values */\r
- } arm_linear_interp_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- float32_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q31_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q15_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 bilinear interpolation function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q7_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q7;\r
-\r
-\r
- /**\r
- * @brief Q7 vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector multiplication.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_mult_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix2_instance_q15;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_q15(\r
- arm_cfft_radix2_instance_q15 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_q15(\r
- const arm_cfft_radix2_instance_q15 * S,\r
- q15_t * pSrc);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix4_instance_q15;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_q15(\r
- arm_cfft_radix4_instance_q15 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_q15(\r
- const arm_cfft_radix4_instance_q15 * S,\r
- q15_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix2_instance_q31;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_q31(\r
- arm_cfft_radix2_instance_q31 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_q31(\r
- const arm_cfft_radix2_instance_q31 * S,\r
- q31_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix4_instance_q31;\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_q31(\r
- const arm_cfft_radix4_instance_q31 * S,\r
- q31_t * pSrc);\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_q31(\r
- arm_cfft_radix4_instance_q31 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- float32_t onebyfftLen; /**< value of 1/fftLen. */\r
- } arm_cfft_radix2_instance_f32;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_f32(\r
- arm_cfft_radix2_instance_f32 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_f32(\r
- const arm_cfft_radix2_instance_f32 * S,\r
- float32_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- float32_t onebyfftLen; /**< value of 1/fftLen. */\r
- } arm_cfft_radix4_instance_f32;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_f32(\r
- arm_cfft_radix4_instance_f32 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_f32(\r
- const arm_cfft_radix4_instance_f32 * S,\r
- float32_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const q15_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_q15;\r
-\r
-void arm_cfft_q15(\r
- const arm_cfft_instance_q15 * S,\r
- q15_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_q31;\r
-\r
-void arm_cfft_q31(\r
- const arm_cfft_instance_q31 * S,\r
- q31_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_f32;\r
-\r
- void arm_cfft_f32(\r
- const arm_cfft_instance_f32 * S,\r
- float32_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_q15;\r
-\r
- arm_status arm_rfft_init_q15(\r
- arm_rfft_instance_q15 * S,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_q15(\r
- const arm_rfft_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_q31;\r
-\r
- arm_status arm_rfft_init_q31(\r
- arm_rfft_instance_q31 * S,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_q31(\r
- const arm_rfft_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint16_t fftLenBy2; /**< length of the complex FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_f32;\r
-\r
- arm_status arm_rfft_init_f32(\r
- arm_rfft_instance_f32 * S,\r
- arm_cfft_radix4_instance_f32 * S_CFFT,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_f32(\r
- const arm_rfft_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
- */\r
-typedef struct\r
- {\r
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */\r
- uint16_t fftLenRFFT; /**< length of the real sequence */\r
- float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */\r
- } arm_rfft_fast_instance_f32 ;\r
-\r
-arm_status arm_rfft_fast_init_f32 (\r
- arm_rfft_fast_instance_f32 * S,\r
- uint16_t fftLen);\r
-\r
-void arm_rfft_fast_f32(\r
- arm_rfft_fast_instance_f32 * S,\r
- float32_t * p, float32_t * pOut,\r
- uint8_t ifftFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- float32_t normalize; /**< normalizing factor. */\r
- float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
- float32_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point DCT4/IDCT4.\r
- * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.\r
- * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
- * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
- */\r
- arm_status arm_dct4_init_f32(\r
- arm_dct4_instance_f32 * S,\r
- arm_rfft_instance_f32 * S_RFFT,\r
- arm_cfft_radix4_instance_f32 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- float32_t normalize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point DCT4/IDCT4.\r
- * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.\r
- * @param[in] pState points to state buffer.\r
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
- */\r
- void arm_dct4_f32(\r
- const arm_dct4_instance_f32 * S,\r
- float32_t * pState,\r
- float32_t * pInlineBuffer);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- q31_t normalize; /**< normalizing factor. */\r
- q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
- q31_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 DCT4/IDCT4.\r
- * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.\r
- * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
- * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
- */\r
- arm_status arm_dct4_init_q31(\r
- arm_dct4_instance_q31 * S,\r
- arm_rfft_instance_q31 * S_RFFT,\r
- arm_cfft_radix4_instance_q31 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- q31_t normalize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 DCT4/IDCT4.\r
- * @param[in] S points to an instance of the Q31 DCT4 structure.\r
- * @param[in] pState points to state buffer.\r
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
- */\r
- void arm_dct4_q31(\r
- const arm_dct4_instance_q31 * S,\r
- q31_t * pState,\r
- q31_t * pInlineBuffer);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
- */\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- q15_t normalize; /**< normalizing factor. */\r
- q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
- q15_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 DCT4/IDCT4.\r
- * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.\r
- * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
- * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
- */\r
- arm_status arm_dct4_init_q15(\r
- arm_dct4_instance_q15 * S,\r
- arm_rfft_instance_q15 * S_RFFT,\r
- arm_cfft_radix4_instance_q15 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- q15_t normalize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 DCT4/IDCT4.\r
- * @param[in] S points to an instance of the Q15 DCT4 structure.\r
- * @param[in] pState points to state buffer.\r
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
- */\r
- void arm_dct4_q15(\r
- const arm_dct4_instance_q15 * S,\r
- q15_t * pState,\r
- q15_t * pInlineBuffer);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q7 vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector addition.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_add_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q7 vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector subtraction.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_sub_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a floating-point vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scale scale factor to be applied\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_f32(\r
- float32_t * pSrc,\r
- float32_t scale,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a Q7 vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_q7(\r
- q7_t * pSrc,\r
- q7_t scaleFract,\r
- int8_t shift,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a Q15 vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_q15(\r
- q15_t * pSrc,\r
- q15_t scaleFract,\r
- int8_t shift,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Multiplies a Q31 vector by a scalar.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_scale_q31(\r
- q31_t * pSrc,\r
- q31_t scaleFract,\r
- int8_t shift,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q7 vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q15 vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Q31 vector absolute value.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[out] pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- */\r
- void arm_abs_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Dot product of floating-point vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- uint32_t blockSize,\r
- float32_t * result);\r
-\r
-\r
- /**\r
- * @brief Dot product of Q7 vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- uint32_t blockSize,\r
- q31_t * result);\r
-\r
-\r
- /**\r
- * @brief Dot product of Q15 vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- uint32_t blockSize,\r
- q63_t * result);\r
-\r
-\r
- /**\r
- * @brief Dot product of Q31 vectors.\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] result output result returned here\r
- */\r
- void arm_dot_prod_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- uint32_t blockSize,\r
- q63_t * result);\r
-\r
-\r
- /**\r
- * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_shift_q7(\r
- q7_t * pSrc,\r
- int8_t shiftBits,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_shift_q15(\r
- q15_t * pSrc,\r
- int8_t shiftBits,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_shift_q31(\r
- q31_t * pSrc,\r
- int8_t shiftBits,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a floating-point vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_f32(\r
- float32_t * pSrc,\r
- float32_t offset,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q7 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_q7(\r
- q7_t * pSrc,\r
- q7_t offset,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q15 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_q15(\r
- q15_t * pSrc,\r
- q15_t offset,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q31 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_offset_q31(\r
- q31_t * pSrc,\r
- q31_t offset,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a floating-point vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a Q7 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a Q15 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Negates the elements of a Q31 vector.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- */\r
- void arm_negate_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a floating-point vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a Q7 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a Q15 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Copies the elements of a Q31 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_copy_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a floating-point vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_f32(\r
- float32_t value,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a Q7 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_q7(\r
- q7_t value,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a Q15 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_q15(\r
- q15_t value,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Fills a constant value into a Q31 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_fill_q31(\r
- q31_t value,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Convolution of floating-point sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- */\r
- void arm_conv_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-/**\r
- * @brief Convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- */\r
- void arm_conv_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q31 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- */\r
- void arm_conv_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
- */\r
- void arm_conv_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of floating-point sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q31 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q7 sequences\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-/**\r
- * @brief Partial convolution of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
- arm_status arm_conv_partial_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR decimator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR decimator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR decimator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR decimator.\r
- * @param[in] S points to an instance of the floating-point FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_f32(\r
- const arm_fir_decimate_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR decimator.\r
- * @param[in,out] S points to an instance of the floating-point FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
- arm_status arm_fir_decimate_init_f32(\r
- arm_fir_decimate_instance_f32 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR decimator.\r
- * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_q15(\r
- const arm_fir_decimate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_fast_q15(\r
- const arm_fir_decimate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR decimator.\r
- * @param[in,out] S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
- arm_status arm_fir_decimate_init_q15(\r
- arm_fir_decimate_instance_q15 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR decimator.\r
- * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_q31(\r
- const arm_fir_decimate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
- * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_decimate_fast_q31(\r
- arm_fir_decimate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR decimator.\r
- * @param[in,out] S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
- arm_status arm_fir_decimate_init_q31(\r
- arm_fir_decimate_instance_q31 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR interpolator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
- } arm_fir_interpolate_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR interpolator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
- } arm_fir_interpolate_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR interpolator.\r
- */\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
- } arm_fir_interpolate_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR interpolator.\r
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_interpolate_q15(\r
- const arm_fir_interpolate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR interpolator.\r
- * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
- arm_status arm_fir_interpolate_init_q15(\r
- arm_fir_interpolate_instance_q15 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR interpolator.\r
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_interpolate_q31(\r
- const arm_fir_interpolate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR interpolator.\r
- * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
- arm_status arm_fir_interpolate_init_q31(\r
- arm_fir_interpolate_instance_q31 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR interpolator.\r
- * @param[in] S points to an instance of the floating-point FIR interpolator structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_interpolate_f32(\r
- const arm_fir_interpolate_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR interpolator.\r
- * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] pCoeffs points to the filter coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
- arm_status arm_fir_interpolate_init_f32(\r
- arm_fir_interpolate_instance_f32 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
- } arm_biquad_cas_df1_32x64_ins_q31;\r
-\r
-\r
- /**\r
- * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cas_df1_32x64_q31(\r
- const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
- */\r
- void arm_biquad_cas_df1_32x64_init_q31(\r
- arm_biquad_cas_df1_32x64_ins_q31 * S,\r
- uint8_t numStages,\r
- q31_t * pCoeffs,\r
- q63_t * pState,\r
- uint8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_df2T_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_stereo_df2T_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
- float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_df2T_instance_f64;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in] S points to an instance of the filter data structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df2T_f32(\r
- const arm_biquad_cascade_df2T_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r
- * @param[in] S points to an instance of the filter data structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_stereo_df2T_f32(\r
- const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in] S points to an instance of the filter data structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_biquad_cascade_df2T_f64(\r
- const arm_biquad_cascade_df2T_instance_f64 * S,\r
- float64_t * pSrc,\r
- float64_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_df2T_init_f32(\r
- arm_biquad_cascade_df2T_instance_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_stereo_df2T_init_f32(\r
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] pCoeffs points to the filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- */\r
- void arm_biquad_cascade_df2T_init_f64(\r
- arm_biquad_cascade_df2T_instance_f64 * S,\r
- uint8_t numStages,\r
- float64_t * pCoeffs,\r
- float64_t * pState);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] pState points to the state buffer. The array is of length numStages.\r
- */\r
- void arm_fir_lattice_init_q15(\r
- arm_fir_lattice_instance_q15 * S,\r
- uint16_t numStages,\r
- q15_t * pCoeffs,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_lattice_q15(\r
- const arm_fir_lattice_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] pState points to the state buffer. The array is of length numStages.\r
- */\r
- void arm_fir_lattice_init_q31(\r
- arm_fir_lattice_instance_q31 * S,\r
- uint16_t numStages,\r
- q31_t * pCoeffs,\r
- q31_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_lattice_q31(\r
- const arm_fir_lattice_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Initialization function for the floating-point FIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] pState points to the state buffer. The array is of length numStages.\r
- */\r
- void arm_fir_lattice_init_f32(\r
- arm_fir_lattice_instance_f32 * S,\r
- uint16_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_fir_lattice_f32(\r
- const arm_fir_lattice_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point IIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_f32(\r
- const arm_iir_lattice_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point IIR lattice filter.\r
- * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_init_f32(\r
- arm_iir_lattice_instance_f32 * S,\r
- uint16_t numStages,\r
- float32_t * pkCoeffs,\r
- float32_t * pvCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 IIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_q31(\r
- const arm_iir_lattice_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 IIR lattice filter.\r
- * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_init_q31(\r
- arm_iir_lattice_instance_q31 * S,\r
- uint16_t numStages,\r
- q31_t * pkCoeffs,\r
- q31_t * pvCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 IIR lattice filter.\r
- * @param[in] S points to an instance of the Q15 IIR lattice structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_iir_lattice_q15(\r
- const arm_iir_lattice_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Initialization function for the Q15 IIR lattice filter.\r
- * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] pState points to state buffer. The array is of length numStages+blockSize.\r
- * @param[in] blockSize number of samples to process per call.\r
- */\r
- void arm_iir_lattice_init_q15(\r
- arm_iir_lattice_instance_q15 * S,\r
- uint16_t numStages,\r
- q15_t * pkCoeffs,\r
- q15_t * pvCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- float32_t mu; /**< step size that controls filter coefficient updates. */\r
- } arm_lms_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for floating-point LMS filter.\r
- * @param[in] S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_f32(\r
- const arm_lms_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pRef,\r
- float32_t * pOut,\r
- float32_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for floating-point LMS filter.\r
- * @param[in] S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to the coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_init_f32(\r
- arm_lms_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- float32_t mu,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q15_t mu; /**< step size that controls filter coefficient updates. */\r
- uint32_t postShift; /**< bit shift applied to coefficients. */\r
- } arm_lms_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 LMS filter.\r
- * @param[in] S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to the coefficient buffer.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_init_q15(\r
- arm_lms_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- q15_t mu,\r
- uint32_t blockSize,\r
- uint32_t postShift);\r
-\r
-\r
- /**\r
- * @brief Processing function for Q15 LMS filter.\r
- * @param[in] S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_q15(\r
- const arm_lms_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pRef,\r
- q15_t * pOut,\r
- q15_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q31_t mu; /**< step size that controls filter coefficient updates. */\r
- uint32_t postShift; /**< bit shift applied to coefficients. */\r
- } arm_lms_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Processing function for Q31 LMS filter.\r
- * @param[in] S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_q31(\r
- const arm_lms_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pRef,\r
- q31_t * pOut,\r
- q31_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q31 LMS filter.\r
- * @param[in] S points to an instance of the Q31 LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_init_q31(\r
- arm_lms_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- q31_t mu,\r
- uint32_t blockSize,\r
- uint32_t postShift);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- float32_t mu; /**< step size that control filter coefficient updates. */\r
- float32_t energy; /**< saves previous frame energy. */\r
- float32_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for floating-point normalized LMS filter.\r
- * @param[in] S points to an instance of the floating-point normalized LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_f32(\r
- arm_lms_norm_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pRef,\r
- float32_t * pOut,\r
- float32_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for floating-point normalized LMS filter.\r
- * @param[in] S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_init_f32(\r
- arm_lms_norm_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- float32_t mu,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q31_t mu; /**< step size that controls filter coefficient updates. */\r
- uint8_t postShift; /**< bit shift applied to coefficients. */\r
- q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
- q31_t energy; /**< saves previous frame energy. */\r
- q31_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_q31;\r
-\r
-\r
- /**\r
- * @brief Processing function for Q31 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_q31(\r
- arm_lms_norm_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pRef,\r
- q31_t * pOut,\r
- q31_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q31 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_norm_init_q31(\r
- arm_lms_norm_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- q31_t mu,\r
- uint32_t blockSize,\r
- uint8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< Number of coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q15_t mu; /**< step size that controls filter coefficient updates. */\r
- uint8_t postShift; /**< bit shift applied to coefficients. */\r
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
- q15_t energy; /**< saves previous frame energy. */\r
- q15_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Processing function for Q15 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[in] pRef points to the block of reference data.\r
- * @param[out] pOut points to the block of output data.\r
- * @param[out] pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- */\r
- void arm_lms_norm_q15(\r
- arm_lms_norm_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pRef,\r
- q15_t * pOut,\r
- q15_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q15 normalized LMS filter.\r
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] pCoeffs points to coefficient buffer.\r
- * @param[in] pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- */\r
- void arm_lms_norm_init_q15(\r
- arm_lms_norm_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- q15_t mu,\r
- uint32_t blockSize,\r
- uint8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Correlation of floating-point sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- */\r
- void arm_correlate_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
-\r
- void arm_correlate_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
-\r
- void arm_correlate_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- */\r
- void arm_correlate_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q31 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- */\r
- void arm_correlate_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q7 sequences.\r
- * @param[in] pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- */\r
- void arm_correlate_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q7 sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q7;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point sparse FIR filter.\r
- * @param[in] S points to an instance of the floating-point sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_f32(\r
- arm_fir_sparse_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- float32_t * pScratchIn,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point sparse FIR filter.\r
- * @param[in,out] S points to an instance of the floating-point sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_f32(\r
- arm_fir_sparse_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 sparse FIR filter.\r
- * @param[in] S points to an instance of the Q31 sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_q31(\r
- arm_fir_sparse_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- q31_t * pScratchIn,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 sparse FIR filter.\r
- * @param[in,out] S points to an instance of the Q31 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_q31(\r
- arm_fir_sparse_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 sparse FIR filter.\r
- * @param[in] S points to an instance of the Q15 sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_q15(\r
- arm_fir_sparse_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- q15_t * pScratchIn,\r
- q31_t * pScratchOut,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 sparse FIR filter.\r
- * @param[in,out] S points to an instance of the Q15 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_q15(\r
- arm_fir_sparse_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q7 sparse FIR filter.\r
- * @param[in] S points to an instance of the Q7 sparse FIR structure.\r
- * @param[in] pSrc points to the block of input data.\r
- * @param[out] pDst points to the block of output data\r
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- */\r
- void arm_fir_sparse_q7(\r
- arm_fir_sparse_instance_q7 * S,\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- q7_t * pScratchIn,\r
- q31_t * pScratchOut,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q7 sparse FIR filter.\r
- * @param[in,out] S points to an instance of the Q7 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] pCoeffs points to the array of filter coefficients.\r
- * @param[in] pState points to the state buffer.\r
- * @param[in] pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- */\r
- void arm_fir_sparse_init_q7(\r
- arm_fir_sparse_instance_q7 * S,\r
- uint16_t numTaps,\r
- q7_t * pCoeffs,\r
- q7_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Floating-point sin_cos function.\r
- * @param[in] theta input value in degrees\r
- * @param[out] pSinVal points to the processed sine output.\r
- * @param[out] pCosVal points to the processed cos output.\r
- */\r
- void arm_sin_cos_f32(\r
- float32_t theta,\r
- float32_t * pSinVal,\r
- float32_t * pCosVal);\r
-\r
-\r
- /**\r
- * @brief Q31 sin_cos function.\r
- * @param[in] theta scaled input value in degrees\r
- * @param[out] pSinVal points to the processed sine output.\r
- * @param[out] pCosVal points to the processed cosine output.\r
- */\r
- void arm_sin_cos_q31(\r
- q31_t theta,\r
- q31_t * pSinVal,\r
- q31_t * pCosVal);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex conjugate.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_conj_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q31 complex conjugate.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_conj_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex conjugate.\r
- * @param[in] pSrc points to the input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_conj_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex magnitude squared\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_squared_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex magnitude squared\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_squared_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex magnitude squared\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_squared_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup PID PID Motor Control\r
- *\r
- * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
- * loop mechanism widely used in industrial control systems.\r
- * A PID controller is the most commonly used type of feedback controller.\r
- *\r
- * This set of functions implements (PID) controllers\r
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
- * of data and each call to the function returns a single processed value.\r
- * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
- * is the input sample value. The functions return the output value.\r
- *\r
- * \par Algorithm:\r
- * <pre>\r
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
- * A0 = Kp + Ki + Kd\r
- * A1 = (-Kp ) - (2 * Kd )\r
- * A2 = Kd </pre>\r
- *\r
- * \par\r
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
- *\r
- * \par\r
- * \image html PID.gif "Proportional Integral Derivative Controller"\r
- *\r
- * \par\r
- * The PID controller calculates an "error" value as the difference between\r
- * the measured output and the reference input.\r
- * The controller attempts to minimize the error by adjusting the process control inputs.\r
- * The proportional value determines the reaction to the current error,\r
- * the integral value determines the reaction based on the sum of recent errors,\r
- * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
- *\r
- * \par Instance Structure\r
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
- * A separate instance structure must be defined for each PID Controller.\r
- * There are separate instance structure declarations for each of the 3 supported data types.\r
- *\r
- * \par Reset Functions\r
- * There is also an associated reset function for each data type which clears the state array.\r
- *\r
- * \par Initialization Functions\r
- * There is also an associated initialization function for each data type.\r
- * The initialization function performs the following operations:\r
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
- * - Zeros out the values in the state buffer.\r
- *\r
- * \par\r
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
- *\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup PID\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Process function for the floating-point PID Control.\r
- * @param[in,out] S is an instance of the floating-point PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- */\r
- static __INLINE float32_t arm_pid_f32(\r
- arm_pid_instance_f32 * S,\r
- float32_t in)\r
- {\r
- float32_t out;\r
-\r
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
- out = (S->A0 * in) +\r
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
-\r
- }\r
-\r
- /**\r
- * @brief Process function for the Q31 PID Control.\r
- * @param[in,out] S points to an instance of the Q31 PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 64-bit accumulator.\r
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
- * Thus, if the accumulator result overflows it wraps around rather than clip.\r
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
- */\r
- static __INLINE q31_t arm_pid_q31(\r
- arm_pid_instance_q31 * S,\r
- q31_t in)\r
- {\r
- q63_t acc;\r
- q31_t out;\r
-\r
- /* acc = A0 * x[n] */\r
- acc = (q63_t) S->A0 * in;\r
-\r
- /* acc += A1 * x[n-1] */\r
- acc += (q63_t) S->A1 * S->state[0];\r
-\r
- /* acc += A2 * x[n-2] */\r
- acc += (q63_t) S->A2 * S->state[1];\r
-\r
- /* convert output to 1.31 format to add y[n-1] */\r
- out = (q31_t) (acc >> 31u);\r
-\r
- /* out += y[n-1] */\r
- out += S->state[2];\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
- }\r
-\r
-\r
- /**\r
- * @brief Process function for the Q15 PID Control.\r
- * @param[in,out] S points to an instance of the Q15 PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using a 64-bit internal accumulator.\r
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
- */\r
- static __INLINE q15_t arm_pid_q15(\r
- arm_pid_instance_q15 * S,\r
- q15_t in)\r
- {\r
- q63_t acc;\r
- q15_t out;\r
-\r
-#ifndef ARM_MATH_CM0_FAMILY\r
- __SIMD32_TYPE *vstate;\r
-\r
- /* Implementation of PID controller */\r
-\r
- /* acc = A0 * x[n] */\r
- acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\r
-\r
- /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
- vstate = __SIMD32_CONST(S->state);\r
- acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);\r
-#else\r
- /* acc = A0 * x[n] */\r
- acc = ((q31_t) S->A0) * in;\r
-\r
- /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
- acc += (q31_t) S->A1 * S->state[0];\r
- acc += (q31_t) S->A2 * S->state[1];\r
-#endif\r
-\r
- /* acc += y[n-1] */\r
- acc += (q31_t) S->state[2] << 15;\r
-\r
- /* saturate the output */\r
- out = (q15_t) (__SSAT((acc >> 15), 16));\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
- }\r
-\r
- /**\r
- * @} end of PID group\r
- */\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix inverse.\r
- * @param[in] src points to the instance of the input floating-point matrix structure.\r
- * @param[out] dst points to the instance of the output floating-point matrix structure.\r
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
- */\r
- arm_status arm_mat_inverse_f32(\r
- const arm_matrix_instance_f32 * src,\r
- arm_matrix_instance_f32 * dst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix inverse.\r
- * @param[in] src points to the instance of the input floating-point matrix structure.\r
- * @param[out] dst points to the instance of the output floating-point matrix structure.\r
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
- */\r
- arm_status arm_mat_inverse_f64(\r
- const arm_matrix_instance_f64 * src,\r
- arm_matrix_instance_f64 * dst);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup clarke Vector Clarke Transform\r
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
- * \image html clarke.gif Stator current space vector and its components in (a,b).\r
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html clarkeFormula.gif\r
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Clarke transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup clarke\r
- * @{\r
- */\r
-\r
- /**\r
- *\r
- * @brief Floating-point Clarke transform\r
- * @param[in] Ia input three-phase coordinate <code>a</code>\r
- * @param[in] Ib input three-phase coordinate <code>b</code>\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- */\r
- static __INLINE void arm_clarke_f32(\r
- float32_t Ia,\r
- float32_t Ib,\r
- float32_t * pIalpha,\r
- float32_t * pIbeta)\r
- {\r
- /* Calculate pIalpha using the equation, pIalpha = Ia */\r
- *pIalpha = Ia;\r
-\r
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
- *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
- }\r
-\r
-\r
- /**\r
- * @brief Clarke transform for Q31 version\r
- * @param[in] Ia input three-phase coordinate <code>a</code>\r
- * @param[in] Ib input three-phase coordinate <code>b</code>\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition, hence there is no risk of overflow.\r
- */\r
- static __INLINE void arm_clarke_q31(\r
- q31_t Ia,\r
- q31_t Ib,\r
- q31_t * pIalpha,\r
- q31_t * pIbeta)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
-\r
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
- *pIalpha = Ia;\r
-\r
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
-\r
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
-\r
- /* pIbeta is calculated by adding the intermediate products */\r
- *pIbeta = __QADD(product1, product2);\r
- }\r
-\r
- /**\r
- * @} end of clarke group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to Q31 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_q7_to_q31(\r
- q7_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup inv_clarke Vector Inverse Clarke Transform\r
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html clarkeInvFormula.gif\r
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Clarke transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup inv_clarke\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Inverse Clarke transform\r
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
- * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
- * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
- * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
- */\r
- static __INLINE void arm_inv_clarke_f32(\r
- float32_t Ialpha,\r
- float32_t Ibeta,\r
- float32_t * pIa,\r
- float32_t * pIb)\r
- {\r
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
- *pIa = Ialpha;\r
-\r
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
- *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\r
- }\r
-\r
-\r
- /**\r
- * @brief Inverse Clarke transform for Q31 version\r
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
- * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
- * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
- * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the subtraction, hence there is no risk of overflow.\r
- */\r
- static __INLINE void arm_inv_clarke_q31(\r
- q31_t Ialpha,\r
- q31_t Ibeta,\r
- q31_t * pIa,\r
- q31_t * pIb)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
-\r
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
- *pIa = Ialpha;\r
-\r
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
-\r
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
-\r
- /* pIb is calculated by subtracting the products */\r
- *pIb = __QSUB(product2, product1);\r
- }\r
-\r
- /**\r
- * @} end of inv_clarke group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to Q15 vector.\r
- * @param[in] pSrc input pointer\r
- * @param[out] pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- */\r
- void arm_q7_to_q15(\r
- q7_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup park Vector Park Transform\r
- *\r
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
- * from the stationary to the moving reference frame and control the spatial relationship between\r
- * the stator vector current and rotor flux vector.\r
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
- * current vector and the relationship from the two reference frames:\r
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html parkFormula.gif\r
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
- * cosine and sine values of theta (rotor flux position).\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Park transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup park\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Park transform\r
- * @param[in] Ialpha input two-phase vector coordinate alpha\r
- * @param[in] Ibeta input two-phase vector coordinate beta\r
- * @param[out] pId points to output rotor reference frame d\r
- * @param[out] pIq points to output rotor reference frame q\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- *\r
- * The function implements the forward Park transform.\r
- *\r
- */\r
- static __INLINE void arm_park_f32(\r
- float32_t Ialpha,\r
- float32_t Ibeta,\r
- float32_t * pId,\r
- float32_t * pIq,\r
- float32_t sinVal,\r
- float32_t cosVal)\r
- {\r
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
- *pId = Ialpha * cosVal + Ibeta * sinVal;\r
-\r
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
- }\r
-\r
-\r
- /**\r
- * @brief Park transform for Q31 version\r
- * @param[in] Ialpha input two-phase vector coordinate alpha\r
- * @param[in] Ibeta input two-phase vector coordinate beta\r
- * @param[out] pId points to output rotor reference frame d\r
- * @param[out] pIq points to output rotor reference frame q\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
- */\r
- static __INLINE void arm_park_q31(\r
- q31_t Ialpha,\r
- q31_t Ibeta,\r
- q31_t * pId,\r
- q31_t * pIq,\r
- q31_t sinVal,\r
- q31_t cosVal)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
- q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
-\r
- /* Intermediate product is calculated by (Ialpha * cosVal) */\r
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Ibeta * sinVal) */\r
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
-\r
-\r
- /* Intermediate product is calculated by (Ialpha * sinVal) */\r
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Ibeta * cosVal) */\r
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
-\r
- /* Calculate pId by adding the two intermediate products 1 and 2 */\r
- *pId = __QADD(product1, product2);\r
-\r
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
- *pIq = __QSUB(product4, product3);\r
- }\r
-\r
- /**\r
- * @} end of park group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q7_to_float(\r
- q7_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup inv_park Vector Inverse Park transform\r
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html parkInvFormula.gif\r
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
- * cosine and sine values of theta (rotor flux position).\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Park transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup inv_park\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Inverse Park transform\r
- * @param[in] Id input coordinate of rotor reference frame d\r
- * @param[in] Iq input coordinate of rotor reference frame q\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- */\r
- static __INLINE void arm_inv_park_f32(\r
- float32_t Id,\r
- float32_t Iq,\r
- float32_t * pIalpha,\r
- float32_t * pIbeta,\r
- float32_t sinVal,\r
- float32_t cosVal)\r
- {\r
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
- *pIalpha = Id * cosVal - Iq * sinVal;\r
-\r
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
- *pIbeta = Id * sinVal + Iq * cosVal;\r
- }\r
-\r
-\r
- /**\r
- * @brief Inverse Park transform for Q31 version\r
- * @param[in] Id input coordinate of rotor reference frame d\r
- * @param[in] Iq input coordinate of rotor reference frame q\r
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition, hence there is no risk of overflow.\r
- */\r
- static __INLINE void arm_inv_park_q31(\r
- q31_t Id,\r
- q31_t Iq,\r
- q31_t * pIalpha,\r
- q31_t * pIbeta,\r
- q31_t sinVal,\r
- q31_t cosVal)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
- q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
-\r
- /* Intermediate product is calculated by (Id * cosVal) */\r
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Iq * sinVal) */\r
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
-\r
-\r
- /* Intermediate product is calculated by (Id * sinVal) */\r
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Iq * cosVal) */\r
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
-\r
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
- *pIalpha = __QSUB(product1, product2);\r
-\r
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
- *pIbeta = __QADD(product4, product3);\r
- }\r
-\r
- /**\r
- * @} end of Inverse park group\r
- */\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q31_to_float(\r
- q31_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @ingroup groupInterpolation\r
- */\r
-\r
- /**\r
- * @defgroup LinearInterpolate Linear Interpolation\r
- *\r
- * Linear interpolation is a method of curve fitting using linear polynomials.\r
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
- *\r
- * \par\r
- * \image html LinearInterp.gif "Linear interpolation"\r
- *\r
- * \par\r
- * A Linear Interpolate function calculates an output value(y), for the input(x)\r
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
- *\r
- * \par Algorithm:\r
- * <pre>\r
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
- * where x0, x1 are nearest values of input x\r
- * y0, y1 are nearest values to output y\r
- * </pre>\r
- *\r
- * \par\r
- * This set of functions implements Linear interpolation process\r
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
- * sample of data and each call to the function returns a single processed value.\r
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
- * <code>x</code> is the input sample value. The functions returns the output value.\r
- *\r
- * \par\r
- * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
- * if x is below input range and returns last value of table if x is above range.\r
- */\r
-\r
- /**\r
- * @addtogroup LinearInterpolate\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Process function for the floating-point Linear Interpolation Function.\r
- * @param[in,out] S is an instance of the floating-point Linear Interpolation structure\r
- * @param[in] x input sample to process\r
- * @return y processed output sample.\r
- *\r
- */\r
- static __INLINE float32_t arm_linear_interp_f32(\r
- arm_linear_interp_instance_f32 * S,\r
- float32_t x)\r
- {\r
- float32_t y;\r
- float32_t x0, x1; /* Nearest input values */\r
- float32_t y0, y1; /* Nearest output values */\r
- float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
- int32_t i; /* Index variable */\r
- float32_t *pYData = S->pYData; /* pointer to output table */\r
-\r
- /* Calculation of index */\r
- i = (int32_t) ((x - S->x1) / xSpacing);\r
-\r
- if(i < 0)\r
- {\r
- /* Iniatilize output for below specified range as least output value of table */\r
- y = pYData[0];\r
- }\r
- else if((uint32_t)i >= S->nValues)\r
- {\r
- /* Iniatilize output for above specified range as last output value of table */\r
- y = pYData[S->nValues - 1];\r
- }\r
- else\r
- {\r
- /* Calculation of nearest input values */\r
- x0 = S->x1 + i * xSpacing;\r
- x1 = S->x1 + (i + 1) * xSpacing;\r
-\r
- /* Read of nearest output values */\r
- y0 = pYData[i];\r
- y1 = pYData[i + 1];\r
-\r
- /* Calculation of output */\r
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r
-\r
- }\r
-\r
- /* returns output value */\r
- return (y);\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q31 Linear Interpolation Function.\r
- * @param[in] pYData pointer to Q31 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- *\r
- */\r
- static __INLINE q31_t arm_linear_interp_q31(\r
- q31_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q31_t y; /* output */\r
- q31_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- int32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- index = ((x & (q31_t)0xFFF00000) >> 20);\r
-\r
- if(index >= (int32_t)(nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else if(index < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* shift left by 11 to keep fract in 1.31 format */\r
- fract = (x & 0x000FFFFF) << 11;\r
-\r
- /* Read two nearest output values from the index in 1.31(q31) format */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1];\r
-\r
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
-\r
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
-\r
- /* Convert y to 1.31 format */\r
- return (y << 1u);\r
- }\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q15 Linear Interpolation Function.\r
- * @param[in] pYData pointer to Q15 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- *\r
- */\r
- static __INLINE q15_t arm_linear_interp_q15(\r
- q15_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q63_t y; /* output */\r
- q15_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- int32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- index = ((x & (int32_t)0xFFF00000) >> 20);\r
-\r
- if(index >= (int32_t)(nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else if(index < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* fract is in 12.20 format */\r
- fract = (x & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1];\r
-\r
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
- y = ((q63_t) y0 * (0xFFFFF - fract));\r
-\r
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
- y += ((q63_t) y1 * (fract));\r
-\r
- /* convert y to 1.15 format */\r
- return (q15_t) (y >> 20);\r
- }\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q7 Linear Interpolation Function.\r
- * @param[in] pYData pointer to Q7 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- */\r
- static __INLINE q7_t arm_linear_interp_q7(\r
- q7_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q31_t y; /* output */\r
- q7_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- uint32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- if (x < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- index = (x >> 20) & 0xfff;\r
-\r
- if(index >= (nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* fract is in 12.20 format */\r
- fract = (x & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index and are in 1.7(q7) format */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1];\r
-\r
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
- y = ((y0 * (0xFFFFF - fract)));\r
-\r
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
- y += (y1 * fract);\r
-\r
- /* convert y to 1.7(q7) format */\r
- return (q7_t) (y >> 20);\r
- }\r
- }\r
-\r
- /**\r
- * @} end of LinearInterpolate group\r
- */\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
- * @param[in] x input value in radians.\r
- * @return sin(x).\r
- */\r
- float32_t arm_sin_f32(\r
- float32_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return sin(x).\r
- */\r
- q31_t arm_sin_q31(\r
- q31_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return sin(x).\r
- */\r
- q15_t arm_sin_q15(\r
- q15_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
- * @param[in] x input value in radians.\r
- * @return cos(x).\r
- */\r
- float32_t arm_cos_f32(\r
- float32_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return cos(x).\r
- */\r
- q31_t arm_cos_q31(\r
- q31_t x);\r
-\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return cos(x).\r
- */\r
- q15_t arm_cos_q15(\r
- q15_t x);\r
-\r
-\r
- /**\r
- * @ingroup groupFastMath\r
- */\r
-\r
-\r
- /**\r
- * @defgroup SQRT Square Root\r
- *\r
- * Computes the square root of a number.\r
- * There are separate functions for Q15, Q31, and floating-point data types.\r
- * The square root function is computed using the Newton-Raphson algorithm.\r
- * This is an iterative algorithm of the form:\r
- * <pre>\r
- * x1 = x0 - f(x0)/f'(x0)\r
- * </pre>\r
- * where <code>x1</code> is the current estimate,\r
- * <code>x0</code> is the previous estimate, and\r
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
- * For the square root function, the algorithm reduces to:\r
- * <pre>\r
- * x0 = in/2 [initial guess]\r
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
- * </pre>\r
- */\r
-\r
-\r
- /**\r
- * @addtogroup SQRT\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point square root function.\r
- * @param[in] in input value.\r
- * @param[out] pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- static __INLINE arm_status arm_sqrt_f32(\r
- float32_t in,\r
- float32_t * pOut)\r
- {\r
- if(in >= 0.0f)\r
- {\r
-\r
-#if (__FPU_USED == 1) && defined ( __CC_ARM )\r
- *pOut = __sqrtf(in);\r
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\r
- *pOut = __builtin_sqrtf(in);\r
-#elif (__FPU_USED == 1) && defined(__GNUC__)\r
- *pOut = __builtin_sqrtf(in);\r
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)\r
- __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));\r
-#else\r
- *pOut = sqrtf(in);\r
-#endif\r
-\r
- return (ARM_MATH_SUCCESS);\r
- }\r
- else\r
- {\r
- *pOut = 0.0f;\r
- return (ARM_MATH_ARGUMENT_ERROR);\r
- }\r
- }\r
-\r
-\r
- /**\r
- * @brief Q31 square root function.\r
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
- * @param[out] pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- arm_status arm_sqrt_q31(\r
- q31_t in,\r
- q31_t * pOut);\r
-\r
-\r
- /**\r
- * @brief Q15 square root function.\r
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
- * @param[out] pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- arm_status arm_sqrt_q15(\r
- q15_t in,\r
- q15_t * pOut);\r
-\r
- /**\r
- * @} end of SQRT group\r
- */\r
-\r
-\r
- /**\r
- * @brief floating-point Circular write function.\r
- */\r
- static __INLINE void arm_circularWrite_f32(\r
- int32_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const int32_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if(wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = (uint16_t)wOffset;\r
- }\r
-\r
-\r
-\r
- /**\r
- * @brief floating-point Circular Read function.\r
- */\r
- static __INLINE void arm_circularRead_f32(\r
- int32_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- int32_t * dst,\r
- int32_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if(dst == (int32_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update rOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if(rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q15 Circular write function.\r
- */\r
- static __INLINE void arm_circularWrite_q15(\r
- q15_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const q15_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if(wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = (uint16_t)wOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q15 Circular Read function.\r
- */\r
- static __INLINE void arm_circularRead_q15(\r
- q15_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- q15_t * dst,\r
- q15_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
-\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if(dst == (q15_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if(rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 Circular write function.\r
- */\r
- static __INLINE void arm_circularWrite_q7(\r
- q7_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const q7_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if(wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = (uint16_t)wOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 Circular Read function.\r
- */\r
- static __INLINE void arm_circularRead_q7(\r
- q7_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- q7_t * dst,\r
- q7_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
-\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if(dst == (q7_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update rOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if(rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q63_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q63_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_power_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Mean value of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_mean_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Variance of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_var_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Variance of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_var_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Variance of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_var_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_rms_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_rms_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_rms_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_std_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_std_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output value.\r
- */\r
- void arm_std_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex magnitude\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex magnitude\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex magnitude\r
- * @param[in] pSrc points to the complex input vector\r
- * @param[out] pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- */\r
- void arm_cmplx_mag_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q15 complex dot product\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] realResult real part of the result returned here\r
- * @param[out] imagResult imaginary part of the result returned here\r
- */\r
- void arm_cmplx_dot_prod_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- uint32_t numSamples,\r
- q31_t * realResult,\r
- q31_t * imagResult);\r
-\r
-\r
- /**\r
- * @brief Q31 complex dot product\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] realResult real part of the result returned here\r
- * @param[out] imagResult imaginary part of the result returned here\r
- */\r
- void arm_cmplx_dot_prod_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- uint32_t numSamples,\r
- q63_t * realResult,\r
- q63_t * imagResult);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex dot product\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] realResult real part of the result returned here\r
- * @param[out] imagResult imaginary part of the result returned here\r
- */\r
- void arm_cmplx_dot_prod_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- uint32_t numSamples,\r
- float32_t * realResult,\r
- float32_t * imagResult);\r
-\r
-\r
- /**\r
- * @brief Q15 complex-by-real multiplication\r
- * @param[in] pSrcCmplx points to the complex input vector\r
- * @param[in] pSrcReal points to the real input vector\r
- * @param[out] pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- */\r
- void arm_cmplx_mult_real_q15(\r
- q15_t * pSrcCmplx,\r
- q15_t * pSrcReal,\r
- q15_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex-by-real multiplication\r
- * @param[in] pSrcCmplx points to the complex input vector\r
- * @param[in] pSrcReal points to the real input vector\r
- * @param[out] pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- */\r
- void arm_cmplx_mult_real_q31(\r
- q31_t * pSrcCmplx,\r
- q31_t * pSrcReal,\r
- q31_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex-by-real multiplication\r
- * @param[in] pSrcCmplx points to the complex input vector\r
- * @param[in] pSrcReal points to the real input vector\r
- * @param[out] pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- */\r
- void arm_cmplx_mult_real_f32(\r
- float32_t * pSrcCmplx,\r
- float32_t * pSrcReal,\r
- float32_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] result is output pointer\r
- * @param[in] index is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * result,\r
- uint32_t * index);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output pointer\r
- * @param[in] pIndex is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output pointer\r
- * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
- /**\r
- * @brief Minimum value of a floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] pResult is output pointer\r
- * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
- */\r
- void arm_min_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a Q7 vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a Q15 vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a Q31 vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
-/**\r
- * @brief Maximum value of a floating-point vector.\r
- * @param[in] pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] pResult maximum value returned here\r
- * @param[out] pIndex index of maximum value returned here\r
- */\r
- void arm_max_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-\r
- /**\r
- * @brief Q15 complex-by-complex multiplication\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_mult_cmplx_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Q31 complex-by-complex multiplication\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_mult_cmplx_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex-by-complex multiplication\r
- * @param[in] pSrcA points to the first input vector\r
- * @param[in] pSrcB points to the second input vector\r
- * @param[out] pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- */\r
- void arm_cmplx_mult_cmplx_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q31 vector.\r
- * @param[in] pSrc points to the floating-point input vector\r
- * @param[out] pDst points to the Q31 output vector\r
- * @param[in] blockSize length of the input vector\r
- */\r
- void arm_float_to_q31(\r
- float32_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q15 vector.\r
- * @param[in] pSrc points to the floating-point input vector\r
- * @param[out] pDst points to the Q15 output vector\r
- * @param[in] blockSize length of the input vector\r
- */\r
- void arm_float_to_q15(\r
- float32_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q7 vector.\r
- * @param[in] pSrc points to the floating-point input vector\r
- * @param[out] pDst points to the Q7 output vector\r
- * @param[in] blockSize length of the input vector\r
- */\r
- void arm_float_to_q7(\r
- float32_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to Q15 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q31_to_q15(\r
- q31_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q31_to_q7(\r
- q31_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to floating-point vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q15_to_float(\r
- q15_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to Q31 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q15_to_q31(\r
- q15_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to Q7 vector.\r
- * @param[in] pSrc is input pointer\r
- * @param[out] pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- */\r
- void arm_q15_to_q7(\r
- q15_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @ingroup groupInterpolation\r
- */\r
-\r
- /**\r
- * @defgroup BilinearInterpolate Bilinear Interpolation\r
- *\r
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
- * determines values between the grid points.\r
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
- * Bilinear interpolation is often used in image processing to rescale images.\r
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
- *\r
- * <b>Algorithm</b>\r
- * \par\r
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
- * For floating-point, the instance structure is defined as:\r
- * <pre>\r
- * typedef struct\r
- * {\r
- * uint16_t numRows;\r
- * uint16_t numCols;\r
- * float32_t *pData;\r
- * } arm_bilinear_interp_instance_f32;\r
- * </pre>\r
- *\r
- * \par\r
- * where <code>numRows</code> specifies the number of rows in the table;\r
- * <code>numCols</code> specifies the number of columns in the table;\r
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
- *\r
- * \par\r
- * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
- * <pre>\r
- * XF = floor(x)\r
- * YF = floor(y)\r
- * </pre>\r
- * \par\r
- * The interpolated output point is computed as:\r
- * <pre>\r
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
- * </pre>\r
- * Note that the coordinates (x, y) contain integer and fractional components.\r
- * The integer components specify which portion of the table to use while the\r
- * fractional components control the interpolation processor.\r
- *\r
- * \par\r
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
- */\r
-\r
- /**\r
- * @addtogroup BilinearInterpolate\r
- * @{\r
- */\r
-\r
-\r
- /**\r
- *\r
- * @brief Floating-point bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate.\r
- * @param[in] Y interpolation coordinate.\r
- * @return out interpolated value.\r
- */\r
- static __INLINE float32_t arm_bilinear_interp_f32(\r
- const arm_bilinear_interp_instance_f32 * S,\r
- float32_t X,\r
- float32_t Y)\r
- {\r
- float32_t out;\r
- float32_t f00, f01, f10, f11;\r
- float32_t *pData = S->pData;\r
- int32_t xIndex, yIndex, index;\r
- float32_t xdiff, ydiff;\r
- float32_t b1, b2, b3, b4;\r
-\r
- xIndex = (int32_t) X;\r
- yIndex = (int32_t) Y;\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* Calculation of index for two nearest points in X-direction */\r
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r
-\r
-\r
- /* Read two nearest points in X-direction */\r
- f00 = pData[index];\r
- f01 = pData[index + 1];\r
-\r
- /* Calculation of index for two nearest points in Y-direction */\r
- index = (xIndex - 1) + (yIndex) * S->numCols;\r
-\r
-\r
- /* Read two nearest points in Y-direction */\r
- f10 = pData[index];\r
- f11 = pData[index + 1];\r
-\r
- /* Calculation of intermediate values */\r
- b1 = f00;\r
- b2 = f01 - f00;\r
- b3 = f10 - f00;\r
- b4 = f00 - f01 - f10 + f11;\r
-\r
- /* Calculation of fractional part in X */\r
- xdiff = X - xIndex;\r
-\r
- /* Calculation of fractional part in Y */\r
- ydiff = Y - yIndex;\r
-\r
- /* Calculation of bi-linear interpolated output */\r
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
-\r
- /* return to application */\r
- return (out);\r
- }\r
-\r
-\r
- /**\r
- *\r
- * @brief Q31 bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
- static __INLINE q31_t arm_bilinear_interp_q31(\r
- arm_bilinear_interp_instance_q31 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q31_t out; /* Temporary output */\r
- q31_t acc = 0; /* output */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- q31_t x1, x2, y1, y2; /* Nearest output values */\r
- int32_t rI, cI; /* Row and column indices */\r
- q31_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* shift left xfract by 11 to keep 1.31 format */\r
- xfract = (X & 0x000FFFFF) << 11u;\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[(rI) + (int32_t)nCols * (cI) ];\r
- x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\r
-\r
- /* 20 bits for the fractional part */\r
- /* shift left yfract by 11 to keep 1.31 format */\r
- yfract = (Y & 0x000FFFFF) << 11u;\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];\r
- y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
-\r
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
-\r
- /* Convert acc to 1.31(q31) format */\r
- return ((q31_t)(acc << 2));\r
- }\r
-\r
-\r
- /**\r
- * @brief Q15 bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
- static __INLINE q15_t arm_bilinear_interp_q15(\r
- arm_bilinear_interp_instance_q15 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q63_t acc = 0; /* output */\r
- q31_t out; /* Temporary output */\r
- q15_t x1, x2, y1, y2; /* Nearest output values */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- int32_t rI, cI; /* Row and column indices */\r
- q15_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* xfract should be in 12.20 format */\r
- xfract = (X & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
-\r
- /* 20 bits for the fractional part */\r
- /* yfract should be in 12.20 format */\r
- yfract = (Y & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
-\r
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
- acc = ((q63_t) out * (0xFFFFF - yfract));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
- acc += ((q63_t) out * (xfract));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
- acc += ((q63_t) out * (yfract));\r
-\r
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
- acc += ((q63_t) out * (yfract));\r
-\r
- /* acc is in 13.51 format and down shift acc by 36 times */\r
- /* Convert out to 1.15 format */\r
- return ((q15_t)(acc >> 36));\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 bilinear interpolation.\r
- * @param[in,out] S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
- static __INLINE q7_t arm_bilinear_interp_q7(\r
- arm_bilinear_interp_instance_q7 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q63_t acc = 0; /* output */\r
- q31_t out; /* Temporary output */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- q7_t x1, x2, y1, y2; /* Nearest output values */\r
- int32_t rI, cI; /* Row and column indices */\r
- q7_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* xfract should be in 12.20 format */\r
- xfract = (X & (q31_t)0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
-\r
- /* 20 bits for the fractional part */\r
- /* yfract should be in 12.20 format */\r
- yfract = (Y & (q31_t)0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
- out = ((x1 * (0xFFFFF - xfract)));\r
- acc = (((q63_t) out * (0xFFFFF - yfract)));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
- out = ((x2 * (0xFFFFF - yfract)));\r
- acc += (((q63_t) out * (xfract)));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
- out = ((y1 * (0xFFFFF - xfract)));\r
- acc += (((q63_t) out * (yfract)));\r
-\r
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
- out = ((y2 * (yfract)));\r
- acc += (((q63_t) out * (xfract)));\r
-\r
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
- return ((q7_t)(acc >> 40));\r
- }\r
-\r
- /**\r
- * @} end of BilinearInterpolate group\r
- */\r
-\r
-\r
-/* SMMLAR */\r
-#define multAcc_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
-\r
-/* SMMLSR */\r
-#define multSub_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
-\r
-/* SMMULR */\r
-#define mult_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r
-\r
-/* SMMLA */\r
-#define multAcc_32x32_keep32(a, x, y) \\r
- a += (q31_t) (((q63_t) x * y) >> 32)\r
-\r
-/* SMMLS */\r
-#define multSub_32x32_keep32(a, x, y) \\r
- a -= (q31_t) (((q63_t) x * y) >> 32)\r
-\r
-/* SMMUL */\r
-#define mult_32x32_keep32(a, x, y) \\r
- a = (q31_t) (((q63_t) x * y ) >> 32)\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- /* Enter low optimization region - place directly above function definition */\r
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r
- #define LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("push") \\r
- _Pragma ("O1")\r
- #else\r
- #define LOW_OPTIMIZATION_ENTER\r
- #endif\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r
- #define LOW_OPTIMIZATION_EXIT \\r
- _Pragma ("pop")\r
- #else\r
- #define LOW_OPTIMIZATION_EXIT\r
- #endif\r
-\r
- /* Enter low optimization region - place directly above function definition */\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined(__GNUC__)\r
- #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined(__ICCARM__)\r
- /* Enter low optimization region - place directly above function definition */\r
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r
- #define LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("optimize=low")\r
- #else\r
- #define LOW_OPTIMIZATION_ENTER\r
- #endif\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #define LOW_OPTIMIZATION_EXIT\r
-\r
- /* Enter low optimization region - place directly above function definition */\r
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("optimize=low")\r
- #else\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #endif\r
-\r
- /* Exit low optimization region - place directly after end of function definition */\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined(__CSMC__)\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined(__TASKING__)\r
- #define LOW_OPTIMIZATION_ENTER\r
- #define LOW_OPTIMIZATION_EXIT\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#endif\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#if defined ( __GNUC__ )\r
-#pragma GCC diagnostic pop\r
-#endif\r
-\r
-#endif /* _ARM_MATH_H */\r
-\r
-/**\r
- *\r
- * End of file.\r
- */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file cmsis_armcc.h\r
- * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#ifndef __CMSIS_ARMCC_H\r
-#define __CMSIS_ARMCC_H\r
-\r
-\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
- */\r
-\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-/**\r
- \brief Get Control Register\r
- \details Returns the content of the Control Register.\r
- \return Control Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Control Register\r
- \details Writes the given value to the Control Register.\r
- \param [in] control Control Register value to set\r
- */\r
-__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-\r
-/**\r
- \brief Get IPSR Register\r
- \details Returns the content of the IPSR Register.\r
- \return IPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- register uint32_t __regIPSR __ASM("ipsr");\r
- return(__regIPSR);\r
-}\r
-\r
-\r
-/**\r
- \brief Get APSR Register\r
- \details Returns the content of the APSR Register.\r
- \return APSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- register uint32_t __regAPSR __ASM("apsr");\r
- return(__regAPSR);\r
-}\r
-\r
-\r
-/**\r
- \brief Get xPSR Register\r
- \details Returns the content of the xPSR Register.\r
- \return xPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- register uint32_t __regXPSR __ASM("xpsr");\r
- return(__regXPSR);\r
-}\r
-\r
-\r
-/**\r
- \brief Get Process Stack Pointer\r
- \details Returns the current value of the Process Stack Pointer (PSP).\r
- \return PSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- return(__regProcessStackPointer);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Process Stack Pointer\r
- \details Assigns the given value to the Process Stack Pointer (PSP).\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- __regProcessStackPointer = topOfProcStack;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Main Stack Pointer\r
- \details Returns the current value of the Main Stack Pointer (MSP).\r
- \return MSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- return(__regMainStackPointer);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Main Stack Pointer\r
- \details Assigns the given value to the Main Stack Pointer (MSP).\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- __regMainStackPointer = topOfMainStack;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Mask\r
- \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
- \return Priority Mask value\r
- */\r
-__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Priority Mask\r
- \details Assigns the given value to the Priority Mask Register.\r
- \param [in] priMask Priority Mask\r
- */\r
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
-\r
-/**\r
- \brief Enable FIQ\r
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __enable_fault_irq __enable_fiq\r
-\r
-\r
-/**\r
- \brief Disable FIQ\r
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-\r
-/**\r
- \brief Get Base Priority\r
- \details Returns the current value of the Base Priority register.\r
- \return Base Priority register value\r
- */\r
-__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority\r
- \details Assigns the given value to the Base Priority register.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xFFU);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority with condition\r
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
- or the new value increases the BASEPRI priority level.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePriMax __ASM("basepri_max");\r
- __regBasePriMax = (basePri & 0xFFU);\r
-}\r
-\r
-\r
-/**\r
- \brief Get Fault Mask\r
- \details Returns the current value of the Fault Mask register.\r
- \return Fault Mask register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Fault Mask\r
- \details Assigns the given value to the Fault Mask register.\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & (uint32_t)1);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
-\r
-/**\r
- \brief Get FPSCR\r
- \details Returns the current value of the Floating Point Status/Control register.\r
- \return Floating Point Status/Control register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- return(__regfpscr);\r
-#else\r
- return(0U);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Set FPSCR\r
- \details Assigns the given value to the Floating Point Status/Control register.\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- __regfpscr = (fpscr);\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
-\r
-\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-/**\r
- \brief No Operation\r
- \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP __nop\r
-\r
-\r
-/**\r
- \brief Wait For Interrupt\r
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
- */\r
-#define __WFI __wfi\r
-\r
-\r
-/**\r
- \brief Wait For Event\r
- \details Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE __wfe\r
-\r
-\r
-/**\r
- \brief Send Event\r
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV __sev\r
-\r
-\r
-/**\r
- \brief Instruction Synchronization Barrier\r
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or memory,\r
- after the instruction has been completed.\r
- */\r
-#define __ISB() do {\\r
- __schedule_barrier();\\r
- __isb(0xF);\\r
- __schedule_barrier();\\r
- } while (0U)\r
-\r
-/**\r
- \brief Data Synchronization Barrier\r
- \details Acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() do {\\r
- __schedule_barrier();\\r
- __dsb(0xF);\\r
- __schedule_barrier();\\r
- } while (0U)\r
-\r
-/**\r
- \brief Data Memory Barrier\r
- \details Ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() do {\\r
- __schedule_barrier();\\r
- __dmb(0xF);\\r
- __schedule_barrier();\\r
- } while (0U)\r
-\r
-/**\r
- \brief Reverse byte order (32 bit)\r
- \details Reverses the byte order in integer value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV __rev\r
-\r
-\r
-/**\r
- \brief Reverse byte order (16 bit)\r
- \details Reverses the byte order in two unsigned short values.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-/**\r
- \brief Reverse byte order in signed short value\r
- \details Reverses the byte order in a signed short value with sign extension to integer.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Rotate Right in unsigned value (32 bit)\r
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-#define __ROR __ror\r
-\r
-\r
-/**\r
- \brief Breakpoint\r
- \details Causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __breakpoint(value)\r
-\r
-\r
-/**\r
- \brief Reverse bit order of value\r
- \details Reverses the bit order of the given value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
- #define __RBIT __rbit\r
-#else\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
-\r
- result = value; /* r will be reversed bits of v; first get LSB of v */\r
- for (value >>= 1U; value; value >>= 1U)\r
- {\r
- result <<= 1U;\r
- result |= value & 1U;\r
- s--;\r
- }\r
- result <<= s; /* shift when v's highest bits are zero */\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Count leading zeros\r
- \details Counts the number of leading zeros of a data value.\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __clz\r
-\r
-\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
-\r
-/**\r
- \brief LDR Exclusive (8 bit)\r
- \details Executes a exclusive LDR instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
-#else\r
- #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (16 bit)\r
- \details Executes a exclusive LDR instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
-#else\r
- #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (32 bit)\r
- \details Executes a exclusive LDR instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
-#else\r
- #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief STR Exclusive (8 bit)\r
- \details Executes a exclusive STR instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __STREXB(value, ptr) __strex(value, ptr)\r
-#else\r
- #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief STR Exclusive (16 bit)\r
- \details Executes a exclusive STR instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __STREXH(value, ptr) __strex(value, ptr)\r
-#else\r
- #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief STR Exclusive (32 bit)\r
- \details Executes a exclusive STR instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __STREXW(value, ptr) __strex(value, ptr)\r
-#else\r
- #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief Remove the exclusive lock\r
- \details Removes the exclusive lock which is created by LDREX.\r
- */\r
-#define __CLREX __clrex\r
-\r
-\r
-/**\r
- \brief Signed Saturate\r
- \details Saturates a signed value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT __ssat\r
-\r
-\r
-/**\r
- \brief Unsigned Saturate\r
- \details Saturates an unsigned value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT __usat\r
-\r
-\r
-/**\r
- \brief Rotate Right with Extend (32 bit)\r
- \details Moves each bit of a bitstring right by one bit.\r
- The carry input is shifted in at the left end of the bitstring.\r
- \param [in] value Value to rotate\r
- \return Rotated value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
-{\r
- rrx r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged STRT instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-#define __STRBT(value, ptr) __strt(value, ptr)\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged STRT instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-#define __STRHT(value, ptr) __strt(value, ptr)\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged STRT instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-#define __STRT(value, ptr) __strt(value, ptr)\r
-\r
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
- Access to dedicated SIMD instructions\r
- @{\r
-*/\r
-\r
-#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */\r
-\r
-#define __SADD8 __sadd8\r
-#define __QADD8 __qadd8\r
-#define __SHADD8 __shadd8\r
-#define __UADD8 __uadd8\r
-#define __UQADD8 __uqadd8\r
-#define __UHADD8 __uhadd8\r
-#define __SSUB8 __ssub8\r
-#define __QSUB8 __qsub8\r
-#define __SHSUB8 __shsub8\r
-#define __USUB8 __usub8\r
-#define __UQSUB8 __uqsub8\r
-#define __UHSUB8 __uhsub8\r
-#define __SADD16 __sadd16\r
-#define __QADD16 __qadd16\r
-#define __SHADD16 __shadd16\r
-#define __UADD16 __uadd16\r
-#define __UQADD16 __uqadd16\r
-#define __UHADD16 __uhadd16\r
-#define __SSUB16 __ssub16\r
-#define __QSUB16 __qsub16\r
-#define __SHSUB16 __shsub16\r
-#define __USUB16 __usub16\r
-#define __UQSUB16 __uqsub16\r
-#define __UHSUB16 __uhsub16\r
-#define __SASX __sasx\r
-#define __QASX __qasx\r
-#define __SHASX __shasx\r
-#define __UASX __uasx\r
-#define __UQASX __uqasx\r
-#define __UHASX __uhasx\r
-#define __SSAX __ssax\r
-#define __QSAX __qsax\r
-#define __SHSAX __shsax\r
-#define __USAX __usax\r
-#define __UQSAX __uqsax\r
-#define __UHSAX __uhsax\r
-#define __USAD8 __usad8\r
-#define __USADA8 __usada8\r
-#define __SSAT16 __ssat16\r
-#define __USAT16 __usat16\r
-#define __UXTB16 __uxtb16\r
-#define __UXTAB16 __uxtab16\r
-#define __SXTB16 __sxtb16\r
-#define __SXTAB16 __sxtab16\r
-#define __SMUAD __smuad\r
-#define __SMUADX __smuadx\r
-#define __SMLAD __smlad\r
-#define __SMLADX __smladx\r
-#define __SMLALD __smlald\r
-#define __SMLALDX __smlaldx\r
-#define __SMUSD __smusd\r
-#define __SMUSDX __smusdx\r
-#define __SMLSD __smlsd\r
-#define __SMLSDX __smlsdx\r
-#define __SMLSLD __smlsld\r
-#define __SMLSLDX __smlsldx\r
-#define __SEL __sel\r
-#define __QADD __qadd\r
-#define __QSUB __qsub\r
-\r
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
-\r
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
- ((int64_t)(ARG3) << 32U) ) >> 32U))\r
-\r
-#endif /* (__CORTEX_M >= 0x04) */\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#endif /* __CMSIS_ARMCC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file cmsis_armcc_V6.h\r
- * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#ifndef __CMSIS_ARMCC_V6_H\r
-#define __CMSIS_ARMCC_V6_H\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
- */\r
-\r
-/**\r
- \brief Enable IRQ Interrupts\r
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)\r
-{\r
- __ASM volatile ("cpsie i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Disable IRQ Interrupts\r
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)\r
-{\r
- __ASM volatile ("cpsid i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Control Register\r
- \details Returns the content of the Control Register.\r
- \return Control Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get Control Register (non-secure)\r
- \details Returns the content of the non-secure Control Register when in secure mode.\r
- \return non-secure Control Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Control Register\r
- \details Writes the given value to the Control Register.\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Set Control Register (non-secure)\r
- \details Writes the given value to the non-secure Control Register when in secure state.\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Get IPSR Register\r
- \details Returns the content of the IPSR Register.\r
- \return IPSR Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get IPSR Register (non-secure)\r
- \details Returns the content of the non-secure IPSR Register when in secure state.\r
- \return IPSR Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Get APSR Register\r
- \details Returns the content of the APSR Register.\r
- \return APSR Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get APSR Register (non-secure)\r
- \details Returns the content of the non-secure APSR Register when in secure state.\r
- \return APSR Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Get xPSR Register\r
- \details Returns the content of the xPSR Register.\r
- \return xPSR Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get xPSR Register (non-secure)\r
- \details Returns the content of the non-secure xPSR Register when in secure state.\r
- \return xPSR Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Get Process Stack Pointer\r
- \details Returns the current value of the Process Stack Pointer (PSP).\r
- \return PSP Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get Process Stack Pointer (non-secure)\r
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
- \return PSP Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Process Stack Pointer\r
- \details Assigns the given value to the Process Stack Pointer (PSP).\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Set Process Stack Pointer (non-secure)\r
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Get Main Stack Pointer\r
- \details Returns the current value of the Main Stack Pointer (MSP).\r
- \return MSP Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get Main Stack Pointer (non-secure)\r
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
- \return MSP Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Main Stack Pointer\r
- \details Assigns the given value to the Main Stack Pointer (MSP).\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Set Main Stack Pointer (non-secure)\r
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Get Priority Mask\r
- \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
- \return Priority Mask value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get Priority Mask (non-secure)\r
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
- \return Priority Mask value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Priority Mask\r
- \details Assigns the given value to the Priority Mask Register.\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Set Priority Mask (non-secure)\r
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */\r
-\r
-/**\r
- \brief Enable FIQ\r
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsie f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Disable FIQ\r
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsid f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Base Priority\r
- \details Returns the current value of the Base Priority register.\r
- \return Base Priority register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get Base Priority (non-secure)\r
- \details Returns the current value of the non-secure Base Priority register when in secure state.\r
- \return Base Priority register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Base Priority\r
- \details Assigns the given value to the Base Priority register.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Set Base Priority (non-secure)\r
- \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Base Priority with condition\r
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
- or the new value increases the BASEPRI priority level.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Set Base Priority with condition (non_secure)\r
- \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,\r
- or the new value increases the BASEPRI priority level.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Get Fault Mask\r
- \details Returns the current value of the Fault Mask register.\r
- \return Fault Mask register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get Fault Mask (non-secure)\r
- \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
- \return Fault Mask register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Fault Mask\r
- \details Assigns the given value to the Fault Mask register.\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Set Fault Mask (non-secure)\r
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
-}\r
-#endif\r
-\r
-\r
-#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\r
-\r
-\r
-#if (__ARM_ARCH_8M__ == 1U)\r
-\r
-/**\r
- \brief Get Process Stack Pointer Limit\r
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
- \return PSPLIM Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */\r
-/**\r
- \brief Get Process Stack Pointer Limit (non-secure)\r
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
- \return PSPLIM Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Process Stack Pointer Limit\r
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
-{\r
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */\r
-/**\r
- \brief Set Process Stack Pointer (non-secure)\r
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
-{\r
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Get Main Stack Pointer Limit\r
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
- \return MSPLIM Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
-\r
- return(result);\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */\r
-/**\r
- \brief Get Main Stack Pointer Limit (non-secure)\r
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
- \return MSPLIM Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Main Stack Pointer Limit\r
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
-{\r
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
-}\r
-\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */\r
-/**\r
- \brief Set Main Stack Pointer Limit (non-secure)\r
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
- \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
-{\r
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
-}\r
-#endif\r
-\r
-#endif /* (__ARM_ARCH_8M__ == 1U) */\r
-\r
-\r
-#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */\r
-\r
-/**\r
- \brief Get FPSCR\r
- \details eturns the current value of the Floating Point Status/Control register.\r
- \return Floating Point Status/Control register value\r
- */\r
-#define __get_FPSCR __builtin_arm_get_fpscr\r
-#if 0\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- uint32_t result;\r
-\r
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
- __ASM volatile ("");\r
- return(result);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-#endif\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get FPSCR (non-secure)\r
- \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.\r
- \return Floating Point Status/Control register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- uint32_t result;\r
-\r
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );\r
- __ASM volatile ("");\r
- return(result);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set FPSCR\r
- \details Assigns the given value to the Floating Point Status/Control register.\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-#define __set_FPSCR __builtin_arm_set_fpscr\r
-#if 0\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
- __ASM volatile ("");\r
-#endif\r
-}\r
-#endif\r
-\r
-#if (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Set FPSCR (non-secure)\r
- \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");\r
- __ASM volatile ("");\r
-#endif\r
-}\r
-#endif\r
-\r
-#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\r
-\r
-\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constraint "l"\r
- * Otherwise, use general registers, specified by constraint "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/**\r
- \brief No Operation\r
- \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP __builtin_arm_nop\r
-\r
-/**\r
- \brief Wait For Interrupt\r
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
- */\r
-#define __WFI __builtin_arm_wfi\r
-\r
-\r
-/**\r
- \brief Wait For Event\r
- \details Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE __builtin_arm_wfe\r
-\r
-\r
-/**\r
- \brief Send Event\r
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV __builtin_arm_sev\r
-\r
-\r
-/**\r
- \brief Instruction Synchronization Barrier\r
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or memory,\r
- after the instruction has been completed.\r
- */\r
-#define __ISB() __builtin_arm_isb(0xF);\r
-\r
-/**\r
- \brief Data Synchronization Barrier\r
- \details Acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() __builtin_arm_dsb(0xF);\r
-\r
-\r
-/**\r
- \brief Data Memory Barrier\r
- \details Ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() __builtin_arm_dmb(0xF);\r
-\r
-\r
-/**\r
- \brief Reverse byte order (32 bit)\r
- \details Reverses the byte order in integer value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV __builtin_bswap32\r
-\r
-\r
-/**\r
- \brief Reverse byte order (16 bit)\r
- \details Reverses the byte order in two unsigned short values.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */\r
-#if 0\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Reverse byte order in signed short value\r
- \details Reverses the byte order in a signed short value with sign extension to integer.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
- /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */\r
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Rotate Right in unsigned value (32 bit)\r
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
- \param [in] op1 Value to rotate\r
- \param [in] op2 Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
- return (op1 >> op2) | (op1 << (32U - op2));\r
-}\r
-\r
-\r
-/**\r
- \brief Breakpoint\r
- \details Causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
-\r
-\r
-/**\r
- \brief Reverse bit order of value\r
- \details Reverses the bit order of the given value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
- /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
-#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */\r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
-#else\r
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
-\r
- result = value; /* r will be reversed bits of v; first get LSB of v */\r
- for (value >>= 1U; value; value >>= 1U)\r
- {\r
- result <<= 1U;\r
- result |= value & 1U;\r
- s--;\r
- }\r
- result <<= s; /* shift when v's highest bits are zero */\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Count leading zeros\r
- \details Counts the number of leading zeros of a data value.\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __builtin_clz\r
-\r
-\r
-#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */\r
-\r
-/**\r
- \brief LDR Exclusive (8 bit)\r
- \details Executes a exclusive LDR instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDREXB (uint8_t)__builtin_arm_ldrex\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (16 bit)\r
- \details Executes a exclusive LDR instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDREXH (uint16_t)__builtin_arm_ldrex\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (32 bit)\r
- \details Executes a exclusive LDR instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDREXW (uint32_t)__builtin_arm_ldrex\r
-\r
-\r
-/**\r
- \brief STR Exclusive (8 bit)\r
- \details Executes a exclusive STR instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXB (uint32_t)__builtin_arm_strex\r
-\r
-\r
-/**\r
- \brief STR Exclusive (16 bit)\r
- \details Executes a exclusive STR instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXH (uint32_t)__builtin_arm_strex\r
-\r
-\r
-/**\r
- \brief STR Exclusive (32 bit)\r
- \details Executes a exclusive STR instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXW (uint32_t)__builtin_arm_strex\r
-\r
-\r
-/**\r
- \brief Remove the exclusive lock\r
- \details Removes the exclusive lock which is created by LDREX.\r
- */\r
-#define __CLREX __builtin_arm_clrex\r
-\r
-\r
-/**\r
- \brief Signed Saturate\r
- \details Saturates a signed value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-/*#define __SSAT __builtin_arm_ssat*/\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- int32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/**\r
- \brief Unsigned Saturate\r
- \details Saturates an unsigned value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT __builtin_arm_usat\r
-#if 0\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-#endif\r
-\r
-\r
-/**\r
- \brief Rotate Right with Extend (32 bit)\r
- \details Moves each bit of a bitstring right by one bit.\r
- The carry input is shifted in at the left end of the bitstring.\r
- \param [in] value Value to rotate\r
- \return Rotated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
- return ((uint8_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
- return ((uint16_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged STRT instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
-{\r
- __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged STRT instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
-{\r
- __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged STRT instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
-{\r
- __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
-}\r
-\r
-#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\r
-\r
-\r
-#if (__ARM_ARCH_8M__ == 1U)\r
-\r
-/**\r
- \brief Load-Acquire (8 bit)\r
- \details Executes a LDAB instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
- return ((uint8_t) result);\r
-}\r
-\r
-\r
-/**\r
- \brief Load-Acquire (16 bit)\r
- \details Executes a LDAH instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
- return ((uint16_t) result);\r
-}\r
-\r
-\r
-/**\r
- \brief Load-Acquire (32 bit)\r
- \details Executes a LDA instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Store-Release (8 bit)\r
- \details Executes a STLB instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
-{\r
- __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief Store-Release (16 bit)\r
- \details Executes a STLH instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
-{\r
- __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief Store-Release (32 bit)\r
- \details Executes a STL instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
-{\r
- __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief Load-Acquire Exclusive (8 bit)\r
- \details Executes a LDAB exclusive instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDAEXB (uint8_t)__builtin_arm_ldaex\r
-\r
-\r
-/**\r
- \brief Load-Acquire Exclusive (16 bit)\r
- \details Executes a LDAH exclusive instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDAEXH (uint16_t)__builtin_arm_ldaex\r
-\r
-\r
-/**\r
- \brief Load-Acquire Exclusive (32 bit)\r
- \details Executes a LDA exclusive instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDAEX (uint32_t)__builtin_arm_ldaex\r
-\r
-\r
-/**\r
- \brief Store-Release Exclusive (8 bit)\r
- \details Executes a STLB exclusive instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STLEXB (uint32_t)__builtin_arm_stlex\r
-\r
-\r
-/**\r
- \brief Store-Release Exclusive (16 bit)\r
- \details Executes a STLH exclusive instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STLEXH (uint32_t)__builtin_arm_stlex\r
-\r
-\r
-/**\r
- \brief Store-Release Exclusive (32 bit)\r
- \details Executes a STL exclusive instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STLEX (uint32_t)__builtin_arm_stlex\r
-\r
-#endif /* (__ARM_ARCH_8M__ == 1U) */\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
- Access to dedicated SIMD instructions\r
- @{\r
-*/\r
-\r
-#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-#define __SSAT16(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-#define __USAT16(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-#define __PKHBT(ARG1,ARG2,ARG3) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
- __RES; \\r
- })\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
- if (ARG3 == 0) \\r
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
- else \\r
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
- __RES; \\r
- })\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-#endif /* (__ARM_FEATURE_DSP == 1U) */\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#endif /* __CMSIS_ARMCC_V6_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file cmsis_gcc.h\r
- * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#ifndef __CMSIS_GCC_H\r
-#define __CMSIS_GCC_H\r
-\r
-/* ignore some GCC warnings */\r
-#if defined ( __GNUC__ )\r
-#pragma GCC diagnostic push\r
-#pragma GCC diagnostic ignored "-Wsign-conversion"\r
-#pragma GCC diagnostic ignored "-Wconversion"\r
-#pragma GCC diagnostic ignored "-Wunused-parameter"\r
-#endif\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
- */\r
-\r
-/**\r
- \brief Enable IRQ Interrupts\r
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
-{\r
- __ASM volatile ("cpsie i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Disable IRQ Interrupts\r
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
-{\r
- __ASM volatile ("cpsid i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Control Register\r
- \details Returns the content of the Control Register.\r
- \return Control Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Control Register\r
- \details Writes the given value to the Control Register.\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get IPSR Register\r
- \details Returns the content of the IPSR Register.\r
- \return IPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Get APSR Register\r
- \details Returns the content of the APSR Register.\r
- \return APSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Get xPSR Register\r
- \details Returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Get Process Stack Pointer\r
- \details Returns the current value of the Process Stack Pointer (PSP).\r
- \return PSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Process Stack Pointer\r
- \details Assigns the given value to the Process Stack Pointer (PSP).\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Main Stack Pointer\r
- \details Returns the current value of the Main Stack Pointer (MSP).\r
- \return MSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Main Stack Pointer\r
- \details Assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Mask\r
- \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
- \return Priority Mask value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Priority Mask\r
- \details Assigns the given value to the Priority Mask Register.\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03U)\r
-\r
-/**\r
- \brief Enable FIQ\r
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsie f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Disable FIQ\r
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsid f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Base Priority\r
- \details Returns the current value of the Base Priority register.\r
- \return Base Priority register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority\r
- \details Assigns the given value to the Base Priority register.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority with condition\r
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
- or the new value increases the BASEPRI priority level.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Fault Mask\r
- \details Returns the current value of the Fault Mask register.\r
- \return Fault Mask register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Fault Mask\r
- \details Assigns the given value to the Fault Mask register.\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03U) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
-\r
-/**\r
- \brief Get FPSCR\r
- \details Returns the current value of the Floating Point Status/Control register.\r
- \return Floating Point Status/Control register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- uint32_t result;\r
-\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
- __ASM volatile ("");\r
- return(result);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Set FPSCR\r
- \details Assigns the given value to the Floating Point Status/Control register.\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
- __ASM volatile ("");\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
-\r
-\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constraint "l"\r
- * Otherwise, use general registers, specified by constraint "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/**\r
- \brief No Operation\r
- \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
-{\r
- __ASM volatile ("nop");\r
-}\r
-\r
-\r
-/**\r
- \brief Wait For Interrupt\r
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
-{\r
- __ASM volatile ("wfi");\r
-}\r
-\r
-\r
-/**\r
- \brief Wait For Event\r
- \details Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
-{\r
- __ASM volatile ("wfe");\r
-}\r
-\r
-\r
-/**\r
- \brief Send Event\r
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
-{\r
- __ASM volatile ("sev");\r
-}\r
-\r
-\r
-/**\r
- \brief Instruction Synchronization Barrier\r
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or memory,\r
- after the instruction has been completed.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
-{\r
- __ASM volatile ("isb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Data Synchronization Barrier\r
- \details Acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
-{\r
- __ASM volatile ("dsb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Data Memory Barrier\r
- \details Ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
-{\r
- __ASM volatile ("dmb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Reverse byte order (32 bit)\r
- \details Reverses the byte order in integer value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
- return __builtin_bswap32(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Reverse byte order (16 bit)\r
- \details Reverses the byte order in two unsigned short values.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Reverse byte order in signed short value\r
- \details Reverses the byte order in a signed short value with sign extension to integer.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- return (short)__builtin_bswap16(value);\r
-#else\r
- int32_t result;\r
-\r
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Rotate Right in unsigned value (32 bit)\r
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
- return (op1 >> op2) | (op1 << (32U - op2));\r
-}\r
-\r
-\r
-/**\r
- \brief Breakpoint\r
- \details Causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
-\r
-\r
-/**\r
- \brief Reverse bit order of value\r
- \details Reverses the bit order of the given value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
-#else\r
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
-\r
- result = value; /* r will be reversed bits of v; first get LSB of v */\r
- for (value >>= 1U; value; value >>= 1U)\r
- {\r
- result <<= 1U;\r
- result |= value & 1U;\r
- s--;\r
- }\r
- result <<= s; /* shift when v's highest bits are zero */\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Count leading zeros\r
- \details Counts the number of leading zeros of a data value.\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __builtin_clz\r
-\r
-\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
-\r
-/**\r
- \brief LDR Exclusive (8 bit)\r
- \details Executes a exclusive LDR instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint8_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (16 bit)\r
- \details Executes a exclusive LDR instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint16_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (32 bit)\r
- \details Executes a exclusive LDR instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STR Exclusive (8 bit)\r
- \details Executes a exclusive STR instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STR Exclusive (16 bit)\r
- \details Executes a exclusive STR instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STR Exclusive (32 bit)\r
- \details Executes a exclusive STR instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Remove the exclusive lock\r
- \details Removes the exclusive lock which is created by LDREX.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
-{\r
- __ASM volatile ("clrex" ::: "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Signed Saturate\r
- \details Saturates a signed value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/**\r
- \brief Unsigned Saturate\r
- \details Saturates an unsigned value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/**\r
- \brief Rotate Right with Extend (32 bit)\r
- \details Moves each bit of a bitstring right by one bit.\r
- The carry input is shifted in at the left end of the bitstring.\r
- \param [in] value Value to rotate\r
- \return Rotated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint8_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint16_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged STRT instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r
-{\r
- __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged STRT instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r
-{\r
- __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged STRT instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r
-{\r
- __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
- Access to dedicated SIMD instructions\r
- @{\r
-*/\r
-\r
-#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-#define __SSAT16(ARG1,ARG2) \\r
-({ \\r
- int32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-#define __USAT16(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-#define __PKHBT(ARG1,ARG2,ARG3) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
- __RES; \\r
- })\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
- if (ARG3 == 0) \\r
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
- else \\r
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
- __RES; \\r
- })\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x04) */\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#if defined ( __GNUC__ )\r
-#pragma GCC diagnostic pop\r
-#endif\r
-\r
-#endif /* __CMSIS_GCC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm0.h\r
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM0_H_GENERIC\r
-#define __CORE_CM0_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M0\r
- @{\r
- */\r
-\r
-/* CMSIS CM0 definitions */\r
-#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x00U) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
- #define __STATIC_INLINE static inline\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "core_cmInstr.h" /* Core Instruction Access */\r
-#include "core_cmFunc.h" /* Core Function Access */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM0_H_DEPENDANT\r
-#define __CORE_CM0_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM0_REV\r
- #define __CM0_REV 0x0000U\r
- #warning "__CM0_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 2U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M0 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[31U];\r
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[31U];\r
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[31U];\r
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[31U];\r
- uint32_t RESERVED4[64U];\r
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
-} NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- uint32_t RESERVED0;\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- uint32_t RESERVED1;\r
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
- Therefore they are not covered by the Cortex-M0 header file.\r
- @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M0 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
-\r
-\r
-/**\r
- \brief Enable External Interrupt\r
- \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Disable External Interrupt\r
- \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of an external interrupt.\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of an external interrupt.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of an interrupt.\r
- \note The priority cannot be set for every core interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
- else\r
- {\r
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of an interrupt.\r
- The interrupt number can be positive to specify an external (device specific) interrupt,\r
- or negative to specify an internal (core) interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- SCB_AIRCR_SYSRESETREQ_Msk);\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm0plus.h\r
- * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM0PLUS_H_GENERIC\r
-#define __CORE_CM0PLUS_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex-M0+\r
- @{\r
- */\r
-\r
-/* CMSIS CM0+ definitions */\r
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x00U) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
- #define __STATIC_INLINE static inline\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "core_cmInstr.h" /* Core Instruction Access */\r
-#include "core_cmFunc.h" /* Core Function Access */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0PLUS_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
-#define __CORE_CM0PLUS_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM0PLUS_REV\r
- #define __CM0PLUS_REV 0x0000U\r
- #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __VTOR_PRESENT\r
- #define __VTOR_PRESENT 0U\r
- #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 2U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex-M0+ */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[31U];\r
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[31U];\r
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[31U];\r
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[31U];\r
- uint32_t RESERVED4[64U];\r
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
-} NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
-#if (__VTOR_PRESENT == 1U)\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
-#else\r
- uint32_t RESERVED0;\r
-#endif\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- uint32_t RESERVED1;\r
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-#if (__VTOR_PRESENT == 1U)\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-#endif\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
- Therefore they are not covered by the Cortex-M0+ header file.\r
- @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M0+ Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
-\r
-\r
-/**\r
- \brief Enable External Interrupt\r
- \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Disable External Interrupt\r
- \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of an external interrupt.\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of an external interrupt.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of an interrupt.\r
- \note The priority cannot be set for every core interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
- else\r
- {\r
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of an interrupt.\r
- The interrupt number can be positive to specify an external (device specific) interrupt,\r
- or negative to specify an internal (core) interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- SCB_AIRCR_SYSRESETREQ_Msk);\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm3.h\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM3_H_GENERIC\r
-#define __CORE_CM3_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M3\r
- @{\r
- */\r
-\r
-/* CMSIS CM3 definitions */\r
-#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03U) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
- #define __STATIC_INLINE static inline\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "core_cmInstr.h" /* Core Instruction Access */\r
-#include "core_cmFunc.h" /* Core Function Access */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM3_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM3_H_DEPENDANT\r
-#define __CORE_CM3_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM3_REV\r
- #define __CM3_REV 0x0200U\r
- #warning "__CM3_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M3 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24U];\r
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24U];\r
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24U];\r
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24U];\r
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56U];\r
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5U];\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#if (__CM3_REV < 0x0201U) /* core r2p1 */\r
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-#else\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-#endif\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1[1U];\r
-#endif\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable External Interrupt\r
- \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Disable External Interrupt\r
- \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of an external interrupt.\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of an external interrupt.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in NVIC and returns the active bit.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of an interrupt.\r
- \note The priority cannot be set for every core interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of an interrupt.\r
- The interrupt number can be positive to specify an external (device specific) interrupt,\r
- or negative to specify an internal (core) interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM3_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm4.h\r
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM4_H_GENERIC\r
-#define __CORE_CM4_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M4\r
- @{\r
- */\r
-\r
-/* CMSIS CM4 definitions */\r
-#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x04U) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
- #define __STATIC_INLINE static inline\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1U\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#endif\r
-\r
-#include "core_cmInstr.h" /* Core Instruction Access */\r
-#include "core_cmFunc.h" /* Core Function Access */\r
-#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM4_H_DEPENDANT\r
-#define __CORE_CM4_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM4_REV\r
- #define __CM4_REV 0x0000U\r
- #warning "__CM4_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __FPU_PRESENT\r
- #define __FPU_PRESENT 0U\r
- #warning "__FPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M4 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24U];\r
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24U];\r
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24U];\r
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24U];\r
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56U];\r
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5U];\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if (__FPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
- \brief Type definitions for the Floating Point Unit (FPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M4 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-#if (__FPU_PRESENT == 1U)\r
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable External Interrupt\r
- \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Disable External Interrupt\r
- \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of an external interrupt.\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of an external interrupt.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in NVIC and returns the active bit.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of an interrupt.\r
- \note The priority cannot be set for every core interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of an interrupt.\r
- The interrupt number can be positive to specify an external (device specific) interrupt,\r
- or negative to specify an internal (core) interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm7.h\r
- * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM7_H_GENERIC\r
-#define __CORE_CM7_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M7\r
- @{\r
- */\r
-\r
-/* CMSIS CM7 definitions */\r
-#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x07U) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
- #define __STATIC_INLINE static inline\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1U\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#endif\r
-\r
-#include "core_cmInstr.h" /* Core Instruction Access */\r
-#include "core_cmFunc.h" /* Core Function Access */\r
-#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM7_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM7_H_DEPENDANT\r
-#define __CORE_CM7_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM7_REV\r
- #define __CM7_REV 0x0000U\r
- #warning "__CM7_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __FPU_PRESENT\r
- #define __FPU_PRESENT 0U\r
- #warning "__FPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __ICACHE_PRESENT\r
- #define __ICACHE_PRESENT 0U\r
- #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __DCACHE_PRESENT\r
- #define __DCACHE_PRESENT 0U\r
- #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __DTCM_PRESENT\r
- #define __DTCM_PRESENT 0U\r
- #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 3U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M7 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24U];\r
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24U];\r
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24U];\r
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24U];\r
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56U];\r
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
- uint32_t RESERVED3[93U];\r
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
- uint32_t RESERVED4[15U];\r
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */\r
- uint32_t RESERVED5[1U];\r
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
- uint32_t RESERVED6[1U];\r
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
- uint32_t RESERVED7[6U];\r
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
- uint32_t RESERVED8[1U];\r
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */\r
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
-\r
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */\r
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
-\r
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */\r
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
-\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/* SCB Cache Level ID Register Definitions */\r
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
-\r
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
-\r
-/* SCB Cache Type Register Definitions */\r
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
-\r
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
-\r
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
-\r
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
-\r
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
-\r
-/* SCB Cache Size ID Register Definitions */\r
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
-\r
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
-\r
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
-\r
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
-\r
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
-\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
-\r
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
-\r
-/* SCB Cache Size Selection Register Definitions */\r
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
-\r
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
-\r
-/* SCB Software Triggered Interrupt Register Definitions */\r
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
-\r
-/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
-\r
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
-\r
-/* SCB D-Cache Clean by Set-way Register Definitions */\r
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
-\r
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
-\r
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
-\r
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
-\r
-/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
-\r
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
-\r
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
-\r
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
-\r
-/* Data Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
-\r
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
-\r
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
-\r
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
-\r
-/* AHBP Control Register Definitions */\r
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
-\r
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
-\r
-/* L1 Cache Control Register Definitions */\r
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
-\r
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
-\r
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
-\r
-/* AHBS Control Register Definitions */\r
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
-\r
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
-\r
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
-\r
-/* Auxiliary Bus Fault Status Register Definitions */\r
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
-\r
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
-\r
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
-\r
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
-\r
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
-\r
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */\r
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
-\r
-#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */\r
-#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
-\r
-#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */\r
-#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
- uint32_t RESERVED3[981U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if (__FPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
- \brief Type definitions for the Floating Point Unit (FPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
- __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/* Media and FP Feature Register 2 Definitions */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M4 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-#if (__FPU_PRESENT == 1U)\r
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable External Interrupt\r
- \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Disable External Interrupt\r
- \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of an external interrupt.\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of an external interrupt.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in NVIC and returns the active bit.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of an interrupt.\r
- \note The priority cannot be set for every core interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of an interrupt.\r
- The interrupt number can be positive to specify an external (device specific) interrupt,\r
- or negative to specify an internal (core) interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-/* ########################## FPU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
- \brief Function that provides FPU type.\r
- @{\r
- */\r
-\r
-/**\r
- \brief get FPU type\r
- \details returns the FPU type\r
- \returns\r
- - \b 0: No FPU\r
- - \b 1: Single precision FPU\r
- - \b 2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
- uint32_t mvfr0;\r
-\r
- mvfr0 = SCB->MVFR0;\r
- if ((mvfr0 & 0x00000FF0UL) == 0x220UL)\r
- {\r
- return 2UL; /* Double + Single precision FPU */\r
- }\r
- else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)\r
- {\r
- return 1UL; /* Single precision FPU */\r
- }\r
- else\r
- {\r
- return 0UL; /* No FPU */\r
- }\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ########################## Cache functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
- \brief Functions that configure Instruction and Data cache.\r
- @{\r
- */\r
-\r
-/* Cache Size ID Register Macros */\r
-#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
-#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
-\r
-\r
-/**\r
- \brief Enable I-Cache\r
- \details Turns on I-Cache\r
- */\r
-__STATIC_INLINE void SCB_EnableICache (void)\r
-{\r
- #if (__ICACHE_PRESENT == 1U)\r
- __DSB();\r
- __ISB();\r
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
- SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Disable I-Cache\r
- \details Turns off I-Cache\r
- */\r
-__STATIC_INLINE void SCB_DisableICache (void)\r
-{\r
- #if (__ICACHE_PRESENT == 1U)\r
- __DSB();\r
- __ISB();\r
- SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */\r
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Invalidate I-Cache\r
- \details Invalidates I-Cache\r
- */\r
-__STATIC_INLINE void SCB_InvalidateICache (void)\r
-{\r
- #if (__ICACHE_PRESENT == 1U)\r
- __DSB();\r
- __ISB();\r
- SCB->ICIALLU = 0UL;\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Enable D-Cache\r
- \details Turns on D-Cache\r
- */\r
-__STATIC_INLINE void SCB_EnableDCache (void)\r
-{\r
- #if (__DCACHE_PRESENT == 1U)\r
- uint32_t ccsidr;\r
- uint32_t sets;\r
- uint32_t ways;\r
-\r
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- /* invalidate D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways--);\r
- } while(sets--);\r
- __DSB();\r
-\r
- SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Disable D-Cache\r
- \details Turns off D-Cache\r
- */\r
-__STATIC_INLINE void SCB_DisableDCache (void)\r
-{\r
- #if (__DCACHE_PRESENT == 1U)\r
- uint32_t ccsidr;\r
- uint32_t sets;\r
- uint32_t ways;\r
-\r
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */\r
-\r
- /* clean & invalidate D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways--);\r
- } while(sets--);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Invalidate D-Cache\r
- \details Invalidates D-Cache\r
- */\r
-__STATIC_INLINE void SCB_InvalidateDCache (void)\r
-{\r
- #if (__DCACHE_PRESENT == 1U)\r
- uint32_t ccsidr;\r
- uint32_t sets;\r
- uint32_t ways;\r
-\r
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- /* invalidate D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways--);\r
- } while(sets--);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Clean D-Cache\r
- \details Cleans D-Cache\r
- */\r
-__STATIC_INLINE void SCB_CleanDCache (void)\r
-{\r
- #if (__DCACHE_PRESENT == 1U)\r
- uint32_t ccsidr;\r
- uint32_t sets;\r
- uint32_t ways;\r
-\r
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- /* clean D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
- ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways--);\r
- } while(sets--);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief Clean & Invalidate D-Cache\r
- \details Cleans and Invalidates D-Cache\r
- */\r
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
-{\r
- #if (__DCACHE_PRESENT == 1U)\r
- uint32_t ccsidr;\r
- uint32_t sets;\r
- uint32_t ways;\r
-\r
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
- __DSB();\r
-\r
- ccsidr = SCB->CCSIDR;\r
-\r
- /* clean & invalidate D-Cache */\r
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
- do {\r
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
- do {\r
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
- #if defined ( __CC_ARM )\r
- __schedule_barrier();\r
- #endif\r
- } while (ways--);\r
- } while(sets--);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief D-Cache Invalidate by address\r
- \details Invalidates D-Cache for the given address\r
- \param[in] addr address (aligned to 32-byte boundary)\r
- \param[in] dsize size of memory block (in number of bytes)\r
-*/\r
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
-{\r
- #if (__DCACHE_PRESENT == 1U)\r
- int32_t op_size = dsize;\r
- uint32_t op_addr = (uint32_t)addr;\r
- int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
-\r
- __DSB();\r
-\r
- while (op_size > 0) {\r
- SCB->DCIMVAC = op_addr;\r
- op_addr += linesize;\r
- op_size -= linesize;\r
- }\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief D-Cache Clean by address\r
- \details Cleans D-Cache for the given address\r
- \param[in] addr address (aligned to 32-byte boundary)\r
- \param[in] dsize size of memory block (in number of bytes)\r
-*/\r
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
-{\r
- #if (__DCACHE_PRESENT == 1)\r
- int32_t op_size = dsize;\r
- uint32_t op_addr = (uint32_t) addr;\r
- int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
-\r
- __DSB();\r
-\r
- while (op_size > 0) {\r
- SCB->DCCMVAC = op_addr;\r
- op_addr += linesize;\r
- op_size -= linesize;\r
- }\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/**\r
- \brief D-Cache Clean and Invalidate by address\r
- \details Cleans and invalidates D_Cache for the given address\r
- \param[in] addr address (aligned to 32-byte boundary)\r
- \param[in] dsize size of memory block (in number of bytes)\r
-*/\r
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
-{\r
- #if (__DCACHE_PRESENT == 1U)\r
- int32_t op_size = dsize;\r
- uint32_t op_addr = (uint32_t) addr;\r
- int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
-\r
- __DSB();\r
-\r
- while (op_size > 0) {\r
- SCB->DCCIMVAC = op_addr;\r
- op_addr += linesize;\r
- op_size -= linesize;\r
- }\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_CacheFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM7_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmFunc.h\r
- * @brief CMSIS Cortex-M Core Function Access Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CMFUNC_H\r
-#define __CORE_CMFUNC_H\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
-*/\r
-\r
-/*------------------ RealView Compiler -----------------*/\r
-#if defined ( __CC_ARM )\r
- #include "cmsis_armcc.h"\r
-\r
-/*------------------ ARM Compiler V6 -------------------*/\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #include "cmsis_armcc_V6.h"\r
-\r
-/*------------------ GNU Compiler ----------------------*/\r
-#elif defined ( __GNUC__ )\r
- #include "cmsis_gcc.h"\r
-\r
-/*------------------ ICC Compiler ----------------------*/\r
-#elif defined ( __ICCARM__ )\r
- #include <cmsis_iar.h>\r
-\r
-/*------------------ TI CCS Compiler -------------------*/\r
-#elif defined ( __TMS470__ )\r
- #include <cmsis_ccs.h>\r
-\r
-/*------------------ TASKING Compiler ------------------*/\r
-#elif defined ( __TASKING__ )\r
- /*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-/*------------------ COSMIC Compiler -------------------*/\r
-#elif defined ( __CSMC__ )\r
- #include <cmsis_csm.h>\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-#endif /* __CORE_CMFUNC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmInstr.h\r
- * @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CMINSTR_H\r
-#define __CORE_CMINSTR_H\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-/*------------------ RealView Compiler -----------------*/\r
-#if defined ( __CC_ARM )\r
- #include "cmsis_armcc.h"\r
-\r
-/*------------------ ARM Compiler V6 -------------------*/\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #include "cmsis_armcc_V6.h"\r
-\r
-/*------------------ GNU Compiler ----------------------*/\r
-#elif defined ( __GNUC__ )\r
- #include "cmsis_gcc.h"\r
-\r
-/*------------------ ICC Compiler ----------------------*/\r
-#elif defined ( __ICCARM__ )\r
- #include <cmsis_iar.h>\r
-\r
-/*------------------ TI CCS Compiler -------------------*/\r
-#elif defined ( __TMS470__ )\r
- #include <cmsis_ccs.h>\r
-\r
-/*------------------ TASKING Compiler ------------------*/\r
-#elif defined ( __TASKING__ )\r
- /*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-/*------------------ COSMIC Compiler -------------------*/\r
-#elif defined ( __CSMC__ )\r
- #include <cmsis_csm.h>\r
-\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-#endif /* __CORE_CMINSTR_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmSimd.h\r
- * @brief CMSIS Cortex-M SIMD Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CMSIMD_H\r
-#define __CORE_CMSIMD_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
- Access to dedicated SIMD instructions\r
- @{\r
-*/\r
-\r
-/*------------------ RealView Compiler -----------------*/\r
-#if defined ( __CC_ARM )\r
- #include "cmsis_armcc.h"\r
-\r
-/*------------------ ARM Compiler V6 -------------------*/\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #include "cmsis_armcc_V6.h"\r
-\r
-/*------------------ GNU Compiler ----------------------*/\r
-#elif defined ( __GNUC__ )\r
- #include "cmsis_gcc.h"\r
-\r
-/*------------------ ICC Compiler ----------------------*/\r
-#elif defined ( __ICCARM__ )\r
- #include <cmsis_iar.h>\r
-\r
-/*------------------ TI CCS Compiler -------------------*/\r
-#elif defined ( __TMS470__ )\r
- #include <cmsis_ccs.h>\r
-\r
-/*------------------ TASKING Compiler ------------------*/\r
-#elif defined ( __TASKING__ )\r
- /*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-/*------------------ COSMIC Compiler -------------------*/\r
-#elif defined ( __CSMC__ )\r
- #include <cmsis_csm.h>\r
-\r
-#endif\r
-\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CMSIMD_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_sc000.h\r
- * @brief CMSIS SC000 Core Peripheral Access Layer Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_SC000_H_GENERIC\r
-#define __CORE_SC000_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup SC000\r
- @{\r
- */\r
-\r
-/* CMSIS SC000 definitions */\r
-#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
-#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
-#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\r
- __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_SC (000U) /*!< Cortex secure core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
- #define __STATIC_INLINE static inline\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "core_cmInstr.h" /* Core Instruction Access */\r
-#include "core_cmFunc.h" /* Core Function Access */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC000_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_SC000_H_DEPENDANT\r
-#define __CORE_SC000_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __SC000_REV\r
- #define __SC000_REV 0x0000U\r
- #warning "__SC000_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 2U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group SC000 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[31U];\r
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[31U];\r
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[31U];\r
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[31U];\r
- uint32_t RESERVED4[64U];\r
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
-} NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- uint32_t RESERVED1[154U];\r
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
- Therefore they are not covered by the SC000 header file.\r
- @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of SC000 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
-\r
-\r
-/**\r
- \brief Enable External Interrupt\r
- \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Disable External Interrupt\r
- \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of an external interrupt.\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of an external interrupt.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of an interrupt.\r
- \note The priority cannot be set for every core interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
- else\r
- {\r
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of an interrupt.\r
- The interrupt number can be positive to specify an external (device specific) interrupt,\r
- or negative to specify an internal (core) interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- SCB_AIRCR_SYSRESETREQ_Msk);\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC000_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_sc300.h\r
- * @brief CMSIS SC300 Core Peripheral Access Layer Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_SC300_H_GENERIC\r
-#define __CORE_SC300_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup SC3000\r
- @{\r
- */\r
-\r
-/* CMSIS SC300 definitions */\r
-#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
-#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
-#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\r
- __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_SC (300U) /*!< Cortex secure core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
- #define __STATIC_INLINE static inline\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0U\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#endif\r
-\r
-#include "core_cmInstr.h" /* Core Instruction Access */\r
-#include "core_cmFunc.h" /* Core Function Access */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC300_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_SC300_H_DEPENDANT\r
-#define __CORE_SC300_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __SC300_REV\r
- #define __SC300_REV 0x0000U\r
- #warning "__SC300_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group SC300 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24U];\r
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24U];\r
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24U];\r
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24U];\r
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56U];\r
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5U];\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
- uint32_t RESERVED1[129U];\r
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- uint32_t RESERVED1[1U];\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable External Interrupt\r
- \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Disable External Interrupt\r
- \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of an external interrupt.\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of an external interrupt.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in NVIC and returns the active bit.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of an interrupt.\r
- \note The priority cannot be set for every core interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of an interrupt.\r
- The interrupt number can be positive to specify an external (device specific) interrupt,\r
- or negative to specify an internal (core) interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_SC300_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32_hal_legacy.h\r
- * @author MCD Application Team\r
- * @version V1.1.1\r
- * @date 12-May-2017\r
- * @brief This file contains aliases definition for the STM32Cube HAL constants \r
- * macros and functions maintained for legacy purpose.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32_HAL_LEGACY\r
-#define __STM32_HAL_LEGACY\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR\r
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR\r
-#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF\r
-#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR\r
-#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define ADC_RESOLUTION12b ADC_RESOLUTION_12B\r
-#define ADC_RESOLUTION10b ADC_RESOLUTION_10B\r
-#define ADC_RESOLUTION8b ADC_RESOLUTION_8B\r
-#define ADC_RESOLUTION6b ADC_RESOLUTION_6B\r
-#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN\r
-#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED\r
-#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV\r
-#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV\r
-#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV\r
-#define REGULAR_GROUP ADC_REGULAR_GROUP\r
-#define INJECTED_GROUP ADC_INJECTED_GROUP\r
-#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP\r
-#define AWD_EVENT ADC_AWD_EVENT\r
-#define AWD1_EVENT ADC_AWD1_EVENT\r
-#define AWD2_EVENT ADC_AWD2_EVENT\r
-#define AWD3_EVENT ADC_AWD3_EVENT\r
-#define OVR_EVENT ADC_OVR_EVENT\r
-#define JQOVF_EVENT ADC_JQOVF_EVENT\r
-#define ALL_CHANNELS ADC_ALL_CHANNELS\r
-#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS\r
-#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS\r
-#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR\r
-#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8\r
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO \r
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 \r
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO \r
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 \r
-#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO\r
-#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11\r
-#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1\r
-#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE\r
-#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING\r
-#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING\r
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\r
-#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5\r
-\r
-#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY\r
-#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY\r
-#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC\r
-#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC\r
-#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL\r
-#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL\r
-#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 \r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */ \r
- \r
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG \r
-\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE\r
-#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE\r
-#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1\r
-#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2\r
-#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3\r
-#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4\r
-#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5\r
-#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6\r
-#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7\r
-#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */\r
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR\r
-#if defined(STM32F373xC) || defined(STM32F378xx)\r
-#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1\r
-#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR\r
-#endif /* STM32F373xC || STM32F378xx */\r
-\r
-#if defined(STM32L0) || defined(STM32L4)\r
-#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON\r
-\r
-#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1\r
-#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2\r
-#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3\r
-#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4\r
-#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5\r
-#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6\r
- \r
-#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT\r
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT\r
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT\r
-#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT\r
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1\r
-#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2\r
-#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1\r
-#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2\r
-#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1\r
-#if defined(STM32L0)\r
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */\r
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */\r
-/* to the second dedicated IO (only for COMP2). */\r
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2\r
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2\r
-#else\r
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2\r
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3\r
-#endif\r
-#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4\r
-#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5\r
-\r
-#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW\r
-#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH\r
-\r
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */\r
-/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */\r
-#if defined(COMP_CSR_LOCK)\r
-#define COMP_FLAG_LOCK COMP_CSR_LOCK\r
-#elif defined(COMP_CSR_COMP1LOCK)\r
-#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK\r
-#elif defined(COMP_CSR_COMPxLOCK)\r
-#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK\r
-#endif\r
-\r
-#if defined(STM32L4)\r
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1\r
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1\r
-#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1\r
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2\r
-#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2\r
-#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2\r
-#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE\r
-#endif\r
-\r
-#if defined(STM32L0)\r
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED\r
-#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER\r
-#else\r
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED\r
-#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED\r
-#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER\r
-#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER\r
-#endif\r
-\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE\r
-#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define DAC1_CHANNEL_1 DAC_CHANNEL_1\r
-#define DAC1_CHANNEL_2 DAC_CHANNEL_2\r
-#define DAC2_CHANNEL_1 DAC_CHANNEL_1\r
-#define DAC_WAVE_NONE 0x00000000U\r
-#define DAC_WAVE_NOISE DAC_CR_WAVE1_0\r
-#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1\r
-#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE\r
-#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE\r
-#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 \r
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 \r
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 \r
-#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 \r
-#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 \r
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32\r
-#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6\r
-#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 \r
-#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 \r
-#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 \r
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 \r
-#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 \r
-#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 \r
-#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 \r
-#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 \r
- \r
-#define IS_HAL_REMAPDMA IS_DMA_REMAP \r
-#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE\r
-#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE\r
- \r
- \r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE\r
-#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
-#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD\r
-#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD\r
-#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS\r
-#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES\r
-#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES\r
-#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE\r
-#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE\r
-#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE\r
-#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE\r
-#define OBEX_PCROP OPTIONBYTE_PCROP\r
-#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG\r
-#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE\r
-#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE\r
-#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE\r
-#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD\r
-#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD\r
-#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE\r
-#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD\r
-#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD\r
-#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE\r
-#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r
-#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD\r
-#define PAGESIZE FLASH_PAGE_SIZE\r
-#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE\r
-#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
-#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD\r
-#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1\r
-#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2\r
-#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3\r
-#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4\r
-#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST\r
-#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST\r
-#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA\r
-#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB\r
-#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA\r
-#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB\r
-#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE\r
-#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN\r
-#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE\r
-#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN\r
-#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE\r
-#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD\r
-#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG\r
-#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS\r
-#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP\r
-#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV\r
-#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR\r
-#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG\r
-#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION\r
-#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA\r
-#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE\r
-#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE\r
-#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS\r
-#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS\r
-#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST\r
-#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR\r
-#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO\r
-#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION\r
-#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS\r
-#define OB_WDG_SW OB_IWDG_SW\r
-#define OB_WDG_HW OB_IWDG_HW\r
-#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET\r
-#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET\r
-#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET\r
-#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET\r
-#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR\r
-#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0\r
-#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1\r
-#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2\r
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3\r
-/**\r
- * @}\r
- */\r
- \r
-\r
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r
- * @{\r
- */\r
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)\r
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE\r
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE\r
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8\r
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16\r
-#else\r
-#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r
-#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r
-#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8\r
-#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef\r
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define GET_GPIO_SOURCE GPIO_GET_INDEX\r
-#define GET_GPIO_INDEX GPIO_GET_INDEX\r
-\r
-#if defined(STM32F4)\r
-#define GPIO_AF12_SDMMC GPIO_AF12_SDIO\r
-#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO\r
-#endif\r
-\r
-#if defined(STM32F7)\r
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1\r
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1\r
-#endif\r
-\r
-#if defined(STM32L4)\r
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1\r
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1\r
-#endif\r
-\r
-#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1\r
-#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1\r
-#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1\r
-\r
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)\r
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW \r
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM \r
-#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH \r
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH \r
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */\r
-\r
-#if defined(STM32L1) \r
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW \r
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM \r
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH \r
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH \r
-#endif /* STM32L1 */\r
-\r
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)\r
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW\r
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH\r
-#endif /* STM32F0 || STM32F3 || STM32F1 */\r
-\r
-#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#if defined(STM32H7)\r
- #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE\r
- #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE\r
- #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET\r
- #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET\r
- #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE\r
- #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE \r
-#endif /* STM32H7 */\r
- \r
- \r
-/**\r
- * @}\r
- */ \r
- \r
- \r
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6\r
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7\r
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7\r
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7\r
- \r
-#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER\r
-#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER\r
-#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD\r
-#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD\r
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER\r
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER\r
-#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE\r
-#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE\r
-#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE\r
-#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE\r
-#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE\r
-#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE\r
-#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE\r
-#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE\r
-#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE\r
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)\r
-#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
-#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
-#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
-#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
-#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
-#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE\r
-#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define KR_KEY_RELOAD IWDG_KEY_RELOAD\r
-#define KR_KEY_ENABLE IWDG_KEY_ENABLE\r
-#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE\r
-#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r
-\r
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING\r
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING\r
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING\r
-\r
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION\r
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS \r
-\r
-/* The following 3 definition have also been present in a temporary version of lptim.h */\r
-/* They need to be renamed also to the right name, just in case */\r
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b\r
-#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b\r
-#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b\r
-#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b\r
-\r
-#define NAND_AddressTypedef NAND_AddressTypeDef\r
-\r
-#define __ARRAY_ADDRESS ARRAY_ADDRESS\r
-#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE\r
-#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE\r
-#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE\r
-#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define NOR_StatusTypedef HAL_NOR_StatusTypeDef\r
-#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS\r
-#define NOR_ONGOING HAL_NOR_STATUS_ONGOING\r
-#define NOR_ERROR HAL_NOR_STATUS_ERROR\r
-#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT\r
-\r
-#define __NOR_WRITE NOR_WRITE\r
-#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0\r
-#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1\r
-#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2\r
-#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3\r
- \r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 \r
-\r
-#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
-#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
-\r
-#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
-#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
-\r
-#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0\r
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 \r
-\r
-#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1\r
- \r
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO \r
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 \r
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 \r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS\r
-#if defined(STM32F7) \r
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-/* Compact Flash-ATA registers description */\r
-#define CF_DATA ATA_DATA \r
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT \r
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER \r
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW \r
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH \r
-#define CF_CARD_HEAD ATA_CARD_HEAD \r
-#define CF_STATUS_CMD ATA_STATUS_CMD \r
-#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE\r
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA \r
-\r
-/* Compact Flash-ATA commands */\r
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD \r
-#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD\r
-#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD\r
-#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD\r
-\r
-#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef\r
-#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS\r
-#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING\r
-#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR\r
-#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define FORMAT_BIN RTC_FORMAT_BIN\r
-#define FORMAT_BCD RTC_FORMAT_BCD\r
-\r
-#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE\r
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE\r
-#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE\r
-#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
-\r
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE \r
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE \r
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE \r
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE \r
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT \r
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT \r
-\r
-#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT\r
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 \r
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1\r
-#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2\r
-\r
-#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE\r
-#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1\r
-#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1\r
-\r
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT \r
-#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 \r
-#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE\r
-#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE\r
-\r
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
-\r
-#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE\r
-#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE\r
-\r
-#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE\r
-#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE\r
-#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE\r
-#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE\r
-#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE\r
-#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE\r
-#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE\r
-#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE\r
-#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE\r
-#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE\r
-#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE\r
-#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE\r
-#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE\r
-\r
-#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE\r
-#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE\r
-\r
-#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE\r
-#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK\r
-#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK\r
- \r
-#define TIM_DMABase_CR1 TIM_DMABASE_CR1\r
-#define TIM_DMABase_CR2 TIM_DMABASE_CR2\r
-#define TIM_DMABase_SMCR TIM_DMABASE_SMCR\r
-#define TIM_DMABase_DIER TIM_DMABASE_DIER\r
-#define TIM_DMABase_SR TIM_DMABASE_SR\r
-#define TIM_DMABase_EGR TIM_DMABASE_EGR\r
-#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1\r
-#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2\r
-#define TIM_DMABase_CCER TIM_DMABASE_CCER\r
-#define TIM_DMABase_CNT TIM_DMABASE_CNT\r
-#define TIM_DMABase_PSC TIM_DMABASE_PSC\r
-#define TIM_DMABase_ARR TIM_DMABASE_ARR\r
-#define TIM_DMABase_RCR TIM_DMABASE_RCR\r
-#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1\r
-#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2\r
-#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3\r
-#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4\r
-#define TIM_DMABase_BDTR TIM_DMABASE_BDTR\r
-#define TIM_DMABase_DCR TIM_DMABASE_DCR\r
-#define TIM_DMABase_DMAR TIM_DMABASE_DMAR\r
-#define TIM_DMABase_OR1 TIM_DMABASE_OR1\r
-#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3\r
-#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5\r
-#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6\r
-#define TIM_DMABase_OR2 TIM_DMABASE_OR2\r
-#define TIM_DMABase_OR3 TIM_DMABASE_OR3\r
-#define TIM_DMABase_OR TIM_DMABASE_OR\r
-\r
-#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE\r
-#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1\r
-#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2\r
-#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3\r
-#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4\r
-#define TIM_EventSource_COM TIM_EVENTSOURCE_COM\r
-#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER\r
-#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK\r
-#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2\r
-\r
-#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER\r
-#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS\r
-#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS\r
-#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS\r
-#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS\r
-#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS\r
-#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS\r
-#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS\r
-#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS\r
-#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS\r
-#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS\r
-#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS\r
-#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS\r
-#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS\r
-#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS\r
-#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS\r
-#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS\r
-#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING\r
-#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
-#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
-#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
-#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
-\r
-#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r
-#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r
-\r
-#define __DIV_SAMPLING16 UART_DIV_SAMPLING16\r
-#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16\r
-#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16\r
-#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16\r
-\r
-#define __DIV_SAMPLING8 UART_DIV_SAMPLING8\r
-#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8\r
-#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8\r
-#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8\r
-\r
-#define __DIV_LPUART UART_DIV_LPUART\r
-\r
-#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE\r
-#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE\r
-#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE\r
-\r
-#define USARTNACK_ENABLED USART_NACK_ENABLE\r
-#define USARTNACK_DISABLED USART_NACK_DISABLE\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define CFR_BASE WWDG_CFR_BASE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0\r
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1\r
-#define CAN_IT_RQCP0 CAN_IT_TME\r
-#define CAN_IT_RQCP1 CAN_IT_TME\r
-#define CAN_IT_RQCP2 CAN_IT_TME\r
-#define INAK_TIMEOUT CAN_TIMEOUT_VALUE\r
-#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE\r
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)\r
-#define CAN_TXSTATUS_OK ((uint8_t)0x01)\r
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define VLAN_TAG ETH_VLAN_TAG\r
-#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD\r
-#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD\r
-#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD\r
-#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK\r
-#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK\r
-#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK\r
-#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK\r
-\r
-#define ETH_MMCCR 0x00000100U\r
-#define ETH_MMCRIR 0x00000104U\r
-#define ETH_MMCTIR 0x00000108U\r
-#define ETH_MMCRIMR 0x0000010CU\r
-#define ETH_MMCTIMR 0x00000110U\r
-#define ETH_MMCTGFSCCR 0x0000014CU\r
-#define ETH_MMCTGFMSCCR 0x00000150U\r
-#define ETH_MMCTGFCR 0x00000168U\r
-#define ETH_MMCRFCECR 0x00000194U\r
-#define ETH_MMCRFAECR 0x00000198U\r
-#define ETH_MMCRGUFCR 0x000001C4U\r
- \r
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */\r
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */\r
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */\r
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */\r
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */\r
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */\r
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */\r
-#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */\r
-#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */\r
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
-#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */\r
-#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */\r
-#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */\r
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */\r
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */\r
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */\r
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */\r
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */\r
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */\r
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR\r
-#define DCMI_IT_OVF DCMI_IT_OVR\r
-#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI\r
-#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI\r
-\r
-#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop\r
-#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop\r
-#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop\r
-\r
-/**\r
- * @}\r
- */ \r
- \r
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\\r
- defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\r
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888\r
-#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 \r
-#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 \r
-#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555\r
-#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444\r
-\r
-#define CM_ARGB8888 DMA2D_INPUT_ARGB8888\r
-#define CM_RGB888 DMA2D_INPUT_RGB888 \r
-#define CM_RGB565 DMA2D_INPUT_RGB565 \r
-#define CM_ARGB1555 DMA2D_INPUT_ARGB1555\r
-#define CM_ARGB4444 DMA2D_INPUT_ARGB4444\r
-#define CM_L8 DMA2D_INPUT_L8 \r
-#define CM_AL44 DMA2D_INPUT_AL44 \r
-#define CM_AL88 DMA2D_INPUT_AL88 \r
-#define CM_L4 DMA2D_INPUT_L4 \r
-#define CM_A8 DMA2D_INPUT_A8 \r
-#define CM_A4 DMA2D_INPUT_A4 \r
-/**\r
- * @}\r
- */ \r
-#endif /* STM32L4 || STM32F7*/\r
-\r
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r
- * @{\r
- */ \r
-#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef\r
-#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef\r
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish\r
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish\r
-#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish\r
-#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish\r
-\r
-/*HASH Algorithm Selection*/\r
-\r
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 \r
-#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224\r
-#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256\r
-#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5\r
-\r
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH \r
-#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC\r
-\r
-#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY\r
-#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r
-#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect\r
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r
-#if defined(STM32L0)\r
-#else\r
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r
-#endif\r
-#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram\r
-#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown\r
-#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown\r
-#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock\r
-#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock\r
-#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase\r
-#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program\r
-\r
- /**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter\r
-#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter\r
-#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter\r
-#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter\r
-\r
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r
- /**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD\r
-#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg\r
-#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown\r
-#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor\r
-#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg\r
-#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown\r
-#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor\r
-#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler\r
-#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD\r
-#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler\r
-#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback\r
-#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive\r
-#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive\r
-#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC\r
-#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC\r
-#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM\r
-\r
-#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL\r
-#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING\r
-#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING\r
-#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING\r
-#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING\r
-#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING\r
-#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING\r
-\r
-#define CR_OFFSET_BB PWR_CR_OFFSET_BB\r
-#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB\r
-\r
-#define DBP_BitNumber DBP_BIT_NUMBER\r
-#define PVDE_BitNumber PVDE_BIT_NUMBER\r
-#define PMODE_BitNumber PMODE_BIT_NUMBER\r
-#define EWUP_BitNumber EWUP_BIT_NUMBER\r
-#define FPDS_BitNumber FPDS_BIT_NUMBER\r
-#define ODEN_BitNumber ODEN_BIT_NUMBER\r
-#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER\r
-#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER\r
-#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER\r
-#define BRE_BitNumber BRE_BIT_NUMBER\r
-\r
-#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL\r
- \r
- /**\r
- * @}\r
- */ \r
- \r
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT\r
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback \r
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt\r
-#define HAL_TIM_DMAError TIM_DMAError\r
-#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt\r
-#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r
- * @{\r
- */ \r
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose\r
- * @{\r
- */ \r
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback\r
-#define HAL_LTDC_Relaod HAL_LTDC_Reload\r
-#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig\r
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig\r
-/**\r
- * @}\r
- */ \r
- \r
- \r
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macros ------------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define AES_IT_CC CRYP_IT_CC\r
-#define AES_IT_ERR CRYP_IT_ERR\r
-#define AES_FLAG_CCF CRYP_FLAG_CCF\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE\r
-#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH\r
-#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r
-#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM\r
-#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC\r
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM \r
-#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC\r
-#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r
-#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK\r
-#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG\r
-#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG\r
-#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE\r
-#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE\r
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE\r
-\r
-#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY\r
-#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48\r
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS\r
-#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER\r
-#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __ADC_ENABLE __HAL_ADC_ENABLE\r
-#define __ADC_DISABLE __HAL_ADC_DISABLE\r
-#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS\r
-#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS\r
-#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE\r
-#define __ADC_IS_ENABLED ADC_IS_ENABLE\r
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR\r
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING\r
-#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE\r
-\r
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
-#define __HAL_ADC_JSQR_RK ADC_JSQR_RK\r
-#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT\r
-#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR\r
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION\r
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE\r
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS\r
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS\r
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM\r
-#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT\r
-#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS\r
-#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN\r
-#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ\r
-#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET\r
-#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET\r
-#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL\r
-#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL\r
-#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET\r
-#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET\r
-#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD\r
-\r
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION\r
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r
-#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER\r
-#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI\r
-#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
-#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r
-#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER\r
-#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE\r
-\r
-#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT\r
-#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT\r
-#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL\r
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM\r
-#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET\r
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE\r
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE\r
-#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER\r
-\r
-#define __HAL_ADC_SQR1 ADC_SQR1\r
-#define __HAL_ADC_SMPR1 ADC_SMPR1\r
-#define __HAL_ADC_SMPR2 ADC_SMPR2\r
-#define __HAL_ADC_SQR3_RK ADC_SQR3_RK\r
-#define __HAL_ADC_SQR2_RK ADC_SQR2_RK\r
-#define __HAL_ADC_SQR1_RK ADC_SQR1_RK\r
-#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS\r
-#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS\r
-#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV\r
-#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection\r
-#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq\r
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
-#define __HAL_ADC_JSQR ADC_JSQR\r
-\r
-#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL\r
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS\r
-#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF\r
-#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT\r
-#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS\r
-#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN\r
-#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR\r
-#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT\r
-#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT\r
-#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT\r
-#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r
-\r
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r
-\r
-\r
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#if defined(STM32F3)\r
-#define COMP_START __HAL_COMP_ENABLE\r
-#define COMP_STOP __HAL_COMP_DISABLE\r
-#define COMP_LOCK __HAL_COMP_LOCK\r
- \r
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
- __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
-# endif\r
-# if defined(STM32F302xE) || defined(STM32F302xC)\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
- __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
-# endif\r
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \\r
- __HAL_COMP_COMP7_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \\r
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \\r
- __HAL_COMP_COMP7_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \\r
- __HAL_COMP_COMP7_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \\r
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \\r
- __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())\r
-# endif\r
-# if defined(STM32F373xC) ||defined(STM32F378xx)\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
- __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
-# endif\r
-#else\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
- __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
-#endif\r
-\r
-#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE\r
-\r
-#if defined(STM32L0) || defined(STM32L4)\r
-/* Note: On these STM32 families, the only argument of this macro */\r
-/* is COMP_FLAG_LOCK. */\r
-/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */\r
-/* argument. */\r
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(STM32L0) || defined(STM32L4)\r
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
-/**\r
- * @}\r
- */\r
-#endif\r
-\r
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\r
- ((WAVE) == DAC_WAVE_NOISE)|| \\r
- ((WAVE) == DAC_WAVE_TRIANGLE))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define IS_WRPAREA IS_OB_WRPAREA\r
-#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM\r
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r
-#define IS_TYPEERASE IS_FLASH_TYPEERASE\r
-#define IS_NBSECTORS IS_FLASH_NBSECTORS\r
-#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2\r
-#define __HAL_I2C_GENERATE_START I2C_GENERATE_START\r
-#if defined(STM32F1)\r
-#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE\r
-#else\r
-#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE\r
-#endif /* STM32F1 */\r
-#define __HAL_I2C_RISE_TIME I2C_RISE_TIME\r
-#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD\r
-#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST\r
-#define __HAL_I2C_SPEED I2C_SPEED\r
-#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE\r
-#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ\r
-#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS\r
-#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE\r
-#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ\r
-#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB\r
-#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB\r
-#define __HAL_I2C_FREQRANGE I2C_FREQRANGE\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE\r
-#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define __IRDA_DISABLE __HAL_IRDA_DISABLE\r
-#define __IRDA_ENABLE __HAL_IRDA_ENABLE\r
-\r
-#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
-#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
-#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
-#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
-\r
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE \r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS\r
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT\r
-#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT\r
-#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE\r
-\r
-/**\r
- * @}\r
- */\r
- \r
- \r
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD\r
-#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX\r
-#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX\r
-#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX\r
-#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX\r
-#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L\r
-#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H\r
-#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM\r
-#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES\r
-#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX\r
-#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT\r
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION\r
-#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
-#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE\r
-#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE\r
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine\r
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine\r
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig\r
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig\r
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)\r
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)\r
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)\r
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention\r
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention\r
-#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2\r
-#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2\r
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB\r
-#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB\r
-\r
-#if defined (STM32F4)\r
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()\r
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()\r
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() \r
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r
-#else\r
-#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r
-#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT\r
-#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT\r
-#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG \r
-#endif /* STM32F4 */\r
-/** \r
- * @}\r
- */ \r
- \r
- \r
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI\r
-#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI\r
-\r
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r
-\r
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE\r
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE\r
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET\r
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET\r
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE\r
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE\r
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET\r
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET\r
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE \r
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE \r
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE\r
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE\r
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r
-#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r
-#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r
-#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE\r
-#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE\r
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET\r
-#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET\r
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
-#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
-#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
-#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
-#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r
-#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE\r
-#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE\r
-#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET\r
-#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET\r
-#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r
-#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r
-#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE\r
-#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE\r
-#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET\r
-#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET\r
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r
-#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE\r
-#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE\r
-#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET\r
-#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET\r
-#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r
-#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
-#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE \r
-#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
-#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
-#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
-#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE \r
-#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
-#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
-#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE\r
-#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE\r
-#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET\r
-#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET\r
-#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE\r
-#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE\r
-#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET\r
-#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET\r
-#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE\r
-#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE\r
-#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET\r
-#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE\r
-#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE\r
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r
-#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE\r
-#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE\r
-#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET\r
-#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET\r
-#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r
-#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r
-#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE\r
-#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE\r
-#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET\r
-#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET\r
-#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r
-#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r
-\r
-#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
-#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r
-#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r
-#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r
-#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE \r
-#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE \r
-#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE \r
-#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE \r
-#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r
-#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r
-#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE\r
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE \r
-#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE\r
-#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET\r
-#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET\r
-#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r
-#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE \r
-#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE\r
-#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE\r
-#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET\r
-#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET\r
-#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE \r
-#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE\r
-#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE\r
-#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET\r
-#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET\r
-#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE \r
-#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE\r
-#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE\r
-#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET\r
-#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET\r
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE \r
-#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE \r
-#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE \r
-#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE \r
-#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE \r
-#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE \r
-#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE \r
-#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE\r
-#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE\r
-#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE \r
-#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE \r
-#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE\r
-#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE\r
-#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET\r
-#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET\r
-#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE \r
-#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE\r
-#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE\r
-#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET\r
-#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET\r
-#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE \r
-#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE\r
-#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE\r
-#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET\r
-#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET\r
-#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE \r
-#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE\r
-#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE\r
-#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET\r
-#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET\r
-#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE \r
-#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE\r
-#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE\r
-#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET\r
-#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE \r
-#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE\r
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE \r
-#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE\r
-#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE\r
-#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET\r
-#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET\r
-#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE \r
-#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE\r
-#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE\r
-#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET\r
-#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET\r
-#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE \r
-#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE\r
-#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE\r
-#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET\r
-#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET\r
-#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE \r
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
-#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET \r
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
-#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED\r
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED\r
-#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET \r
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE \r
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED\r
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED \r
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET \r
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE \r
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE \r
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE \r
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE \r
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE \r
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET\r
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET\r
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE \r
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE \r
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE\r
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE\r
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET\r
-#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET\r
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r
-\r
-/* alias define maintained for legacy */\r
-#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
-#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
-\r
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE\r
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE\r
-#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE\r
-#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE\r
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE\r
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE\r
-#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE\r
-#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE\r
-#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE\r
-#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE\r
-#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE\r
-#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE\r
-#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE\r
-#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE\r
-#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE\r
-#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE\r
-#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE\r
-#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE\r
-#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE\r
-#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE\r
-#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE\r
-#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE\r
-\r
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET\r
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET\r
-#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET\r
-#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET\r
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET\r
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET\r
-#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET\r
-#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET\r
-#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET\r
-#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET\r
-#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET\r
-#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET\r
-#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET\r
-#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET\r
-#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET\r
-#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET\r
-#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET\r
-#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET\r
-#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET\r
-#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET\r
-#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET\r
-#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET\r
-\r
-#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED\r
-#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED\r
-#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED\r
-#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED\r
-#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED\r
-#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED\r
-#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED\r
-#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED\r
-#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED\r
-#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED\r
-#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED\r
-#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED\r
-#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED\r
-#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED\r
-#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED\r
-#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED\r
-#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED\r
-#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED\r
-#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED\r
-#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED\r
-#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED\r
-#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED\r
-#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED\r
-#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED\r
-#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED\r
-#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED\r
-#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED\r
-#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED\r
-#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED\r
-#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED\r
-#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED\r
-#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED\r
-#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED\r
-#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED\r
-#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED\r
-#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED\r
-#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED\r
-#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED\r
-#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED\r
-#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED\r
-#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED\r
-#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED\r
-#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED\r
-#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED\r
-#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED\r
-#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED\r
-#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED\r
-#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED\r
-#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED\r
-#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED\r
-#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED\r
-#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED\r
-#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED\r
-#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED\r
-#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED\r
-#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED\r
-#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED\r
-#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED\r
-#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED\r
-#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED\r
-#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED\r
-#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED\r
-#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED\r
-#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED\r
-#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED\r
-#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED\r
-#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED\r
-#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED\r
-#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED\r
-#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED\r
-#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED\r
-#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED\r
-#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED\r
-#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED\r
-#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED\r
-#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED\r
-#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED\r
-#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED\r
-#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED\r
-#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED\r
-#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED\r
-#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED\r
-#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED\r
-#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED\r
-#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED\r
-#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED\r
-#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED\r
-#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED\r
-#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED\r
-#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED\r
-#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED\r
-#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED\r
-#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED\r
-#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED\r
-#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED\r
-#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED\r
-#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED\r
-#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED\r
-#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED\r
-#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED\r
-#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED\r
-#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED\r
-#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED\r
-#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED\r
-#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED\r
-#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED\r
-#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED\r
-#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED\r
-#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED\r
-#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED\r
-#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED\r
-#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED\r
-#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED\r
-#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED\r
-#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED\r
-#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED\r
-\r
-#if defined(STM32F4)\r
-#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
-#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
-#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED\r
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED\r
-#define Sdmmc1ClockSelection SdioClockSelection\r
-#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO\r
-#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48\r
-#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK\r
-#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG\r
-#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE\r
-#endif\r
-\r
-#if defined(STM32F7) || defined(STM32L4)\r
-#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET\r
-#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET\r
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE\r
-#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE\r
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED\r
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED\r
-#define SdioClockSelection Sdmmc1ClockSelection\r
-#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1\r
-#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG\r
-#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE \r
-#endif\r
-\r
-#if defined(STM32H7)\r
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()\r
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()\r
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()\r
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()\r
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()\r
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()\r
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()\r
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()\r
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()\r
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()\r
-\r
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()\r
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()\r
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()\r
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()\r
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()\r
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()\r
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()\r
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()\r
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()\r
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()\r
-#endif\r
-\r
-#if defined(STM32F7)\r
-#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48\r
-#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK\r
-#endif\r
-\r
-#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG\r
-#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG\r
-\r
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE\r
-\r
-#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE\r
-#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE\r
-#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK\r
-#define IS_RCC_HCLK_DIV IS_RCC_PCLK\r
-#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK\r
-\r
-#define RCC_IT_HSI14 RCC_IT_HSI14RDY\r
-\r
-#define RCC_IT_CSSLSE RCC_IT_LSECSS\r
-#define RCC_IT_CSSHSE RCC_IT_CSS\r
-\r
-#define RCC_PLLMUL_3 RCC_PLL_MUL3\r
-#define RCC_PLLMUL_4 RCC_PLL_MUL4\r
-#define RCC_PLLMUL_6 RCC_PLL_MUL6\r
-#define RCC_PLLMUL_8 RCC_PLL_MUL8\r
-#define RCC_PLLMUL_12 RCC_PLL_MUL12\r
-#define RCC_PLLMUL_16 RCC_PLL_MUL16\r
-#define RCC_PLLMUL_24 RCC_PLL_MUL24\r
-#define RCC_PLLMUL_32 RCC_PLL_MUL32\r
-#define RCC_PLLMUL_48 RCC_PLL_MUL48\r
-\r
-#define RCC_PLLDIV_2 RCC_PLL_DIV2\r
-#define RCC_PLLDIV_3 RCC_PLL_DIV3\r
-#define RCC_PLLDIV_4 RCC_PLL_DIV4\r
-\r
-#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE\r
-#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG\r
-#define RCC_MCO_NODIV RCC_MCODIV_1\r
-#define RCC_MCO_DIV1 RCC_MCODIV_1\r
-#define RCC_MCO_DIV2 RCC_MCODIV_2\r
-#define RCC_MCO_DIV4 RCC_MCODIV_4\r
-#define RCC_MCO_DIV8 RCC_MCODIV_8\r
-#define RCC_MCO_DIV16 RCC_MCODIV_16\r
-#define RCC_MCO_DIV32 RCC_MCODIV_32\r
-#define RCC_MCO_DIV64 RCC_MCODIV_64\r
-#define RCC_MCO_DIV128 RCC_MCODIV_128\r
-#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK\r
-#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI\r
-#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE\r
-#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK\r
-#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI\r
-#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14\r
-#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48\r
-#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE\r
-#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK\r
-#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK\r
-#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2\r
-\r
-#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK\r
-\r
-#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1\r
-#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL\r
-#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI\r
-#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL\r
-#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL\r
-#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5\r
-#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2\r
-#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3\r
-\r
-#define HSION_BitNumber RCC_HSION_BIT_NUMBER\r
-#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER\r
-#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER\r
-#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER\r
-#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER\r
-#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER\r
-#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER\r
-#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER\r
-#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER\r
-#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER\r
-#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER\r
-#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER\r
-#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER\r
-#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER\r
-#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER\r
-#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER\r
-#define LSION_BitNumber RCC_LSION_BIT_NUMBER\r
-#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER\r
-#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER\r
-#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER\r
-#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER\r
-#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER\r
-#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER\r
-#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER\r
-#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER\r
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER\r
-#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS\r
-#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS\r
-#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS\r
-#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS\r
-#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE\r
-#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE\r
-\r
-#define CR_HSION_BB RCC_CR_HSION_BB\r
-#define CR_CSSON_BB RCC_CR_CSSON_BB\r
-#define CR_PLLON_BB RCC_CR_PLLON_BB\r
-#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB\r
-#define CR_MSION_BB RCC_CR_MSION_BB\r
-#define CSR_LSION_BB RCC_CSR_LSION_BB\r
-#define CSR_LSEON_BB RCC_CSR_LSEON_BB\r
-#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB\r
-#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB\r
-#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB\r
-#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB\r
-#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB\r
-#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB\r
-#define CR_HSEON_BB RCC_CR_HSEON_BB\r
-#define CSR_RMVF_BB RCC_CSR_RMVF_BB\r
-#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB\r
-#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB\r
-\r
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE\r
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE\r
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE\r
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE\r
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE\r
-\r
-#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT\r
-\r
-#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN\r
-#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF\r
-\r
-#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48\r
-#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ\r
-#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP\r
-#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ\r
-#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE\r
-#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48\r
-\r
-#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE\r
-#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE\r
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED\r
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED\r
-#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET\r
-#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET\r
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED\r
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED\r
-#define DfsdmClockSelection Dfsdm1ClockSelection\r
-#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1\r
-#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2\r
-#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK\r
-#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG\r
-#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE\r
-#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2\r
-#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1\r
-#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1\r
-#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1\r
-\r
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1\r
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2\r
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1\r
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2\r
-#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2\r
-#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2\r
-#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) \r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG\r
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT\r
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT\r
-\r
-#if defined (STM32F1)\r
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r
-\r
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r
-\r
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r
-\r
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()\r
-\r
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r
-#else\r
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r
-#endif /* STM32F1 */\r
-\r
-#define IS_ALARM IS_RTC_ALARM\r
-#define IS_ALARM_MASK IS_RTC_ALARM_MASK\r
-#define IS_TAMPER IS_RTC_TAMPER\r
-#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE\r
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER \r
-#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT\r
-#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE\r
-#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION\r
-#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE\r
-#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ\r
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r
-#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER\r
-#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK\r
-#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER\r
-\r
-#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE\r
-#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE\r
-#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS\r
-\r
-#if defined(STM32F4) || defined(STM32F2)\r
-#define SD_SDMMC_DISABLED SD_SDIO_DISABLED\r
-#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY \r
-#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED \r
-#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION \r
-#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND \r
-#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT \r
-#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED \r
-#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE \r
-#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE \r
-#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE \r
-#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL \r
-#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT \r
-#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT \r
-#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG \r
-#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG \r
-#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT \r
-#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT \r
-#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS \r
-#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT \r
-#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND\r
-/* alias CMSIS */\r
-#define SDMMC1_IRQn SDIO_IRQn\r
-#define SDMMC1_IRQHandler SDIO_IRQHandler\r
-#endif\r
-\r
-#if defined(STM32F7) || defined(STM32L4)\r
-#define SD_SDIO_DISABLED SD_SDMMC_DISABLED\r
-#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY \r
-#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED \r
-#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION\r
-#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND\r
-#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT\r
-#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED\r
-#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE\r
-#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE\r
-#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE\r
-#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE\r
-#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT\r
-#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT\r
-#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG\r
-#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG\r
-#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT\r
-#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT\r
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS\r
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT\r
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND\r
-/* alias CMSIS for compatibilities */\r
-#define SDIO_IRQn SDMMC1_IRQn\r
-#define SDIO_IRQHandler SDMMC1_IRQHandler\r
-#endif\r
-\r
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)\r
-#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef\r
-#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef\r
-#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef\r
-#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT\r
-#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT\r
-#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE\r
-#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE\r
-#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r
-\r
-#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
-#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
-\r
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1\r
-#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2\r
-#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START\r
-#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH\r
-#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR\r
-#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE\r
-#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE\r
-#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __HAL_SPI_1LINE_TX SPI_1LINE_TX\r
-#define __HAL_SPI_1LINE_RX SPI_1LINE_RX\r
-#define __HAL_SPI_RESET_CRC SPI_RESET_CRC\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
-#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
-#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
-#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
-\r
-#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD\r
-\r
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE \r
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT\r
-#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT\r
-#define __USART_ENABLE __HAL_USART_ENABLE\r
-#define __USART_DISABLE __HAL_USART_DISABLE\r
-\r
-#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
-#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE\r
-\r
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
-#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE\r
-\r
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
-#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE\r
-\r
-#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
-\r
-#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r
-\r
-#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r
-\r
-#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup\r
-#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup\r
-\r
-#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo\r
-#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE\r
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r
-\r
-#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
-#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT\r
-\r
-#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
-\r
-#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN\r
-#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER\r
-#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER\r
-#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER\r
-#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD\r
-#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD\r
-#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION\r
-#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION\r
-#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER\r
-#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER\r
-#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE\r
-#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE\r
-\r
-#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r
-\r
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE \r
-#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE\r
-#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_LTDC_LAYER LTDC_LAYER\r
-#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE\r
-#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE\r
-#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE\r
-#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE\r
-#define SAI_STREOMODE SAI_STEREOMODE\r
-#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY\r
-#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL\r
-#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL\r
-#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL\r
-#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL\r
-#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL\r
-#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE\r
-#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1\r
-#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* ___STM32_HAL_LEGACY */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal.h\r
- * @author MCD Application Team\r
- * @brief This file contains all the functions prototypes for the HAL\r
- * module driver.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_H\r
-#define __STM32F1xx_HAL_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_conf.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup HAL\r
- * @{\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_Exported_Constants HAL Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup HAL_TICK_FREQ Tick Frequency\r
- * @{\r
- */\r
-typedef enum\r
-{\r
- HAL_TICK_FREQ_10HZ = 100U,\r
- HAL_TICK_FREQ_100HZ = 10U,\r
- HAL_TICK_FREQ_1KHZ = 1U,\r
- HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ\r
-} HAL_TickFreqTypeDef;\r
-/**\r
- * @}\r
- */\r
-/* Exported types ------------------------------------------------------------*/\r
-extern uint32_t uwTickPrio;\r
-extern HAL_TickFreqTypeDef uwTickFreq;\r
-\r
-/**\r
- * @}\r
- */\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup HAL_Exported_Macros HAL Exported Macros\r
- * @{\r
- */\r
-\r
-/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode\r
- * @brief Freeze/Unfreeze Peripherals in Debug mode\r
- * Note: On devices STM32F10xx8 and STM32F10xxB,\r
- * STM32F101xC/D/E and STM32F103xC/D/E,\r
- * STM32F101xF/G and STM32F103xF/G\r
- * STM32F10xx4 and STM32F10xx6\r
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in\r
- * debug mode (not accessible by the user software in normal mode).\r
- * Refer to errata sheet of these devices for more details.\r
- * @{\r
- */\r
-\r
-/* Peripherals on APB1 */\r
-/**\r
- * @brief TIM2 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)\r
-\r
-/**\r
- * @brief TIM3 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM4_STOP)\r
-/**\r
- * @brief TIM4 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM5_STOP)\r
-/**\r
- * @brief TIM5 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM6_STOP)\r
-/**\r
- * @brief TIM6 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM7_STOP)\r
-/**\r
- * @brief TIM7 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM12_STOP)\r
-/**\r
- * @brief TIM12 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM13_STOP)\r
-/**\r
- * @brief TIM13 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM14_STOP)\r
-/**\r
- * @brief TIM14 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)\r
-#endif\r
-\r
-/**\r
- * @brief WWDG Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)\r
-\r
-/**\r
- * @brief IWDG Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)\r
-\r
-/**\r
- * @brief I2C1 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)\r
-\r
-#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)\r
-/**\r
- * @brief I2C2 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_CAN1_STOP)\r
-/**\r
- * @brief CAN1 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_CAN2_STOP)\r
-/**\r
- * @brief CAN2 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)\r
-#endif\r
-\r
-/* Peripherals on APB2 */\r
-#if defined (DBGMCU_CR_DBG_TIM1_STOP)\r
-/**\r
- * @brief TIM1 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM8_STOP)\r
-/**\r
- * @brief TIM8 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM9_STOP)\r
-/**\r
- * @brief TIM9 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM10_STOP)\r
-/**\r
- * @brief TIM10 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM11_STOP)\r
-/**\r
- * @brief TIM11 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)\r
-#endif\r
-\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM15_STOP)\r
-/**\r
- * @brief TIM15 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM16_STOP)\r
-/**\r
- * @brief TIM16 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)\r
-#endif\r
-\r
-#if defined (DBGMCU_CR_DBG_TIM17_STOP)\r
-/**\r
- * @brief TIM17 Peripherals Debug mode\r
- */\r
-#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_Private_Macros HAL Private Macros\r
- * @{\r
- */\r
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \\r
- ((FREQ) == HAL_TICK_FREQ_100HZ) || \\r
- ((FREQ) == HAL_TICK_FREQ_1KHZ))\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup HAL_Exported_Functions\r
- * @{\r
- */\r
-/** @addtogroup HAL_Exported_Functions_Group1\r
- * @{\r
- */\r
-/* Initialization and de-initialization functions ******************************/\r
-HAL_StatusTypeDef HAL_Init(void);\r
-HAL_StatusTypeDef HAL_DeInit(void);\r
-void HAL_MspInit(void);\r
-void HAL_MspDeInit(void);\r
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup HAL_Exported_Functions_Group2\r
- * @{\r
- */\r
-/* Peripheral Control functions ************************************************/\r
-void HAL_IncTick(void);\r
-void HAL_Delay(uint32_t Delay);\r
-uint32_t HAL_GetTick(void);\r
-uint32_t HAL_GetTickPrio(void);\r
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);\r
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);\r
-void HAL_SuspendTick(void);\r
-void HAL_ResumeTick(void);\r
-uint32_t HAL_GetHalVersion(void);\r
-uint32_t HAL_GetREVID(void);\r
-uint32_t HAL_GetDEVID(void);\r
-void HAL_DBGMCU_EnableDBGSleepMode(void);\r
-void HAL_DBGMCU_DisableDBGSleepMode(void);\r
-void HAL_DBGMCU_EnableDBGStopMode(void);\r
-void HAL_DBGMCU_DisableDBGStopMode(void);\r
-void HAL_DBGMCU_EnableDBGStandbyMode(void);\r
-void HAL_DBGMCU_DisableDBGStandbyMode(void);\r
-void HAL_GetUID(uint32_t *UID);\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-/* Private types -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/** @defgroup HAL_Private_Variables HAL Private Variables\r
- * @{\r
- */\r
-/**\r
- * @}\r
- */\r
-/* Private constants ---------------------------------------------------------*/\r
-/** @defgroup HAL_Private_Constants HAL Private Constants\r
- * @{\r
- */\r
-/**\r
- * @}\r
- */\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_cortex.h\r
- * @author MCD Application Team\r
- * @brief Header file of CORTEX HAL module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_CORTEX_H\r
-#define __STM32F1xx_HAL_CORTEX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup CORTEX\r
- * @{\r
- */ \r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types\r
- * @{\r
- */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r
- * @brief MPU Region initialization structure \r
- * @{\r
- */\r
-typedef struct\r
-{\r
- uint8_t Enable; /*!< Specifies the status of the region. \r
- This parameter can be a value of @ref CORTEX_MPU_Region_Enable */\r
- uint8_t Number; /*!< Specifies the number of the region to protect. \r
- This parameter can be a value of @ref CORTEX_MPU_Region_Number */\r
- uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */\r
- uint8_t Size; /*!< Specifies the size of the region to protect. \r
- This parameter can be a value of @ref CORTEX_MPU_Region_Size */\r
- uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. \r
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ \r
- uint8_t TypeExtField; /*!< Specifies the TEX field level.\r
- This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ \r
- uint8_t AccessPermission; /*!< Specifies the region access permission type. \r
- This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */\r
- uint8_t DisableExec; /*!< Specifies the instruction access status. \r
- This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */\r
- uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. \r
- This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */\r
- uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. \r
- This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */\r
- uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. \r
- This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */\r
-}MPU_Region_InitTypeDef;\r
-/**\r
- * @}\r
- */\r
-#endif /* __MPU_PRESENT */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\r
- * @{\r
- */\r
-#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority\r
- 4 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority\r
- 3 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority\r
- 2 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority\r
- 1 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority\r
- 0 bits for subpriority */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source \r
- * @{\r
- */\r
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U\r
-#define SYSTICK_CLKSOURCE_HCLK 0x00000004U\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if (__MPU_PRESENT == 1)\r
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control\r
- * @{\r
- */\r
-#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U\r
-#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk\r
-#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk\r
-#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r
- * @{\r
- */\r
-#define MPU_REGION_ENABLE ((uint8_t)0x01)\r
-#define MPU_REGION_DISABLE ((uint8_t)0x00)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r
- * @{\r
- */\r
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)\r
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r
- * @{\r
- */\r
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)\r
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r
- * @{\r
- */\r
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)\r
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r
- * @{\r
- */\r
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)\r
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels\r
- * @{\r
- */\r
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00)\r
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01)\r
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r
- * @{\r
- */\r
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04)\r
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05)\r
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)\r
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)\r
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)\r
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)\r
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)\r
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)\r
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)\r
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)\r
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)\r
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)\r
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)\r
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)\r
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)\r
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)\r
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)\r
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)\r
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)\r
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)\r
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)\r
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)\r
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)\r
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)\r
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)\r
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)\r
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)\r
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes \r
- * @{\r
- */\r
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)\r
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)\r
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)\r
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)\r
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)\r
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r
- * @{\r
- */\r
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)\r
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)\r
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)\r
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)\r
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)\r
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05)\r
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06)\r
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07)\r
-/**\r
- * @}\r
- */\r
-#endif /* __MPU_PRESENT */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Exported Macros -----------------------------------------------------------*/\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup CORTEX_Exported_Functions\r
- * @{\r
- */\r
- \r
-/** @addtogroup CORTEX_Exported_Functions_Group1\r
- * @{\r
- */\r
-/* Initialization and de-initialization functions *****************************/\r
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r
-void HAL_NVIC_SystemReset(void);\r
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup CORTEX_Exported_Functions_Group2\r
- * @{\r
- */\r
-/* Peripheral Control functions ***********************************************/\r
-uint32_t HAL_NVIC_GetPriorityGrouping(void);\r
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r
-void HAL_SYSTICK_IRQHandler(void);\r
-void HAL_SYSTICK_Callback(void);\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-void HAL_MPU_Enable(uint32_t MPU_Control);\r
-void HAL_MPU_Disable(void);\r
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r
-#endif /* __MPU_PRESENT */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private types -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private constants ---------------------------------------------------------*/\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r
- * @{\r
- */\r
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\r
- ((GROUP) == NVIC_PRIORITYGROUP_1) || \\r
- ((GROUP) == NVIC_PRIORITYGROUP_2) || \\r
- ((GROUP) == NVIC_PRIORITYGROUP_3) || \\r
- ((GROUP) == NVIC_PRIORITYGROUP_4))\r
-\r
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)\r
-\r
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)\r
-\r
-#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)\r
-\r
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\r
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\r
- ((STATE) == MPU_REGION_DISABLE))\r
-\r
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\r
- ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r
-\r
-#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \\r
- ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r
-\r
-#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \\r
- ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r
-\r
-#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \\r
- ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r
-\r
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \\r
- ((TYPE) == MPU_TEX_LEVEL1) || \\r
- ((TYPE) == MPU_TEX_LEVEL2))\r
-\r
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \\r
- ((TYPE) == MPU_REGION_PRIV_RW) || \\r
- ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\r
- ((TYPE) == MPU_REGION_FULL_ACCESS) || \\r
- ((TYPE) == MPU_REGION_PRIV_RO) || \\r
- ((TYPE) == MPU_REGION_PRIV_RO_URO))\r
-\r
-#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \\r
- ((NUMBER) == MPU_REGION_NUMBER1) || \\r
- ((NUMBER) == MPU_REGION_NUMBER2) || \\r
- ((NUMBER) == MPU_REGION_NUMBER3) || \\r
- ((NUMBER) == MPU_REGION_NUMBER4) || \\r
- ((NUMBER) == MPU_REGION_NUMBER5) || \\r
- ((NUMBER) == MPU_REGION_NUMBER6) || \\r
- ((NUMBER) == MPU_REGION_NUMBER7))\r
-\r
-#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \\r
- ((SIZE) == MPU_REGION_SIZE_64B) || \\r
- ((SIZE) == MPU_REGION_SIZE_128B) || \\r
- ((SIZE) == MPU_REGION_SIZE_256B) || \\r
- ((SIZE) == MPU_REGION_SIZE_512B) || \\r
- ((SIZE) == MPU_REGION_SIZE_1KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_2KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_4KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_8KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_16KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_32KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_64KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_128KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_256KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_512KB) || \\r
- ((SIZE) == MPU_REGION_SIZE_1MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_2MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_4MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_8MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_16MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_32MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_64MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_128MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_256MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_512MB) || \\r
- ((SIZE) == MPU_REGION_SIZE_1GB) || \\r
- ((SIZE) == MPU_REGION_SIZE_2GB) || \\r
- ((SIZE) == MPU_REGION_SIZE_4GB))\r
-\r
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)\r
-#endif /* __MPU_PRESENT */\r
-\r
-/** \r
- * @} \r
- */\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
- \r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_CORTEX_H */\r
- \r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_def.h\r
- * @author MCD Application Team\r
- * @brief This file contains HAL common defines, enumeration, macros and\r
- * structures definitions.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_DEF\r
-#define __STM32F1xx_HAL_DEF\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx.h"\r
-#if defined(USE_HAL_LEGACY)\r
-#include "Legacy/stm32_hal_legacy.h"\r
-#endif\r
-#include <stdio.h>\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/**\r
- * @brief HAL Status structures definition\r
- */\r
-typedef enum\r
-{\r
- HAL_OK = 0x00U,\r
- HAL_ERROR = 0x01U,\r
- HAL_BUSY = 0x02U,\r
- HAL_TIMEOUT = 0x03U\r
-} HAL_StatusTypeDef;\r
-\r
-/**\r
- * @brief HAL Lock structures definition\r
- */\r
-typedef enum\r
-{\r
- HAL_UNLOCKED = 0x00U,\r
- HAL_LOCKED = 0x01U\r
-} HAL_LockTypeDef;\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-#define HAL_MAX_DELAY 0xFFFFFFFFU\r
-\r
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)\r
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)\r
-\r
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \\r
- do{ \\r
- (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\r
- (__DMA_HANDLE__).Parent = (__HANDLE__); \\r
- } while(0U)\r
-\r
-#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */\r
-\r
-/** @brief Reset the Handle's State field.\r
- * @param __HANDLE__: specifies the Peripheral Handle.\r
- * @note This macro can be used for the following purpose:\r
- * - When the Handle is declared as local variable; before passing it as parameter\r
- * to HAL_PPP_Init() for the first time, it is mandatory to use this macro\r
- * to set to 0 the Handle's "State" field.\r
- * Otherwise, "State" field may have any random value and the first time the function\r
- * HAL_PPP_Init() is called, the low level hardware initialization will be missed\r
- * (i.e. HAL_PPP_MspInit() will not be executed).\r
- * - When there is a need to reconfigure the low level hardware: instead of calling\r
- * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r
- * In this later function, when the Handle's "State" field is set to 0, it will execute the function\r
- * HAL_PPP_MspInit() which will reconfigure the low level hardware.\r
- * @retval None\r
- */\r
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\r
-\r
-#if (USE_RTOS == 1U)\r
-/* Reserved for future use */\r
-#error "USE_RTOS should be 0 in the current HAL release"\r
-#else\r
-#define __HAL_LOCK(__HANDLE__) \\r
- do{ \\r
- if((__HANDLE__)->Lock == HAL_LOCKED) \\r
- { \\r
- return HAL_BUSY; \\r
- } \\r
- else \\r
- { \\r
- (__HANDLE__)->Lock = HAL_LOCKED; \\r
- } \\r
- }while (0U)\r
-\r
-#define __HAL_UNLOCK(__HANDLE__) \\r
- do{ \\r
- (__HANDLE__)->Lock = HAL_UNLOCKED; \\r
- }while (0U)\r
-#endif /* USE_RTOS */\r
-\r
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r
-#ifndef __weak\r
-#define __weak __attribute__((weak))\r
-#endif /* __weak */\r
-#ifndef __packed\r
-#define __packed __attribute__((__packed__))\r
-#endif /* __packed */\r
-#endif /* __GNUC__ */\r
-\r
-\r
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */\r
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r
-#ifndef __ALIGN_END\r
-#define __ALIGN_END __attribute__ ((aligned (4)))\r
-#endif /* __ALIGN_END */\r
-#ifndef __ALIGN_BEGIN\r
-#define __ALIGN_BEGIN\r
-#endif /* __ALIGN_BEGIN */\r
-#else\r
-#ifndef __ALIGN_END\r
-#define __ALIGN_END\r
-#endif /* __ALIGN_END */\r
-#ifndef __ALIGN_BEGIN\r
-#if defined (__CC_ARM) /* ARM Compiler */\r
-#define __ALIGN_BEGIN __align(4)\r
-#elif defined (__ICCARM__) /* IAR Compiler */\r
-#define __ALIGN_BEGIN\r
-#endif /* __CC_ARM */\r
-#endif /* __ALIGN_BEGIN */\r
-#endif /* __GNUC__ */\r
-\r
-\r
-/**\r
- * @brief __RAM_FUNC definition\r
- */\r
-#if defined ( __CC_ARM )\r
-/* ARM Compiler\r
- ------------\r
- RAM functions are defined using the toolchain options.\r
- Functions that are executed in RAM should reside in a separate source module.\r
- Using the 'Options for File' dialog you can simply change the 'Code / Const'\r
- area of a module to a memory space in physical RAM.\r
- Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r
- dialog.\r
-*/\r
-#define __RAM_FUNC\r
-\r
-#elif defined ( __ICCARM__ )\r
-/* ICCARM Compiler\r
- ---------------\r
- RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
-*/\r
-#define __RAM_FUNC __ramfunc\r
-\r
-#elif defined ( __GNUC__ )\r
-/* GNU Compiler\r
- ------------\r
- RAM functions are defined using a specific toolchain attribute\r
- "__attribute__((section(".RamFunc")))".\r
-*/\r
-#define __RAM_FUNC __attribute__((section(".RamFunc")))\r
-\r
-#endif\r
-\r
-/**\r
- * @brief __NOINLINE definition\r
- */\r
-#if defined ( __CC_ARM ) || defined ( __GNUC__ )\r
-/* ARM & GNUCompiler\r
- ----------------\r
-*/\r
-#define __NOINLINE __attribute__ ( (noinline) )\r
-\r
-#elif defined ( __ICCARM__ )\r
-/* ICCARM Compiler\r
- ---------------\r
-*/\r
-#define __NOINLINE _Pragma("optimize = no_inline")\r
-\r
-#endif\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* ___STM32F1xx_HAL_DEF */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_dma.h\r
- * @author MCD Application Team\r
- * @brief Header file of DMA HAL module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_DMA_H\r
-#define __STM32F1xx_HAL_DMA_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DMA\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** @defgroup DMA_Exported_Types DMA Exported Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief DMA Configuration Structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, \r
- from memory to memory or from peripheral to memory.\r
- This parameter can be a value of @ref DMA_Data_transfer_direction */\r
-\r
- uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r
- This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
-\r
- uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.\r
- This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
-\r
- uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.\r
- This parameter can be a value of @ref DMA_Peripheral_data_size */\r
-\r
- uint32_t MemDataAlignment; /*!< Specifies the Memory data width.\r
- This parameter can be a value of @ref DMA_Memory_data_size */\r
-\r
- uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_mode\r
- @note The circular buffer mode cannot be used if the memory-to-memory\r
- data transfer is configured on the selected Channel */\r
-\r
- uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_Priority_level */\r
-} DMA_InitTypeDef;\r
-\r
-/**\r
- * @brief HAL DMA State structures definition\r
- */\r
-typedef enum\r
-{\r
- HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */\r
- HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */\r
- HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */\r
- HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */\r
-}HAL_DMA_StateTypeDef;\r
-\r
-/**\r
- * @brief HAL DMA Error Code structure definition\r
- */\r
-typedef enum\r
-{\r
- HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */\r
- HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */\r
-}HAL_DMA_LevelCompleteTypeDef;\r
-\r
-/** \r
- * @brief HAL DMA Callback ID structure definition\r
- */\r
-typedef enum\r
-{\r
- HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */\r
- HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */\r
- HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ \r
- HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ \r
- HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ \r
- \r
-}HAL_DMA_CallbackIDTypeDef;\r
-\r
-/** \r
- * @brief DMA handle Structure definition\r
- */\r
-typedef struct __DMA_HandleTypeDef\r
-{\r
- DMA_Channel_TypeDef *Instance; /*!< Register base address */\r
- \r
- DMA_InitTypeDef Init; /*!< DMA communication parameters */ \r
- \r
- HAL_LockTypeDef Lock; /*!< DMA locking object */ \r
- \r
- HAL_DMA_StateTypeDef State; /*!< DMA transfer state */\r
- \r
- void *Parent; /*!< Parent object state */ \r
- \r
- void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */\r
- \r
- void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */\r
- \r
- void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */\r
-\r
- void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ \r
- \r
- __IO uint32_t ErrorCode; /*!< DMA Error code */\r
-\r
- DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */\r
- \r
- uint32_t ChannelIndex; /*!< DMA Channel Index */ \r
-\r
-} DMA_HandleTypeDef; \r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA_Error_Code DMA Error Code\r
- * @{\r
- */\r
-#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */\r
-#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */\r
-#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */\r
-#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */\r
-#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
- * @{\r
- */\r
-#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */\r
-#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */\r
-#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
- * @{\r
- */\r
-#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */\r
-#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
- * @{\r
- */\r
-#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */\r
-#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
- * @{\r
- */\r
-#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */\r
-#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */\r
-#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Memory_data_size DMA Memory data size\r
- * @{\r
- */\r
-#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */\r
-#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */\r
-#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_mode DMA mode\r
- * @{\r
- */\r
-#define DMA_NORMAL 0x00000000U /*!< Normal mode */\r
-#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Priority_level DMA Priority level\r
- * @{\r
- */\r
-#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */\r
-#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */\r
-#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */\r
-#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
- * @{\r
- */\r
-#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)\r
-#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)\r
-#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_flag_definitions DMA flag definitions\r
- * @{\r
- */\r
-#define DMA_FLAG_GL1 0x00000001U\r
-#define DMA_FLAG_TC1 0x00000002U\r
-#define DMA_FLAG_HT1 0x00000004U\r
-#define DMA_FLAG_TE1 0x00000008U\r
-#define DMA_FLAG_GL2 0x00000010U\r
-#define DMA_FLAG_TC2 0x00000020U\r
-#define DMA_FLAG_HT2 0x00000040U\r
-#define DMA_FLAG_TE2 0x00000080U\r
-#define DMA_FLAG_GL3 0x00000100U\r
-#define DMA_FLAG_TC3 0x00000200U\r
-#define DMA_FLAG_HT3 0x00000400U\r
-#define DMA_FLAG_TE3 0x00000800U\r
-#define DMA_FLAG_GL4 0x00001000U\r
-#define DMA_FLAG_TC4 0x00002000U\r
-#define DMA_FLAG_HT4 0x00004000U\r
-#define DMA_FLAG_TE4 0x00008000U\r
-#define DMA_FLAG_GL5 0x00010000U\r
-#define DMA_FLAG_TC5 0x00020000U\r
-#define DMA_FLAG_HT5 0x00040000U\r
-#define DMA_FLAG_TE5 0x00080000U\r
-#define DMA_FLAG_GL6 0x00100000U\r
-#define DMA_FLAG_TC6 0x00200000U\r
-#define DMA_FLAG_HT6 0x00400000U\r
-#define DMA_FLAG_TE6 0x00800000U\r
-#define DMA_FLAG_GL7 0x01000000U\r
-#define DMA_FLAG_TC7 0x02000000U\r
-#define DMA_FLAG_HT7 0x04000000U\r
-#define DMA_FLAG_TE7 0x08000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup DMA_Exported_Macros DMA Exported Macros\r
- * @{\r
- */\r
-\r
-/** @brief Reset DMA handle state.\r
- * @param __HANDLE__: DMA handle\r
- * @retval None\r
- */\r
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
-\r
-/**\r
- * @brief Enable the specified DMA Channel.\r
- * @param __HANDLE__: DMA handle\r
- * @retval None\r
- */\r
-#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))\r
-\r
-/**\r
- * @brief Disable the specified DMA Channel.\r
- * @param __HANDLE__: DMA handle\r
- * @retval None\r
- */\r
-#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))\r
-\r
-\r
-/* Interrupt & Flag management */\r
-\r
-/**\r
- * @brief Enables the specified DMA Channel interrupts.\r
- * @param __HANDLE__: DMA handle\r
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_IT_TC: Transfer complete interrupt mask\r
- * @arg DMA_IT_HT: Half transfer complete interrupt mask\r
- * @arg DMA_IT_TE: Transfer error interrupt mask\r
- * @retval None\r
- */\r
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))\r
-\r
-/**\r
- * @brief Disable the specified DMA Channel interrupts.\r
- * @param __HANDLE__: DMA handle\r
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_IT_TC: Transfer complete interrupt mask\r
- * @arg DMA_IT_HT: Half transfer complete interrupt mask\r
- * @arg DMA_IT_TE: Transfer error interrupt mask\r
- * @retval None\r
- */\r
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))\r
-\r
-/**\r
- * @brief Check whether the specified DMA Channel interrupt is enabled or not.\r
- * @param __HANDLE__: DMA handle\r
- * @param __INTERRUPT__: specifies the DMA interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg DMA_IT_TC: Transfer complete interrupt mask\r
- * @arg DMA_IT_HT: Half transfer complete interrupt mask\r
- * @arg DMA_IT_TE: Transfer error interrupt mask\r
- * @retval The state of DMA_IT (SET or RESET).\r
- */\r
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
-\r
-/**\r
- * @brief Return the number of remaining data units in the current DMA Channel transfer.\r
- * @param __HANDLE__: DMA handle\r
- * @retval The number of remaining data units in the current DMA Channel transfer.\r
- */\r
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Include DMA HAL Extension module */\r
-#include "stm32f1xx_hal_dma_ex.h" \r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup DMA_Exported_Functions\r
- * @{\r
- */\r
-\r
-/** @addtogroup DMA_Exported_Functions_Group1\r
- * @{\r
- */\r
-/* Initialization and de-initialization functions *****************************/\r
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);\r
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup DMA_Exported_Functions_Group2\r
- * @{\r
- */\r
-/* IO operation functions *****************************************************/\r
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);\r
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));\r
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup DMA_Exported_Functions_Group3\r
- * @{\r
- */\r
-/* Peripheral State and Error functions ***************************************/\r
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup DMA_Private_Macros DMA Private Macros\r
- * @{\r
- */\r
-\r
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \\r
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))\r
-\r
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))\r
-\r
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
- ((STATE) == DMA_PINC_DISABLE))\r
-\r
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \\r
- ((STATE) == DMA_MINC_DISABLE))\r
-\r
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \\r
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
- ((SIZE) == DMA_PDATAALIGN_WORD))\r
-\r
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \\r
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
- ((SIZE) == DMA_MDATAALIGN_WORD ))\r
-\r
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \\r
- ((MODE) == DMA_CIRCULAR))\r
-\r
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \\r
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \\r
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_DMA_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_dma_ex.h\r
- * @author MCD Application Team\r
- * @brief Header file of DMA HAL extension module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_DMA_EX_H\r
-#define __STM32F1xx_HAL_DMA_EX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DMAEx DMAEx\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/ \r
-/* Exported constants --------------------------------------------------------*/\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros\r
- * @{\r
- */\r
-/* Interrupt & Flag management */\r
-#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \\r
- defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)\r
-/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Returns the current DMA Channel transfer complete flag.\r
- * @param __HANDLE__: DMA handle\r
- * @retval The specified transfer complete flag index.\r
- */\r
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\\r
- DMA_FLAG_TC5)\r
-\r
-/**\r
- * @brief Returns the current DMA Channel half transfer complete flag.\r
- * @param __HANDLE__: DMA handle\r
- * @retval The specified half transfer complete flag index.\r
- */ \r
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\\r
- DMA_FLAG_HT5)\r
-\r
-/**\r
- * @brief Returns the current DMA Channel transfer error flag.\r
- * @param __HANDLE__: DMA handle\r
- * @retval The specified transfer error flag index.\r
- */\r
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\\r
- DMA_FLAG_TE5)\r
-\r
-/**\r
- * @brief Return the current DMA Channel Global interrupt flag.\r
- * @param __HANDLE__: DMA handle\r
- * @retval The specified transfer error flag index.\r
- */\r
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\\r
- DMA_FLAG_GL5)\r
- \r
-/**\r
- * @brief Get the DMA Channel pending flags.\r
- * @param __HANDLE__: DMA handle\r
- * @param __FLAG__: Get the specified flag.\r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_FLAG_TCx: Transfer complete flag\r
- * @arg DMA_FLAG_HTx: Half transfer complete flag\r
- * @arg DMA_FLAG_TEx: Transfer error flag\r
- * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. \r
- * @retval The state of FLAG (SET or RESET).\r
- */\r
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\\r
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\\r
- (DMA1->ISR & (__FLAG__)))\r
-\r
-/**\r
- * @brief Clears the DMA Channel pending flags.\r
- * @param __HANDLE__: DMA handle\r
- * @param __FLAG__: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_FLAG_TCx: Transfer complete flag\r
- * @arg DMA_FLAG_HTx: Half transfer complete flag\r
- * @arg DMA_FLAG_TEx: Transfer error flag\r
- * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. \r
- * @retval None\r
- */\r
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \\r
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\\r
- (DMA1->IFCR = (__FLAG__)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#else\r
-/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Returns the current DMA Channel transfer complete flag.\r
- * @param __HANDLE__: DMA handle\r
- * @retval The specified transfer complete flag index.\r
- */\r
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\\r
- DMA_FLAG_TC7)\r
-\r
-/**\r
- * @brief Return the current DMA Channel half transfer complete flag.\r
- * @param __HANDLE__: DMA handle\r
- * @retval The specified half transfer complete flag index.\r
- */\r
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\\r
- DMA_FLAG_HT7)\r
-\r
-/**\r
- * @brief Return the current DMA Channel transfer error flag.\r
- * @param __HANDLE__: DMA handle\r
- * @retval The specified transfer error flag index.\r
- */\r
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\\r
- DMA_FLAG_TE7)\r
-\r
-/**\r
- * @brief Return the current DMA Channel Global interrupt flag.\r
- * @param __HANDLE__: DMA handle\r
- * @retval The specified transfer error flag index.\r
- */\r
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\\r
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\\r
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\\r
- DMA_FLAG_GL7)\r
-\r
-/**\r
- * @brief Get the DMA Channel pending flags.\r
- * @param __HANDLE__: DMA handle\r
- * @param __FLAG__: Get the specified flag.\r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_FLAG_TCx: Transfer complete flag\r
- * @arg DMA_FLAG_HTx: Half transfer complete flag\r
- * @arg DMA_FLAG_TEx: Transfer error flag\r
- * @arg DMA_FLAG_GLx: Global interrupt flag\r
- * Where x can be 1_7 to select the DMA Channel flag. \r
- * @retval The state of FLAG (SET or RESET).\r
- */\r
-\r
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))\r
-\r
-/**\r
- * @brief Clear the DMA Channel pending flags.\r
- * @param __HANDLE__: DMA handle\r
- * @param __FLAG__: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_FLAG_TCx: Transfer complete flag\r
- * @arg DMA_FLAG_HTx: Half transfer complete flag\r
- * @arg DMA_FLAG_TEx: Transfer error flag\r
- * @arg DMA_FLAG_GLx: Global interrupt flag\r
- * Where x can be 1_7 to select the DMA Channel flag. \r
- * @retval None\r
- */\r
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */\r
- /* STM32F103xG || STM32F105xC || STM32F107xC */\r
-\r
-#endif /* __STM32F1xx_HAL_DMA_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_flash.h\r
- * @author MCD Application Team\r
- * @brief Header file of Flash HAL module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ****************************************************************************** \r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_FLASH_H\r
-#define __STM32F1xx_HAL_FLASH_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
- \r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup FLASH\r
- * @{\r
- */\r
- \r
-/** @addtogroup FLASH_Private_Constants\r
- * @{\r
- */\r
-#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASH_Private_Macros\r
- * @{\r
- */\r
-\r
-#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \\r
- ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \\r
- ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) \r
-\r
-#if defined(FLASH_ACR_LATENCY)\r
-#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \\r
- ((__LATENCY__) == FLASH_LATENCY_1) || \\r
- ((__LATENCY__) == FLASH_LATENCY_2))\r
-\r
-#else\r
-#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)\r
-#endif /* FLASH_ACR_LATENCY */\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/ \r
-/** @defgroup FLASH_Exported_Types FLASH Exported Types\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief FLASH Procedure structure definition\r
- */\r
-typedef enum \r
-{\r
- FLASH_PROC_NONE = 0U, \r
- FLASH_PROC_PAGEERASE = 1U,\r
- FLASH_PROC_MASSERASE = 2U,\r
- FLASH_PROC_PROGRAMHALFWORD = 3U,\r
- FLASH_PROC_PROGRAMWORD = 4U,\r
- FLASH_PROC_PROGRAMDOUBLEWORD = 5U\r
-} FLASH_ProcedureTypeDef;\r
-\r
-/** \r
- * @brief FLASH handle Structure definition \r
- */\r
-typedef struct\r
-{\r
- __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */\r
- \r
- __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */\r
-\r
- __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */\r
-\r
- __IO uint64_t Data; /*!< Internal variable to save data to be programmed */\r
-\r
- HAL_LockTypeDef Lock; /*!< FLASH locking object */\r
-\r
- __IO uint32_t ErrorCode; /*!< FLASH error code \r
- This parameter can be a value of @ref FLASH_Error_Codes */\r
-} FLASH_ProcessTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup FLASH_Error_Codes FLASH Error Codes\r
- * @{\r
- */\r
-\r
-#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */\r
-#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */\r
-#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */\r
-#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Type_Program FLASH Type Program\r
- * @{\r
- */ \r
-#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/\r
-#define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/\r
-#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(FLASH_ACR_LATENCY)\r
-/** @defgroup FLASH_Latency FLASH Latency\r
- * @{\r
- */\r
-#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */\r
-#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */\r
-#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#else\r
-/** @defgroup FLASH_Latency FLASH Latency\r
- * @{\r
- */\r
-#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* FLASH_ACR_LATENCY */\r
-/**\r
- * @}\r
- */ \r
- \r
-/* Exported macro ------------------------------------------------------------*/\r
-\r
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
- * @brief macros to control FLASH features \r
- * @{\r
- */\r
- \r
-/** @defgroup FLASH_Half_Cycle FLASH Half Cycle\r
- * @brief macros to handle FLASH half cycle\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enable the FLASH half cycle access.\r
- * @note half cycle access can only be used with a low-frequency clock of less than\r
- 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.\r
- * @retval None\r
- */\r
-#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)\r
-\r
-/**\r
- * @brief Disable the FLASH half cycle access.\r
- * @note half cycle access can only be used with a low-frequency clock of less than\r
- 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.\r
- * @retval None\r
- */\r
-#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(FLASH_ACR_LATENCY)\r
-/** @defgroup FLASH_EM_Latency FLASH Latency\r
- * @brief macros to handle FLASH Latency\r
- * @{\r
- */ \r
- \r
-/**\r
- * @brief Set the FLASH Latency.\r
- * @param __LATENCY__ FLASH Latency \r
- * The value of this parameter depend on device used within the same series\r
- * @retval None\r
- */ \r
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))\r
-\r
-\r
-/**\r
- * @brief Get the FLASH Latency.\r
- * @retval FLASH Latency \r
- * The value of this parameter depend on device used within the same series\r
- */ \r
-#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* FLASH_ACR_LATENCY */\r
-/** @defgroup FLASH_Prefetch FLASH Prefetch\r
- * @brief macros to handle FLASH Prefetch buffer\r
- * @{\r
- */ \r
-/**\r
- * @brief Enable the FLASH prefetch buffer.\r
- * @retval None\r
- */ \r
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)\r
-\r
-/**\r
- * @brief Disable the FLASH prefetch buffer.\r
- * @retval None\r
- */\r
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/* Include FLASH HAL Extended module */\r
-#include "stm32f1xx_hal_flash_ex.h" \r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup FLASH_Exported_Functions\r
- * @{\r
- */\r
- \r
-/** @addtogroup FLASH_Exported_Functions_Group1\r
- * @{\r
- */\r
-/* IO operation functions *****************************************************/\r
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
-\r
-/* FLASH IRQ handler function */\r
-void HAL_FLASH_IRQHandler(void);\r
-/* Callbacks in non blocking modes */ \r
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASH_Exported_Functions_Group2\r
- * @{\r
- */\r
-/* Peripheral Control functions ***********************************************/\r
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);\r
-HAL_StatusTypeDef HAL_FLASH_Lock(void);\r
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);\r
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);\r
-void HAL_FLASH_OB_Launch(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASH_Exported_Functions_Group3\r
- * @{\r
- */\r
-/* Peripheral State and Error functions ***************************************/\r
-uint32_t HAL_FLASH_GetError(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private function -------------------------------------------------*/\r
-/** @addtogroup FLASH_Private_Functions\r
- * @{\r
- */\r
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
-#if defined(FLASH_BANK2_END)\r
-HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);\r
-#endif /* FLASH_BANK2_END */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_FLASH_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_flash_ex.h\r
- * @author MCD Application Team\r
- * @brief Header file of Flash HAL Extended module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_FLASH_EX_H\r
-#define __STM32F1xx_HAL_FLASH_EX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup FLASHEx\r
- * @{\r
- */ \r
-\r
-/** @addtogroup FLASHEx_Private_Constants\r
- * @{\r
- */\r
-\r
-#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U\r
-#define OBR_REG_INDEX 1U\r
-#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @addtogroup FLASHEx_Private_Macros\r
- * @{\r
- */\r
-\r
-#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))\r
-\r
-#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))\r
-\r
-#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))\r
-\r
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))\r
-\r
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) \r
-\r
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
-\r
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))\r
-\r
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))\r
-\r
-#if defined(FLASH_BANK2_END)\r
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))\r
-#endif /* FLASH_BANK2_END */\r
-\r
-/* Low Density */\r
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))\r
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \\r
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))\r
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */\r
-\r
-/* Medium Density */\r
-#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))\r
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \\r
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \\r
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \\r
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))\r
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/\r
-\r
-/* High Density */\r
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))\r
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \\r
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \\r
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))\r
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */\r
-\r
-/* XL Density */\r
-#if defined(FLASH_BANK2_END)\r
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \\r
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))\r
-#endif /* FLASH_BANK2_END */\r
-\r
-/* Connectivity Line */\r
-#if (defined(STM32F105xC) || defined(STM32F107xC))\r
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \\r
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \\r
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))\r
-\r
-#if defined(FLASH_BANK2_END)\r
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \\r
- ((BANK) == FLASH_BANK_2) || \\r
- ((BANK) == FLASH_BANK_BOTH))\r
-#else\r
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))\r
-#endif /* FLASH_BANK2_END */\r
-\r
-/* Low Density */\r
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))\r
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \\r
- ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))\r
-\r
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */\r
-\r
-/* Medium Density */\r
-#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))\r
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \\r
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \\r
- ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \\r
- ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))\r
-\r
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/\r
-\r
-/* High Density */\r
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))\r
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \\r
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \\r
- ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))\r
-\r
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */\r
-\r
-/* XL Density */\r
-#if defined(FLASH_BANK2_END)\r
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \\r
- ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))\r
-\r
-#endif /* FLASH_BANK2_END */\r
-\r
-/* Connectivity Line */\r
-#if (defined(STM32F105xC) || defined(STM32F107xC))\r
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \\r
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \\r
- ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/ \r
-/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief FLASH Erase structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.\r
- This parameter can be a value of @ref FLASHEx_Type_Erase */\r
- \r
- uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.\r
- This parameter must be a value of @ref FLASHEx_Banks */ \r
- \r
- uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled\r
- This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END \r
- (x = 1 or 2 depending on devices)*/\r
- \r
- uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.\r
- This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/\r
- \r
-} FLASH_EraseInitTypeDef;\r
-\r
-/**\r
- * @brief FLASH Options bytes program structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t OptionType; /*!< OptionType: Option byte to be configured.\r
- This parameter can be a value of @ref FLASHEx_OB_Type */\r
-\r
- uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.\r
- This parameter can be a value of @ref FLASHEx_OB_WRP_State */\r
-\r
- uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected\r
- This parameter can be a value of @ref FLASHEx_OB_Write_Protection */\r
-\r
- uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.\r
- This parameter must be a value of @ref FLASHEx_Banks */ \r
- \r
- uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..\r
- This parameter can be a value of @ref FLASHEx_OB_Read_Protection */\r
-\r
-#if defined(FLASH_BANK2_END)\r
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: \r
- IWDG / STOP / STDBY / BOOT1\r
- This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, \r
- @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */\r
-#else\r
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: \r
- IWDG / STOP / STDBY\r
- This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, \r
- @ref FLASHEx_OB_nRST_STDBY */\r
-#endif /* FLASH_BANK2_END */\r
-\r
- uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed\r
- This parameter can be a value of @ref FLASHEx_OB_Data_Address */\r
- \r
- uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA\r
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
-} FLASH_OBProgramInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup FLASHEx_Constants FLASH Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup FLASHEx_Page_Size Page Size\r
- * @{\r
- */ \r
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))\r
-#define FLASH_PAGE_SIZE 0x400U\r
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */\r
- /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */\r
-\r
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))\r
-#define FLASH_PAGE_SIZE 0x800U\r
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */\r
- /* STM32F101xG || STM32F103xG */ \r
- /* STM32F105xC || STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASHEx_Type_Erase Type Erase\r
- * @{\r
- */ \r
-#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/\r
-#define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASHEx_Banks Banks\r
- * @{\r
- */\r
-#if defined(FLASH_BANK2_END)\r
-#define FLASH_BANK_1 1U /*!< Bank 1 */\r
-#define FLASH_BANK_2 2U /*!< Bank 2 */\r
-#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */\r
-\r
-#else\r
-#define FLASH_BANK_1 1U /*!< Bank 1 */\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup FLASHEx_OB_Type Option Bytes Type\r
- * @{\r
- */\r
-#define OPTIONBYTE_WRP 0x01U /*!<WRP option byte configuration*/\r
-#define OPTIONBYTE_RDP 0x02U /*!<RDP option byte configuration*/\r
-#define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/\r
-#define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State\r
- * @{\r
- */ \r
-#define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/\r
-#define OB_WRPSTATE_ENABLE 0x01U /*!<Enable the write protection of the desired pagess*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection\r
- * @{\r
- */\r
-/* STM32 Low and Medium density devices */\r
-#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \\r
- || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \\r
- || defined(STM32F103xB)\r
-#define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */\r
-#define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */\r
-#define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */\r
-#define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */\r
-#define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */\r
-#define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */\r
-#define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */\r
-#define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */\r
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */\r
- /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */\r
- \r
-/* STM32 Medium-density devices */\r
-#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)\r
-#define OB_WRP_PAGES32TO35 0x00000100U /*!< Write protection of page 32 to 35 */\r
-#define OB_WRP_PAGES36TO39 0x00000200U /*!< Write protection of page 36 to 39 */\r
-#define OB_WRP_PAGES40TO43 0x00000400U /*!< Write protection of page 40 to 43 */\r
-#define OB_WRP_PAGES44TO47 0x00000800U /*!< Write protection of page 44 to 47 */\r
-#define OB_WRP_PAGES48TO51 0x00001000U /*!< Write protection of page 48 to 51 */\r
-#define OB_WRP_PAGES52TO55 0x00002000U /*!< Write protection of page 52 to 55 */\r
-#define OB_WRP_PAGES56TO59 0x00004000U /*!< Write protection of page 56 to 59 */\r
-#define OB_WRP_PAGES60TO63 0x00008000U /*!< Write protection of page 60 to 63 */\r
-#define OB_WRP_PAGES64TO67 0x00010000U /*!< Write protection of page 64 to 67 */\r
-#define OB_WRP_PAGES68TO71 0x00020000U /*!< Write protection of page 68 to 71 */\r
-#define OB_WRP_PAGES72TO75 0x00040000U /*!< Write protection of page 72 to 75 */\r
-#define OB_WRP_PAGES76TO79 0x00080000U /*!< Write protection of page 76 to 79 */\r
-#define OB_WRP_PAGES80TO83 0x00100000U /*!< Write protection of page 80 to 83 */\r
-#define OB_WRP_PAGES84TO87 0x00200000U /*!< Write protection of page 84 to 87 */\r
-#define OB_WRP_PAGES88TO91 0x00400000U /*!< Write protection of page 88 to 91 */\r
-#define OB_WRP_PAGES92TO95 0x00800000U /*!< Write protection of page 92 to 95 */\r
-#define OB_WRP_PAGES96TO99 0x01000000U /*!< Write protection of page 96 to 99 */\r
-#define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */\r
-#define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */\r
-#define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */\r
-#define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */\r
-#define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */\r
-#define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */\r
-#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */\r
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */\r
-\r
-\r
-/* STM32 High-density, XL-density and Connectivity line devices */\r
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \\r
- || defined(STM32F101xG) || defined(STM32F103xG) \\r
- || defined(STM32F105xC) || defined(STM32F107xC)\r
-#define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */\r
-#define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */\r
-#define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */\r
-#define OB_WRP_PAGES6TO7 0x00000008U /*!< Write protection of page 6 TO 7 */\r
-#define OB_WRP_PAGES8TO9 0x00000010U /*!< Write protection of page 8 TO 9 */\r
-#define OB_WRP_PAGES10TO11 0x00000020U /*!< Write protection of page 10 TO 11 */\r
-#define OB_WRP_PAGES12TO13 0x00000040U /*!< Write protection of page 12 TO 13 */\r
-#define OB_WRP_PAGES14TO15 0x00000080U /*!< Write protection of page 14 TO 15 */\r
-#define OB_WRP_PAGES16TO17 0x00000100U /*!< Write protection of page 16 TO 17 */\r
-#define OB_WRP_PAGES18TO19 0x00000200U /*!< Write protection of page 18 TO 19 */\r
-#define OB_WRP_PAGES20TO21 0x00000400U /*!< Write protection of page 20 TO 21 */\r
-#define OB_WRP_PAGES22TO23 0x00000800U /*!< Write protection of page 22 TO 23 */\r
-#define OB_WRP_PAGES24TO25 0x00001000U /*!< Write protection of page 24 TO 25 */\r
-#define OB_WRP_PAGES26TO27 0x00002000U /*!< Write protection of page 26 TO 27 */\r
-#define OB_WRP_PAGES28TO29 0x00004000U /*!< Write protection of page 28 TO 29 */\r
-#define OB_WRP_PAGES30TO31 0x00008000U /*!< Write protection of page 30 TO 31 */\r
-#define OB_WRP_PAGES32TO33 0x00010000U /*!< Write protection of page 32 TO 33 */\r
-#define OB_WRP_PAGES34TO35 0x00020000U /*!< Write protection of page 34 TO 35 */\r
-#define OB_WRP_PAGES36TO37 0x00040000U /*!< Write protection of page 36 TO 37 */\r
-#define OB_WRP_PAGES38TO39 0x00080000U /*!< Write protection of page 38 TO 39 */\r
-#define OB_WRP_PAGES40TO41 0x00100000U /*!< Write protection of page 40 TO 41 */\r
-#define OB_WRP_PAGES42TO43 0x00200000U /*!< Write protection of page 42 TO 43 */\r
-#define OB_WRP_PAGES44TO45 0x00400000U /*!< Write protection of page 44 TO 45 */\r
-#define OB_WRP_PAGES46TO47 0x00800000U /*!< Write protection of page 46 TO 47 */\r
-#define OB_WRP_PAGES48TO49 0x01000000U /*!< Write protection of page 48 TO 49 */\r
-#define OB_WRP_PAGES50TO51 0x02000000U /*!< Write protection of page 50 TO 51 */\r
-#define OB_WRP_PAGES52TO53 0x04000000U /*!< Write protection of page 52 TO 53 */\r
-#define OB_WRP_PAGES54TO55 0x08000000U /*!< Write protection of page 54 TO 55 */\r
-#define OB_WRP_PAGES56TO57 0x10000000U /*!< Write protection of page 56 TO 57 */\r
-#define OB_WRP_PAGES58TO59 0x20000000U /*!< Write protection of page 58 TO 59 */\r
-#define OB_WRP_PAGES60TO61 0x40000000U /*!< Write protection of page 60 TO 61 */\r
-#define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */\r
-#define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */\r
-#define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */\r
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */\r
- /* STM32F101xG || STM32F103xG */ \r
- /* STM32F105xC || STM32F107xC */\r
-\r
-#define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */\r
- \r
-/* Low Density */\r
-#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)\r
-#define OB_WRP_PAGES0TO31MASK 0x000000FFU \r
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */\r
-\r
-/* Medium Density */\r
-#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)\r
-#define OB_WRP_PAGES0TO31MASK 0x000000FFU\r
-#define OB_WRP_PAGES32TO63MASK 0x0000FF00U\r
-#define OB_WRP_PAGES64TO95MASK 0x00FF0000U\r
-#define OB_WRP_PAGES96TO127MASK 0xFF000000U\r
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/\r
- \r
-/* High Density */\r
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \r
-#define OB_WRP_PAGES0TO15MASK 0x000000FFU\r
-#define OB_WRP_PAGES16TO31MASK 0x0000FF00U\r
-#define OB_WRP_PAGES32TO47MASK 0x00FF0000U\r
-#define OB_WRP_PAGES48TO255MASK 0xFF000000U\r
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */\r
-\r
-/* XL Density */\r
-#if defined(STM32F101xG) || defined(STM32F103xG) \r
-#define OB_WRP_PAGES0TO15MASK 0x000000FFU\r
-#define OB_WRP_PAGES16TO31MASK 0x0000FF00U\r
-#define OB_WRP_PAGES32TO47MASK 0x00FF0000U\r
-#define OB_WRP_PAGES48TO511MASK 0xFF000000U\r
-#endif /* STM32F101xG || STM32F103xG */\r
- \r
-/* Connectivity line devices */\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define OB_WRP_PAGES0TO15MASK 0x000000FFU\r
-#define OB_WRP_PAGES16TO31MASK 0x0000FF00U\r
-#define OB_WRP_PAGES32TO47MASK 0x00FF0000U\r
-#define OB_WRP_PAGES48TO127MASK 0xFF000000U\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection\r
- * @{\r
- */\r
-#define OB_RDP_LEVEL_0 ((uint8_t)0xA5)\r
-#define OB_RDP_LEVEL_1 ((uint8_t)0x00)\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog\r
- * @{\r
- */ \r
-#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */\r
-#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP\r
- * @{\r
- */ \r
-#define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */\r
-#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY\r
- * @{\r
- */ \r
-#define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */\r
-#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(FLASH_BANK2_END)\r
-/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1\r
- * @{\r
- */\r
-#define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */\r
-#define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */\r
-/**\r
- * @}\r
- */\r
-#endif /* FLASH_BANK2_END */\r
-\r
-/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address\r
- * @{\r
- */\r
-#define OB_DATA_ADDRESS_DATA0 0x1FFFF804U\r
-#define OB_DATA_ADDRESS_DATA1 0x1FFFF806U\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASHEx_Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup FLASH_Flag_definition Flag definition\r
- * @brief Flag definition\r
- * @{\r
- */\r
-#if defined(FLASH_BANK2_END)\r
- #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */ \r
- #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */\r
- #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */\r
- #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */\r
-\r
- #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */ \r
- #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */\r
- #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */\r
- #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */\r
- \r
- #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */ \r
- #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */\r
- #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */\r
- #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */\r
-\r
-#else \r
-\r
- #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ \r
- #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */\r
- #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */\r
- #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */\r
-\r
-#endif\r
- #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FLASH_Interrupt_definition Interrupt definition\r
- * @brief FLASH Interrupt definition\r
- * @{\r
- */\r
-#if defined(FLASH_BANK2_END)\r
- #define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */\r
- #define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */\r
-\r
- #define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */\r
- #define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */\r
-\r
- #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */\r
- #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */\r
-\r
-#else\r
-\r
- #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */\r
- #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */\r
-\r
-#endif\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
- \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros\r
- * @{\r
- */\r
-\r
-/** @defgroup FLASH_Interrupt Interrupt\r
- * @brief macros to handle FLASH interrupts\r
- * @{\r
- */ \r
-\r
-#if defined(FLASH_BANK2_END)\r
-/**\r
- * @brief Enable the specified FLASH interrupt.\r
- * @param __INTERRUPT__ FLASH interrupt \r
- * This parameter can be any combination of the following values:\r
- * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1\r
- * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1\r
- * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2\r
- * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2\r
- * @retval none\r
- */ \r
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \\r
- /* Enable Bank1 IT */ \\r
- SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \\r
- /* Enable Bank2 IT */ \\r
- SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \\r
- } while(0U)\r
-\r
-/**\r
- * @brief Disable the specified FLASH interrupt.\r
- * @param __INTERRUPT__ FLASH interrupt \r
- * This parameter can be any combination of the following values:\r
- * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1\r
- * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1\r
- * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2\r
- * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2\r
- * @retval none\r
- */ \r
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \\r
- /* Disable Bank1 IT */ \\r
- CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \\r
- /* Disable Bank2 IT */ \\r
- CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \\r
- } while(0U)\r
-\r
-/**\r
- * @brief Get the specified FLASH flag status. \r
- * @param __FLAG__ specifies the FLASH flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1\r
- * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1\r
- * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1\r
- * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1\r
- * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2\r
- * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2\r
- * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2\r
- * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2\r
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match\r
- * @retval The new state of __FLAG__ (SET or RESET).\r
- */\r
-#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \\r
- (FLASH->OBR & FLASH_OBR_OPTERR) : \\r
- ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \\r
- (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \\r
- (FLASH->SR2 & ((__FLAG__) >> 16U))))\r
-\r
-/**\r
- * @brief Clear the specified FLASH flag.\r
- * @param __FLAG__ specifies the FLASH flags to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1\r
- * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1\r
- * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1\r
- * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1\r
- * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2\r
- * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2\r
- * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2\r
- * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2\r
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match\r
- * @retval none\r
- */\r
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \\r
- /* Clear FLASH_FLAG_OPTVERR flag */ \\r
- if ((__FLAG__) == FLASH_FLAG_OPTVERR) \\r
- { \\r
- CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \\r
- } \\r
- else { \\r
- /* Clear Flag in Bank1 */ \\r
- if (((__FLAG__) & SR_FLAG_MASK) != RESET) \\r
- { \\r
- FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \\r
- } \\r
- /* Clear Flag in Bank2 */ \\r
- if (((__FLAG__) >> 16U) != RESET) \\r
- { \\r
- FLASH->SR2 = ((__FLAG__) >> 16U); \\r
- } \\r
- } \\r
- } while(0U)\r
-#else\r
-/**\r
- * @brief Enable the specified FLASH interrupt.\r
- * @param __INTERRUPT__ FLASH interrupt \r
- * This parameter can be any combination of the following values:\r
- * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt\r
- * @arg @ref FLASH_IT_ERR Error Interrupt \r
- * @retval none\r
- */ \r
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))\r
-\r
-/**\r
- * @brief Disable the specified FLASH interrupt.\r
- * @param __INTERRUPT__ FLASH interrupt \r
- * This parameter can be any combination of the following values:\r
- * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt\r
- * @arg @ref FLASH_IT_ERR Error Interrupt \r
- * @retval none\r
- */ \r
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))\r
-\r
-/**\r
- * @brief Get the specified FLASH flag status. \r
- * @param __FLAG__ specifies the FLASH flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag \r
- * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag \r
- * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag\r
- * @arg @ref FLASH_FLAG_BSY FLASH Busy flag\r
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match\r
- * @retval The new state of __FLAG__ (SET or RESET).\r
- */\r
-#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \\r
- (FLASH->OBR & FLASH_OBR_OPTERR) : \\r
- (FLASH->SR & (__FLAG__)))\r
-/**\r
- * @brief Clear the specified FLASH flag.\r
- * @param __FLAG__ specifies the FLASH flags to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag \r
- * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag \r
- * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag \r
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match\r
- * @retval none\r
- */\r
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \\r
- /* Clear FLASH_FLAG_OPTVERR flag */ \\r
- if ((__FLAG__) == FLASH_FLAG_OPTVERR) \\r
- { \\r
- CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \\r
- } \\r
- else { \\r
- /* Clear Flag in Bank1 */ \\r
- FLASH->SR = (__FLAG__); \\r
- } \\r
- } while(0U)\r
-\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup FLASHEx_Exported_Functions\r
- * @{\r
- */\r
-\r
-/** @addtogroup FLASHEx_Exported_Functions_Group1\r
- * @{\r
- */\r
-/* IO operation functions *****************************************************/\r
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);\r
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASHEx_Exported_Functions_Group2\r
- * @{\r
- */\r
-/* Peripheral Control functions ***********************************************/\r
-HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);\r
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r
-uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_FLASH_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_gpio.h\r
- * @author MCD Application Team\r
- * @brief Header file of GPIO HAL module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_GPIO_H\r
-#define __STM32F1xx_HAL_GPIO_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup GPIO\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup GPIO_Exported_Types GPIO Exported Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief GPIO Init structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.\r
- This parameter can be any value of @ref GPIO_pins_define */\r
-\r
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.\r
- This parameter can be a value of @ref GPIO_mode_define */\r
-\r
- uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r
- This parameter can be a value of @ref GPIO_pull_define */\r
-\r
- uint32_t Speed; /*!< Specifies the speed for the selected pins.\r
- This parameter can be a value of @ref GPIO_speed_define */\r
-} GPIO_InitTypeDef;\r
-\r
-/**\r
- * @brief GPIO Bit SET and Bit RESET enumeration\r
- */\r
-typedef enum\r
-{\r
- GPIO_PIN_RESET = 0U,\r
- GPIO_PIN_SET\r
-} GPIO_PinState;\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIO_pins_define GPIO pins define\r
- * @{\r
- */\r
-#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */\r
-#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */\r
-#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */\r
-#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */\r
-#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */\r
-#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */\r
-#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */\r
-#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */\r
-#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */\r
-#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */\r
-#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */\r
-#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */\r
-#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */\r
-#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */\r
-#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */\r
-#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */\r
-#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */\r
-\r
-#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_mode_define GPIO mode define\r
- * @brief GPIO Configuration Mode\r
- * Elements values convention: 0xX0yz00YZ\r
- * - X : GPIO mode or EXTI Mode\r
- * - y : External IT or Event trigger detection\r
- * - z : IO configuration on External IT or Event\r
- * - Y : Output type (Push Pull or Open Drain)\r
- * - Z : IO Direction mode (Input, Output, Alternate or Analog)\r
- * @{\r
- */\r
-#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */\r
-#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */\r
-#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */\r
-#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */\r
-#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */\r
-#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */\r
-\r
-#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */\r
-\r
-#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */\r
-#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */\r
-#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
-\r
-#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */\r
-#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */\r
-#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_speed_define GPIO speed define\r
- * @brief GPIO Output Maximum frequency\r
- * @{\r
- */\r
-#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */\r
-#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */\r
-#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_pull_define GPIO pull define\r
- * @brief GPIO Pull-Up or Pull-Down Activation\r
- * @{\r
- */\r
-#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */\r
-#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */\r
-#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified EXTI line flag is set or not.\r
- * @param __EXTI_LINE__: specifies the EXTI line flag to check.\r
- * This parameter can be GPIO_PIN_x where x can be(0..15)\r
- * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
- */\r
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
-\r
-/**\r
- * @brief Clears the EXTI's line pending flags.\r
- * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.\r
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
- * @retval None\r
- */\r
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
-\r
-/**\r
- * @brief Checks whether the specified EXTI line is asserted or not.\r
- * @param __EXTI_LINE__: specifies the EXTI line to check.\r
- * This parameter can be GPIO_PIN_x where x can be(0..15)\r
- * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
- */\r
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
-\r
-/**\r
- * @brief Clears the EXTI's line pending bits.\r
- * @param __EXTI_LINE__: specifies the EXTI lines to clear.\r
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
- * @retval None\r
- */\r
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
-\r
-/**\r
- * @brief Generates a Software interrupt on selected EXTI line.\r
- * @param __EXTI_LINE__: specifies the EXTI line to check.\r
- * This parameter can be GPIO_PIN_x where x can be(0..15)\r
- * @retval None\r
- */\r
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))\r
-/**\r
- * @}\r
- */\r
-\r
-/* Include GPIO HAL Extension module */\r
-#include "stm32f1xx_hal_gpio_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup GPIO_Exported_Functions\r
- * @{\r
- */\r
-\r
-/** @addtogroup GPIO_Exported_Functions_Group1\r
- * @{\r
- */\r
-/* Initialization and de-initialization functions *****************************/\r
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup GPIO_Exported_Functions_Group2\r
- * @{\r
- */\r
-/* IO operation functions *****************************************************/\r
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);\r
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);\r
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);\r
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-/* Private types -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private constants ---------------------------------------------------------*/\r
-/** @defgroup GPIO_Private_Constants GPIO Private Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup GPIO_Private_Macros GPIO Private Macros\r
- * @{\r
- */\r
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r
-#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))\r
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\\r
- ((MODE) == GPIO_MODE_OUTPUT_PP) ||\\r
- ((MODE) == GPIO_MODE_OUTPUT_OD) ||\\r
- ((MODE) == GPIO_MODE_AF_PP) ||\\r
- ((MODE) == GPIO_MODE_AF_OD) ||\\r
- ((MODE) == GPIO_MODE_IT_RISING) ||\\r
- ((MODE) == GPIO_MODE_IT_FALLING) ||\\r
- ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\\r
- ((MODE) == GPIO_MODE_EVT_RISING) ||\\r
- ((MODE) == GPIO_MODE_EVT_FALLING) ||\\r
- ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\\r
- ((MODE) == GPIO_MODE_ANALOG))\r
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \\r
- ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))\r
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \\r
- ((PULL) == GPIO_PULLDOWN))\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-/** @defgroup GPIO_Private_Functions GPIO Private Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_GPIO_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_gpio_ex.h\r
- * @author MCD Application Team\r
- * @brief Header file of GPIO HAL Extension module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_GPIO_EX_H\r
-#define __STM32F1xx_HAL_GPIO_EX_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIOEx GPIOEx\r
- * @{\r
- */\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration\r
- * @brief This section propose definition to use the Cortex EVENTOUT signal.\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin\r
- * @{\r
- */\r
-\r
-#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */\r
-#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */\r
-#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */\r
-#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */\r
-#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */\r
-#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */\r
-#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */\r
-#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */\r
-#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */\r
-#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */\r
-#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */\r
-#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */\r
-#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */\r
-#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */\r
-#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */\r
-#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */\r
-\r
-#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \\r
- ((__PIN__) == AFIO_EVENTOUT_PIN_15))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port\r
- * @{\r
- */\r
-\r
-#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */\r
-#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */\r
-#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */\r
-#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */\r
-#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */\r
-\r
-#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \\r
- ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \\r
- ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \\r
- ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \\r
- ((__PORT__) == AFIO_EVENTOUT_PORT_E))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping\r
- * @brief This section propose definition to remap the alternate function to some other port/pins.\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.\r
- * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.\r
- * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of I2C1 alternate function SCL and SDA.\r
- * @note ENABLE: Remap (SCL/PB8, SDA/PB9)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of I2C1 alternate function SCL and SDA.\r
- * @note DISABLE: No remap (SCL/PB6, SDA/PB7)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of USART1 alternate function TX and RX.\r
- * @note ENABLE: Remap (TX/PB6, RX/PB7)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of USART1 alternate function TX and RX.\r
- * @note DISABLE: No remap (TX/PA9, RX/PA10)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.\r
- * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.\r
- * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.\r
- * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.\r
- * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.\r
- * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)\r
- * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)\r
- * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)\r
- * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)\r
- * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)\r
- * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)\r
- * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)\r
- * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4\r
- * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)\r
- * @note TIM3_ETR on PE0 is not re-mapped.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4\r
- * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)\r
- * @note TIM3_ETR on PE0 is not re-mapped.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM3 alternate function channels 1 to 4\r
- * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)\r
- * @note TIM3_ETR on PE0 is not re-mapped.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.\r
- * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)\r
- * @note TIM4_ETR on PE0 is not re-mapped.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.\r
- * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)\r
- * @note TIM4_ETR on PE0 is not re-mapped.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)\r
-\r
-#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)\r
-\r
-/**\r
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.\r
- * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)\r
-\r
-/**\r
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.\r
- * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)\r
-\r
-/**\r
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.\r
- * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)\r
-\r
-#endif\r
-\r
-/**\r
- * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used\r
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and\r
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available\r
- * on 100-pin and 144-pin packages, no need for remapping).\r
- * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used\r
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and\r
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available\r
- * on 100-pin and 144-pin packages, no need for remapping).\r
- * @note DISABLE: No remapping of PD0 and PD1\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)\r
-\r
-#if defined(AFIO_MAPR_TIM5CH4_IREMAP)\r
-/**\r
- * @brief Enable the remapping of TIM5CH4.\r
- * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.\r
- * @note This function is available only in high density value line devices.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM5CH4.\r
- * @note DISABLE: TIM5_CH4 is connected to PA3\r
- * @note This function is available only in high density value line devices.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR_ETH_REMAP)\r
-/**\r
- * @brief Enable the remapping of Ethernet MAC connections with the PHY.\r
- * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of Ethernet MAC connections with the PHY.\r
- * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR_CAN2_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.\r
- * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.\r
- * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR_MII_RMII_SEL)\r
-/**\r
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.\r
- * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)\r
-\r
-/**\r
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.\r
- * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)\r
-#endif\r
-\r
-/**\r
- * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).\r
- * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).\r
- * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).\r
- * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).\r
- * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)\r
-\r
-#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).\r
- * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).\r
- * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)\r
-#endif\r
-\r
-#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).\r
- * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).\r
- * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)\r
-#endif\r
-\r
-/**\r
- * @brief Enable the Serial wire JTAG configuration\r
- * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)\r
-\r
-/**\r
- * @brief Enable the Serial wire JTAG configuration\r
- * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)\r
-\r
-/**\r
- * @brief Enable the Serial wire JTAG configuration\r
- * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled\r
- * @retval None\r
- */\r
-\r
-#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)\r
-\r
-/**\r
- * @brief Disable the Serial wire JTAG configuration\r
- * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)\r
-\r
-#if defined(AFIO_MAPR_SPI3_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.\r
- * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.\r
- * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)\r
-\r
-/**\r
- * @brief Control of TIM2_ITR1 internal mapping.\r
- * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)\r
-\r
-/**\r
- * @brief Control of TIM2_ITR1 internal mapping.\r
- * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR_PTP_PPS_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).\r
- * @note ENABLE: PTP_PPS is output on PB5 pin.\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).\r
- * @note DISABLE: PTP_PPS not output on PB5 pin.\r
- * @note This bit is available only in connectivity line devices and is reserved otherwise.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM9_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.\r
- * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.\r
- * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM10_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM10_CH1.\r
- * @note ENABLE: Remap (TIM10_CH1 on PF6).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM10_CH1.\r
- * @note DISABLE: No remap (TIM10_CH1 on PB8).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM11_REMAP)\r
-/**\r
- * @brief Enable the remapping of TIM11_CH1.\r
- * @note ENABLE: Remap (TIM11_CH1 on PF7).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM11_CH1.\r
- * @note DISABLE: No remap (TIM11_CH1 on PB9).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM13_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM13_CH1.\r
- * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM13_CH1.\r
- * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM14_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM14_CH1.\r
- * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM14_CH1.\r
- * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)\r
-\r
-/**\r
- * @brief Controls the use of the optional FSMC_NADV signal.\r
- * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)\r
-\r
-/**\r
- * @brief Controls the use of the optional FSMC_NADV signal.\r
- * @note CONNECTED: The NADV signal is connected to the output (default).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM15_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.\r
- * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.\r
- * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM16_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM16_CH1.\r
- * @note ENABLE: Remap (TIM16_CH1 on PA6).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM16_CH1.\r
- * @note DISABLE: No remap (TIM16_CH1 on PB8).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM17_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM17_CH1.\r
- * @note ENABLE: Remap (TIM17_CH1 on PA7).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM17_CH1.\r
- * @note DISABLE: No remap (TIM17_CH1 on PB9).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_CEC_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of CEC.\r
- * @note ENABLE: Remap (CEC on PB10).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of CEC.\r
- * @note DISABLE: No remap (CEC on PB8).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)\r
-\r
-/**\r
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.\r
- * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)\r
-\r
-/**\r
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.\r
- * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)\r
-\r
-/**\r
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.\r
- * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)\r
-\r
-/**\r
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.\r
- * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_TIM12_REMAP)\r
-\r
-/**\r
- * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.\r
- * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).\r
- * @note This bit is available only in high density value line devices.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)\r
-\r
-/**\r
- * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.\r
- * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).\r
- * @note This bit is available only in high density value line devices.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)\r
-#endif\r
-\r
-#if defined(AFIO_MAPR2_MISC_REMAP)\r
-\r
-/**\r
- * @brief Miscellaneous features remapping.\r
- * This bit is set and cleared by software. It controls miscellaneous features.\r
- * The DMA2 channel 5 interrupt position in the vector table.\r
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).\r
- * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is\r
- * selected as DAC Trigger 3, TIM15 triggers TIM1/3.\r
- * @note This bit is available only in high density value line devices.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)\r
-\r
-/**\r
- * @brief Miscellaneous features remapping.\r
- * This bit is set and cleared by software. It controls miscellaneous features.\r
- * The DMA2 channel 5 interrupt position in the vector table.\r
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).\r
- * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO\r
- * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.\r
- * @note This bit is available only in high density value line devices.\r
- * @retval None\r
- */\r
-#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros\r
- * @{\r
- */\r
-#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\r
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\\r
- ((__GPIOx__) == (GPIOB))? 1U :\\r
- ((__GPIOx__) == (GPIOC))? 2U :3U)\r
-#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)\r
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\\r
- ((__GPIOx__) == (GPIOB))? 1U :\\r
- ((__GPIOx__) == (GPIOC))? 2U :\\r
- ((__GPIOx__) == (GPIOD))? 3U :4U)\r
-#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\r
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\\r
- ((__GPIOx__) == (GPIOB))? 1U :\\r
- ((__GPIOx__) == (GPIOC))? 2U :\\r
- ((__GPIOx__) == (GPIOD))? 3U :\\r
- ((__GPIOx__) == (GPIOE))? 4U :\\r
- ((__GPIOx__) == (GPIOF))? 5U :6U)\r
-#endif\r
-\r
-#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \\r
- tmpreg |= AFIO_MAPR_SWJ_CFG; \\r
- tmpreg |= REMAP_PIN; \\r
- AFIO->MAPR = tmpreg; \\r
- }while(0U)\r
-\r
-#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \\r
- tmpreg |= AFIO_MAPR_SWJ_CFG; \\r
- tmpreg &= ~REMAP_PIN; \\r
- AFIO->MAPR = tmpreg; \\r
- }while(0U)\r
-\r
-#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \\r
- tmpreg &= ~REMAP_PIN_MASK; \\r
- tmpreg |= AFIO_MAPR_SWJ_CFG; \\r
- tmpreg |= REMAP_PIN; \\r
- AFIO->MAPR = tmpreg; \\r
- }while(0U)\r
-\r
-#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \\r
- tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \\r
- tmpreg |= DBGAFR_SWJCFG; \\r
- AFIO->MAPR = tmpreg; \\r
- }while(0U)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @addtogroup GPIOEx_Exported_Functions\r
- * @{\r
- */\r
-\r
-/** @addtogroup GPIOEx_Exported_Functions_Group1\r
- * @{\r
- */\r
-void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);\r
-void HAL_GPIOEx_EnableEventout(void);\r
-void HAL_GPIOEx_DisableEventout(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_GPIO_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_pwr.h\r
- * @author MCD Application Team\r
- * @brief Header file of PWR HAL module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_PWR_H\r
-#define __STM32F1xx_HAL_PWR_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup PWR\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Exported_Types PWR Exported Types\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief PWR PVD configuration structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.\r
- This parameter can be a value of @ref PWR_PVD_detection_level */\r
-\r
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.\r
- This parameter can be a value of @ref PWR_PVD_Mode */\r
-}PWR_PVDTypeDef;\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Internal constants --------------------------------------------------------*/\r
-\r
-/** @addtogroup PWR_Private_Constants\r
- * @{\r
- */ \r
-\r
-#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Exported_Constants PWR Exported Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level\r
- * @{\r
- */\r
-#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2\r
-#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3\r
-#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4\r
-#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5\r
-#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6\r
-#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7\r
-#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8\r
-#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 \r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_PVD_Mode PWR PVD Mode\r
- * @{\r
- */\r
-#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */\r
-#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */\r
-#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */\r
-#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
-#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */\r
-#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */\r
-#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins\r
- * @{\r
- */\r
-\r
-#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode\r
- * @{\r
- */\r
-#define PWR_MAINREGULATOR_ON 0x00000000U\r
-#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry\r
- * @{\r
- */\r
-#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)\r
-#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry\r
- * @{\r
- */\r
-#define PWR_STOPENTRY_WFI ((uint8_t)0x01)\r
-#define PWR_STOPENTRY_WFE ((uint8_t)0x02)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Flag PWR Flag\r
- * @{\r
- */\r
-#define PWR_FLAG_WU PWR_CSR_WUF\r
-#define PWR_FLAG_SB PWR_CSR_SBF\r
-#define PWR_FLAG_PVDO PWR_CSR_PVDO\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup PWR_Exported_Macros PWR Exported Macros\r
- * @{\r
- */\r
-\r
-/** @brief Check PWR flag is set or not.\r
- * @param __FLAG__: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event\r
- * was received from the WKUP pin or from the RTC alarm\r
- * An additional wakeup event is detected if the WKUP pin is enabled\r
- * (by setting the EWUP bit) when the WKUP pin level is already high.\r
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
- * resumed from StandBy mode.\r
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled\r
- * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode\r
- * For this reason, this bit is equal to 0 after Standby or reset\r
- * until the PVDE bit is set.\r
- * @retval The new state of __FLAG__ (TRUE or FALSE).\r
- */\r
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))\r
-\r
-/** @brief Clear the PWR's pending flags.\r
- * @param __FLAG__: specifies the flag to clear.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag\r
- * @arg PWR_FLAG_SB: StandBy flag\r
- */\r
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))\r
-\r
-/**\r
- * @brief Enable interrupt on PVD Exti Line 16.\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
- * @brief Disable interrupt on PVD Exti Line 16. \r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
- * @brief Enable event on PVD Exti Line 16.\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
- * @brief Disable event on PVD Exti Line 16.\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)\r
-\r
-\r
-/**\r
- * @brief PVD EXTI line configuration: set falling edge trigger. \r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
-\r
-\r
-/**\r
- * @brief Disable the PVD Extended Interrupt Falling Trigger.\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
-\r
-\r
-/**\r
- * @brief PVD EXTI line configuration: set rising edge trigger.\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
- * @brief Disable the PVD Extended Interrupt Rising Trigger.\r
- * This parameter can be:\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
-\r
-/**\r
- * @brief PVD EXTI line configuration: set rising & falling edge trigger.\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
-\r
-/**\r
- * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r
- * This parameter can be:\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r
-\r
-\r
-\r
-/**\r
- * @brief Check whether the specified PVD EXTI interrupt flag is set or not.\r
- * @retval EXTI PVD Line Status.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))\r
-\r
-/**\r
- * @brief Clear the PVD EXTI flag.\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))\r
-\r
-/**\r
- * @brief Generate a Software interrupt on selected EXTI line.\r
- * @retval None.\r
- */\r
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/** @defgroup PWR_Private_Macros PWR Private Macros\r
- * @{\r
- */\r
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\r
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\r
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\r
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r
-\r
-\r
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \\r
- ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \\r
- ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \\r
- ((MODE) == PWR_PVD_MODE_NORMAL)) \r
-\r
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))\r
-\r
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\r
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r
-\r
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r
-\r
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r
- * @{\r
- */\r
- \r
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r
- * @{\r
- */\r
-\r
-/* Initialization and de-initialization functions *******************************/\r
-void HAL_PWR_DeInit(void);\r
-void HAL_PWR_EnableBkUpAccess(void);\r
-void HAL_PWR_DisableBkUpAccess(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions \r
- * @{\r
- */\r
-\r
-/* Peripheral Control functions ************************************************/\r
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r
-/* #define HAL_PWR_ConfigPVD 12*/\r
-void HAL_PWR_EnablePVD(void);\r
-void HAL_PWR_DisablePVD(void);\r
-\r
-/* WakeUp pins configuration functions ****************************************/\r
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);\r
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r
-\r
-/* Low Power modes configuration functions ************************************/\r
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r
-void HAL_PWR_EnterSTANDBYMode(void);\r
-\r
-void HAL_PWR_EnableSleepOnExit(void);\r
-void HAL_PWR_DisableSleepOnExit(void);\r
-void HAL_PWR_EnableSEVOnPend(void);\r
-void HAL_PWR_DisableSEVOnPend(void);\r
-\r
-\r
-\r
-void HAL_PWR_PVD_IRQHandler(void);\r
-void HAL_PWR_PVDCallback(void);\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* __STM32F1xx_HAL_PWR_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_rcc.h\r
- * @author MCD Application Team\r
- * @brief Header file of RCC HAL module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_RCC_H\r
-#define __STM32F1xx_HAL_RCC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup RCC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Exported_Types RCC Exported Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief RCC PLL configuration structure definition \r
- */\r
-typedef struct\r
-{\r
- uint32_t PLLState; /*!< PLLState: The new state of the PLL.\r
- This parameter can be a value of @ref RCC_PLL_Config */\r
-\r
- uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.\r
- This parameter must be a value of @ref RCC_PLL_Clock_Source */ \r
-\r
- uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock\r
- This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */\r
-} RCC_PLLInitTypeDef;\r
- \r
-/**\r
- * @brief RCC System, AHB and APB busses clock configuration structure definition \r
- */\r
-typedef struct\r
-{\r
- uint32_t ClockType; /*!< The clock to be configured.\r
- This parameter can be a value of @ref RCC_System_Clock_Type */\r
-\r
- uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.\r
- This parameter can be a value of @ref RCC_System_Clock_Source */\r
-\r
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r
- This parameter can be a value of @ref RCC_AHB_Clock_Source */\r
-\r
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
-\r
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
-} RCC_ClkInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup RCC_Exported_Constants RCC Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r
- * @{\r
- */\r
-\r
-#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
-#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Oscillator_Type Oscillator Type\r
- * @{\r
- */\r
-#define RCC_OSCILLATORTYPE_NONE 0x00000000U\r
-#define RCC_OSCILLATORTYPE_HSE 0x00000001U\r
-#define RCC_OSCILLATORTYPE_HSI 0x00000002U\r
-#define RCC_OSCILLATORTYPE_LSE 0x00000004U\r
-#define RCC_OSCILLATORTYPE_LSI 0x00000008U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_HSE_Config HSE Config\r
- * @{\r
- */\r
-#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */\r
-#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */\r
-#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_LSE_Config LSE Config\r
- * @{\r
- */\r
-#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */\r
-#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */\r
-#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_HSI_Config HSI Config\r
- * @{\r
- */\r
-#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */\r
-#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */\r
-\r
-#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_LSI_Config LSI Config\r
- * @{\r
- */\r
-#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */\r
-#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_PLL_Config PLL Config\r
- * @{\r
- */\r
-#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */\r
-#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */\r
-#define RCC_PLL_ON 0x00000002U /*!< PLL activation */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_System_Clock_Type System Clock Type\r
- * @{\r
- */\r
-#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */\r
-#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */\r
-#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */\r
-#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_System_Clock_Source System Clock Source\r
- * @{\r
- */\r
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */\r
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */\r
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r
- * @{\r
- */\r
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */\r
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */\r
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source\r
- * @{\r
- */\r
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */\r
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */\r
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */\r
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */\r
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */\r
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */\r
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */\r
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */\r
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source\r
- * @{\r
- */\r
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */\r
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */\r
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */\r
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */\r
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source\r
- * @{\r
- */\r
-#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */\r
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */\r
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */\r
-#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup RCC_MCO_Index MCO Index\r
- * @{\r
- */\r
-#define RCC_MCO1 0x00000000U\r
-#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler\r
- * @{\r
- */\r
-#define RCC_MCODIV_1 0x00000000U\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Interrupt Interrupts\r
- * @{\r
- */\r
-#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */\r
-#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */\r
-#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */\r
-#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */\r
-#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */\r
-#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup RCC_Flag Flags\r
- * Elements values convention: XXXYYYYYb\r
- * - YYYYY : Flag position in the register\r
- * - XXX : Register index\r
- * - 001: CR register\r
- * - 010: BDCR register\r
- * - 011: CSR register\r
- * @{\r
- */\r
-/* Flags in the CR register */\r
-#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */\r
-#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */\r
-#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */\r
-\r
-/* Flags in the CSR register */\r
-#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */\r
-#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */\r
-#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */\r
-#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */\r
-#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */\r
-#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */\r
-#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */\r
-\r
-/* Flags in the BDCR register */\r
-#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Exported_Macros RCC Exported Macros\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable\r
- * @brief Enable or disable the AHB1 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it. \r
- * @{\r
- */\r
-#define __HAL_RCC_DMA1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_SRAM_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_FLITF_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_CRC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))\r
-#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))\r
-#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))\r
-#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status\r
- * @brief Get the enable or disable status of the AHB peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)\r
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)\r
-#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)\r
-#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)\r
-#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)\r
-#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)\r
-#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)\r
-#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable\r
- * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it. \r
- * @{ \r
- */\r
-#define __HAL_RCC_TIM2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_WWDG_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_USART2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_I2C1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_BKP_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_PWR_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\r
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\r
-#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))\r
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))\r
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))\r
-\r
-#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))\r
-#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\r
- * @brief Get the enable or disable status of the APB1 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)\r
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)\r
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)\r
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)\r
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)\r
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)\r
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)\r
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)\r
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)\r
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)\r
-#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)\r
-#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)\r
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)\r
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable\r
- * @brief Enable or disable the High Speed APB (APB2) peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it.\r
- * @{ \r
- */\r
-#define __HAL_RCC_AFIO_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_ADC1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_USART1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
- /* Delay after an RCC peripheral clock enabling */\\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))\r
-#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))\r
-#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))\r
-#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))\r
-#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))\r
-#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))\r
-\r
-#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))\r
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))\r
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\r
- * @brief Get the enable or disable status of the APB2 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)\r
-#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)\r
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)\r
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)\r
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)\r
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)\r
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)\r
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)\r
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)\r
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)\r
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)\r
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)\r
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)\r
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)\r
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)\r
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)\r
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)\r
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset\r
- * @brief Force or release APB1 peripheral reset.\r
- * @{ \r
- */\r
-#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) \r
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\r
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\r
-#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))\r
-#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))\r
-#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))\r
-\r
-#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))\r
-#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))\r
-\r
-#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) \r
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\r
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\r
-#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))\r
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))\r
-#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))\r
-\r
-#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))\r
-#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset\r
- * @brief Force or release APB2 peripheral reset.\r
- * @{ \r
- */\r
-#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) \r
-#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))\r
-#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))\r
-#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))\r
-#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))\r
-#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))\r
-#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))\r
-\r
-#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))\r
-#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))\r
-#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))\r
-\r
-#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) \r
-#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))\r
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))\r
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))\r
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))\r
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))\r
-#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))\r
-\r
-#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))\r
-#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))\r
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_HSI_Configuration HSI Configuration\r
- * @{ \r
- */\r
-\r
-/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).\r
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
- * @note HSI can not be stopped if it is used as system clock source. In this case,\r
- * you have to select another source of the system clock then stop the HSI. \r
- * @note After enabling the HSI, the application software should wait on HSIRDY\r
- * flag to be set indicating that HSI clock is stable and can be used as\r
- * system clock source. \r
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
- * clock cycles. \r
- */\r
-#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)\r
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)\r
-\r
-/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.\r
- * @note The calibration is used to compensate for the variations in voltage\r
- * and temperature that influence the frequency of the internal HSI RC.\r
- * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.\r
- * (default is RCC_HSICALIBRATION_DEFAULT).\r
- * This parameter must be a number between 0 and 0x1F.\r
- */ \r
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \\r
- (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_LSI_Configuration LSI Configuration\r
- * @{ \r
- */\r
-\r
-/** @brief Macro to enable the Internal Low Speed oscillator (LSI).\r
- * @note After enabling the LSI, the application software should wait on \r
- * LSIRDY flag to be set indicating that LSI clock is stable and can\r
- * be used to clock the IWDG and/or the RTC.\r
- */\r
-#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)\r
-\r
-/** @brief Macro to disable the Internal Low Speed oscillator (LSI).\r
- * @note LSI can not be disabled if the IWDG is running. \r
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
- * clock cycles. \r
- */\r
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_HSE_Configuration HSE Configuration\r
- * @{ \r
- */\r
-\r
-/**\r
- * @brief Macro to configure the External High Speed oscillator (HSE).\r
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
- * supported by this macro. User should request a transition to HSE Off\r
- * first and then HSE On or HSE Bypass.\r
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
- * software should wait on HSERDY flag to be set indicating that HSE clock\r
- * is stable and can be used to clock the PLL and/or system clock.\r
- * @note HSE state can not be changed if it is used directly or through the\r
- * PLL as system clock. In this case, you have to select another source\r
- * of the system clock then change the HSE state (ex. disable it).\r
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
- * @note This function reset the CSSON bit, so if the clock security system(CSS)\r
- * was previously enabled you have to enable it again after calling this\r
- * function.\r
- * @param __STATE__ specifies the new state of the HSE.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after\r
- * 6 HSE oscillator clock cycles.\r
- * @arg @ref RCC_HSE_ON turn ON the HSE oscillator\r
- * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock\r
- */\r
-#define __HAL_RCC_HSE_CONFIG(__STATE__) \\r
- do{ \\r
- if ((__STATE__) == RCC_HSE_ON) \\r
- { \\r
- SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
- } \\r
- else if ((__STATE__) == RCC_HSE_OFF) \\r
- { \\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
- } \\r
- else if ((__STATE__) == RCC_HSE_BYPASS) \\r
- { \\r
- SET_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
- SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
- } \\r
- else \\r
- { \\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
- } \\r
- }while(0U)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_LSE_Configuration LSE Configuration\r
- * @{ \r
- */\r
-\r
-/**\r
- * @brief Macro to configure the External Low Speed oscillator (LSE).\r
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. \r
- * @note As the LSE is in the Backup domain and write access is denied to\r
- * this domain after reset, you have to enable write access using \r
- * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
- * (to be done once after reset). \r
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r
- * software should wait on LSERDY flag to be set indicating that LSE clock\r
- * is stable and can be used to clock the RTC.\r
- * @param __STATE__ specifies the new state of the LSE.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after\r
- * 6 LSE oscillator clock cycles.\r
- * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.\r
- * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.\r
- */\r
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \\r
- do{ \\r
- if ((__STATE__) == RCC_LSE_ON) \\r
- { \\r
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
- } \\r
- else if ((__STATE__) == RCC_LSE_OFF) \\r
- { \\r
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
- } \\r
- else if ((__STATE__) == RCC_LSE_BYPASS) \\r
- { \\r
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
- } \\r
- else \\r
- { \\r
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
- } \\r
- }while(0U)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_PLL_Configuration PLL Configuration\r
- * @{ \r
- */\r
-\r
-/** @brief Macro to enable the main PLL.\r
- * @note After enabling the main PLL, the application software should wait on \r
- * PLLRDY flag to be set indicating that PLL clock is stable and can\r
- * be used as system clock source.\r
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
- */\r
-#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)\r
-\r
-/** @brief Macro to disable the main PLL.\r
- * @note The main PLL can not be disabled if it is used as system clock source\r
- */\r
-#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)\r
-\r
-/** @brief Macro to configure the main PLL clock source and multiplication factors.\r
- * @note This function must be used only when the main PLL is disabled.\r
- * \r
- * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry\r
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry\r
- * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4\r
- * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6\r
- @if STM32F105xC\r
- * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5\r
- @elseif STM32F107xC\r
- * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5\r
- @else\r
- * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2\r
- * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3\r
- * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10\r
- * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11\r
- * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12\r
- * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13\r
- * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14\r
- * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15\r
- * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16\r
- @endif\r
- * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8\r
- * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9\r
- * \r
- */\r
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\\r
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))\r
-\r
-/** @brief Get oscillator clock selected as PLL input clock\r
- * @retval The clock source used for PLL entry. The returned value can be one\r
- * of the following:\r
- * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock\r
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock\r
- */\r
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Get_Clock_source Get Clock source\r
- * @{ \r
- */\r
-\r
-/**\r
- * @brief Macro to configure the system clock source.\r
- * @param __SYSCLKSOURCE__ specifies the system clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.\r
- * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.\r
- * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.\r
- */\r
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))\r
-\r
-/** @brief Macro to get the clock source used as system clock.\r
- * @retval The clock source used as system clock. The returned value can be one\r
- * of the following:\r
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock\r
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock\r
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock\r
- */\r
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config\r
- * @{ \r
- */ \r
-\r
-#if defined(RCC_CFGR_MCO_3)\r
-/** @brief Macro to configure the MCO clock.\r
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock\r
- * @param __MCODIV__ specifies the MCO clock prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source\r
- */\r
-#else\r
-/** @brief Macro to configure the MCO clock.\r
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock\r
- * @param __MCODIV__ specifies the MCO clock prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source\r
- */\r
-#endif\r
-\r
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration\r
- * @{ \r
- */\r
-\r
-/** @brief Macro to configure the RTC clock (RTCCLK).\r
- * @note As the RTC clock configuration bits are in the Backup domain and write\r
- * access is denied to this domain after reset, you have to enable write\r
- * access using the Power Backup Access macro before to configure\r
- * the RTC clock source (to be done once after reset). \r
- * @note Once the RTC clock is configured it can't be changed unless the \r
- * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by\r
- * a Power On Reset (POR).\r
- *\r
- * @param __RTC_CLKSOURCE__ specifies the RTC clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock\r
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock\r
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock\r
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock\r
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
- * work in STOP and STANDBY modes, and can be used as wakeup source.\r
- * However, when the HSE clock is used as RTC clock source, the RTC\r
- * cannot be used in STOP and STANDBY modes. \r
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
- * RTC clock source).\r
- */\r
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))\r
- \r
-/** @brief Macro to get the RTC clock source.\r
- * @retval The clock source can be one of the following values:\r
- * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock\r
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock\r
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock\r
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock\r
- */\r
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))\r
-\r
-/** @brief Macro to enable the the RTC clock.\r
- * @note These macros must be used only after the RTC clock source was selected.\r
- */\r
-#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)\r
-\r
-/** @brief Macro to disable the the RTC clock.\r
- * @note These macros must be used only after the RTC clock source was selected.\r
- */\r
-#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)\r
-\r
-/** @brief Macro to force the Backup domain reset.\r
- * @note This function resets the RTC peripheral (including the backup registers)\r
- * and the RTC clock source selection in RCC_BDCR register.\r
- */\r
-#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)\r
-\r
-/** @brief Macros to release the Backup domain reset.\r
- */\r
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r
- * @brief macros to manage the specified RCC Flags and interrupts.\r
- * @{\r
- */\r
-\r
-/** @brief Enable RCC interrupt.\r
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt\r
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt\r
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt\r
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt\r
- * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt\r
- @if STM32F105xx\r
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.\r
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.\r
- @elsif STM32F107xx\r
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.\r
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.\r
- @endif\r
- */\r
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))\r
-\r
-/** @brief Disable RCC interrupt.\r
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt\r
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt\r
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt\r
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt\r
- * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt\r
- @if STM32F105xx\r
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.\r
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.\r
- @elsif STM32F107xx\r
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.\r
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.\r
- @endif\r
- */\r
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))\r
-\r
-/** @brief Clear the RCC's interrupt pending bits.\r
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.\r
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt.\r
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.\r
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt.\r
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.\r
- @if STM32F105xx\r
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.\r
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.\r
- @elsif STM32F107xx\r
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.\r
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.\r
- @endif\r
- * @arg @ref RCC_IT_CSS Clock Security System interrupt\r
- */\r
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))\r
-\r
-/** @brief Check the RCC's interrupt has occurred or not.\r
- * @param __INTERRUPT__ specifies the RCC interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.\r
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt.\r
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.\r
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt.\r
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.\r
- @if STM32F105xx\r
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.\r
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.\r
- @elsif STM32F107xx\r
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.\r
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.\r
- @endif\r
- * @arg @ref RCC_IT_CSS Clock Security System interrupt\r
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
- */\r
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))\r
-\r
-/** @brief Set RMVF bit to clear the reset flags.\r
- * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,\r
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST\r
- */\r
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)\r
-\r
-/** @brief Check RCC flag is set or not.\r
- * @param __FLAG__ specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.\r
- * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.\r
- * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.\r
- @if STM32F105xx\r
- * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.\r
- * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.\r
- @elsif STM32F107xx\r
- * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.\r
- * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.\r
- @endif\r
- * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.\r
- * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.\r
- * @arg @ref RCC_FLAG_PINRST Pin reset.\r
- * @arg @ref RCC_FLAG_PORRST POR/PDR reset.\r
- * @arg @ref RCC_FLAG_SFTRST Software reset.\r
- * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.\r
- * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.\r
- * @arg @ref RCC_FLAG_LPWRRST Low Power reset.\r
- * @retval The new state of __FLAG__ (TRUE or FALSE).\r
- */\r
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \\r
- ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \\r
- RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Include RCC HAL Extension module */\r
-#include "stm32f1xx_hal_rcc_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup RCC_Exported_Functions\r
- * @{\r
- */\r
-\r
-/** @addtogroup RCC_Exported_Functions_Group1\r
- * @{\r
- */\r
-\r
-/* Initialization and de-initialization functions ******************************/\r
-HAL_StatusTypeDef HAL_RCC_DeInit(void);\r
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup RCC_Exported_Functions_Group2\r
- * @{\r
- */\r
-\r
-/* Peripheral Control functions ************************************************/\r
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r
-void HAL_RCC_EnableCSS(void);\r
-void HAL_RCC_DisableCSS(void);\r
-uint32_t HAL_RCC_GetSysClockFreq(void);\r
-uint32_t HAL_RCC_GetHCLKFreq(void);\r
-uint32_t HAL_RCC_GetPCLK1Freq(void);\r
-uint32_t HAL_RCC_GetPCLK2Freq(void);\r
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r
-\r
-/* CSS NMI IRQ handler */\r
-void HAL_RCC_NMI_IRQHandler(void);\r
-\r
-/* User Callbacks in non blocking mode (IT mode) */\r
-void HAL_RCC_CSSCallback(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup RCC_Private_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_Timeout RCC Timeout\r
- * @{\r
- */ \r
- \r
-/* Disable Backup domain write protection state change timeout */\r
-#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */\r
-/* LSE state change timeout */\r
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT\r
-#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */\r
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT\r
-#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */\r
-#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */\r
-#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup RCC_Register_Offset Register offsets\r
- * @{\r
- */\r
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
-#define RCC_CR_OFFSET 0x00U\r
-#define RCC_CFGR_OFFSET 0x04U\r
-#define RCC_CIR_OFFSET 0x08U\r
-#define RCC_BDCR_OFFSET 0x20U\r
-#define RCC_CSR_OFFSET 0x24U\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion\r
- * @brief RCC registers bit address in the alias region\r
- * @{\r
- */\r
-#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)\r
-#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)\r
-#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)\r
-#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)\r
-#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)\r
-\r
-/* --- CR Register ---*/\r
-/* Alias word address of HSION bit */\r
-#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos\r
-#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))\r
-/* Alias word address of HSEON bit */\r
-#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos\r
-#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))\r
-/* Alias word address of CSSON bit */\r
-#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos\r
-#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))\r
-/* Alias word address of PLLON bit */\r
-#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos\r
-#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))\r
-\r
-/* --- CSR Register ---*/\r
-/* Alias word address of LSION bit */\r
-#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos\r
-#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))\r
-\r
-/* Alias word address of RMVF bit */\r
-#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos\r
-#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))\r
-\r
-/* --- BDCR Registers ---*/\r
-/* Alias word address of LSEON bit */\r
-#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos\r
-#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))\r
-\r
-/* Alias word address of LSEON bit */\r
-#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos\r
-#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))\r
-\r
-/* Alias word address of RTCEN bit */\r
-#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos\r
-#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))\r
-\r
-/* Alias word address of BDRST bit */\r
-#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos\r
-#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/* CR register byte 2 (Bits[23:16]) base address */\r
-#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))\r
-\r
-/* CIR register byte 1 (Bits[15:8]) base address */\r
-#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))\r
-\r
-/* CIR register byte 2 (Bits[23:16]) base address */\r
-#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))\r
-\r
-/* Defines used for Flags */\r
-#define CR_REG_INDEX ((uint8_t)1)\r
-#define BDCR_REG_INDEX ((uint8_t)2)\r
-#define CSR_REG_INDEX ((uint8_t)3)\r
-\r
-#define RCC_FLAG_MASK ((uint8_t)0x1F)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup RCC_Private_Macros\r
- * @{\r
- */\r
-/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy\r
- * @{\r
- */\r
-#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r
-#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r
-#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r
-#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r
-/**\r
- * @}\r
- */\r
-\r
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \\r
- ((__SOURCE__) == RCC_PLLSOURCE_HSE))\r
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))\r
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \\r
- ((__HSE__) == RCC_HSE_BYPASS))\r
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \\r
- ((__LSE__) == RCC_LSE_BYPASS))\r
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))\r
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)\r
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))\r
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \\r
- ((__PLL__) == RCC_PLL_ON))\r
-\r
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \\r
- (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \\r
- (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \\r
- (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))\r
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \\r
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \\r
- ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))\r
-#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \\r
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \\r
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))\r
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \\r
- ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \\r
- ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \\r
- ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \\r
- ((__HCLK__) == RCC_SYSCLK_DIV512))\r
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \\r
- ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \\r
- ((__PCLK__) == RCC_HCLK_DIV16))\r
-#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)\r
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) \r
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \\r
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \\r
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \\r
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_RCC_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_rcc_ex.h\r
- * @author MCD Application Team\r
- * @brief Header file of RCC HAL Extension module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_RCC_EX_H\r
-#define __STM32F1xx_HAL_RCC_EX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup RCCEx\r
- * @{\r
- */ \r
-\r
-/** @addtogroup RCCEx_Private_Constants\r
- * @{\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-\r
-/* Alias word address of PLLI2SON bit */\r
-#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos\r
-#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U)))\r
-/* Alias word address of PLL2ON bit */\r
-#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos\r
-#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U)))\r
-\r
-#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */\r
-#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-\r
-#define CR_REG_INDEX ((uint8_t)1) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup RCCEx_Private_Macros\r
- * @{\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \\r
- ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\\r
- || defined(STM32F100xE)\r
-#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \\r
- ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \\r
- ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \\r
- ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \\r
- ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \\r
- ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \\r
- ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \\r
- ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))\r
-\r
-#else\r
-#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))\r
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \\r
- ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \\r
- ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \\r
- ((__MUL__) == RCC_PLL_MUL6_5))\r
-\r
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \\r
- || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \\r
- || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \\r
- || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \\r
- || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))\r
-\r
-#else\r
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \\r
- ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \\r
- ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \\r
- ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \\r
- ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \\r
- ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \\r
- ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \\r
- ((__MUL__) == RCC_PLL_MUL16))\r
-\r
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \\r
- || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \\r
- || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))\r
-\r
-#endif /* STM32F105xC || STM32F107xC*/\r
-\r
-#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \\r
- ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))\r
-\r
-#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))\r
-\r
-#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))\r
-\r
-#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \\r
- ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \\r
- ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \\r
- ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \\r
- ((__MUL__) == RCC_PLLI2S_MUL20))\r
-\r
-#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \\r
- ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \\r
- ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \\r
- ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \\r
- ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \\r
- ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \\r
- ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \\r
- ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))\r
-\r
-#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \\r
- ((__PLL__) == RCC_PLL2_ON))\r
-\r
-#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \\r
- ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \\r
- ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \\r
- ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \\r
- ((__MUL__) == RCC_PLL2_MUL20))\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \\r
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))\r
-\r
-#elif defined(STM32F103xE) || defined(STM32F103xG)\r
-\r
-#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)\r
-\r
-#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \\r
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))\r
-\r
-\r
-#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB)\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \\r
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))\r
-\r
-#else\r
-\r
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \\r
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \\r
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\r
-\r
-#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))\r
-\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/ \r
-\r
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r
- * @{\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** \r
- * @brief RCC PLL2 configuration structure definition \r
- */\r
-typedef struct\r
-{\r
- uint32_t PLL2State; /*!< The new state of the PLL2.\r
- This parameter can be a value of @ref RCCEx_PLL2_Config */\r
-\r
- uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock\r
- This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ \r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.\r
- This parameter can be a value of @ref RCCEx_Prediv2_Factor */\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-} RCC_PLL2InitTypeDef;\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/** \r
- * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition \r
- */\r
-typedef struct\r
-{\r
- uint32_t OscillatorType; /*!< The oscillators to be configured.\r
- This parameter can be a value of @ref RCC_Oscillator_Type */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- uint32_t Prediv1Source; /*!< The Prediv1 source value.\r
- This parameter can be a value of @ref RCCEx_Prediv1_Source */\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
- uint32_t HSEState; /*!< The new state of the HSE.\r
- This parameter can be a value of @ref RCC_HSE_Config */\r
- \r
- uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)\r
- This parameter can be a value of @ref RCCEx_Prediv1_Factor */\r
-\r
- uint32_t LSEState; /*!< The new state of the LSE.\r
- This parameter can be a value of @ref RCC_LSE_Config */\r
- \r
- uint32_t HSIState; /*!< The new state of the HSI.\r
- This parameter can be a value of @ref RCC_HSI_Config */\r
-\r
- uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r
- \r
- uint32_t LSIState; /*!< The new state of the LSI.\r
- This parameter can be a value of @ref RCC_LSI_Config */\r
-\r
- RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ \r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ \r
-#endif /* STM32F105xC || STM32F107xC */\r
-} RCC_OscInitTypeDef;\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** \r
- * @brief RCC PLLI2S configuration structure definition \r
- */\r
-typedef struct\r
-{\r
- uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock\r
- This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ \r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.\r
- This parameter can be a value of @ref RCCEx_Prediv2_Factor */\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-} RCC_PLLI2SInitTypeDef;\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/** \r
- * @brief RCC extended clocks structure definition \r
- */\r
-typedef struct\r
-{\r
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\r
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r
-\r
- uint32_t RTCClockSelection; /*!< specifies the RTC clock source.\r
- This parameter can be a value of @ref RCC_RTC_Clock_Source */\r
-\r
- uint32_t AdcClockSelection; /*!< ADC clock source \r
- This parameter can be a value of @ref RCCEx_ADC_Prescaler */\r
-\r
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\\r
- || defined(STM32F107xC)\r
- uint32_t I2s2ClockSelection; /*!< I2S2 clock source\r
- This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */\r
-\r
- uint32_t I2s3ClockSelection; /*!< I2S3 clock source\r
- This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */\r
- \r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters \r
- This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\\r
- || defined(STM32F105xC) || defined(STM32F107xC)\r
- uint32_t UsbClockSelection; /*!< USB clock source \r
- This parameter can be a value of @ref RCCEx_USB_Prescaler */\r
-\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-} RCC_PeriphCLKInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection\r
- * @{\r
- */\r
-#define RCC_PERIPHCLK_RTC 0x00000001U\r
-#define RCC_PERIPHCLK_ADC 0x00000002U\r
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\\r
- || defined(STM32F107xC)\r
-#define RCC_PERIPHCLK_I2S2 0x00000004U\r
-#define RCC_PERIPHCLK_I2S3 0x00000008U\r
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\\r
- || defined(STM32F105xC) || defined(STM32F107xC)\r
-#define RCC_PERIPHCLK_USB 0x00000010U\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler\r
- * @{\r
- */\r
-#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2\r
-#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4\r
-#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6\r
-#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\\r
- || defined(STM32F107xC)\r
-/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source\r
- * @{\r
- */\r
-#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source\r
- * @{\r
- */\r
-#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\r
-\r
-/** @defgroup RCCEx_USB_Prescaler USB Prescaler\r
- * @{\r
- */\r
-#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE\r
-#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */\r
-\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** @defgroup RCCEx_USB_Prescaler USB Prescaler\r
- * @{\r
- */\r
-#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE\r
-#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor\r
- * @{\r
- */\r
-\r
-#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */\r
-#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */\r
-#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */\r
-#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */\r
-#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */\r
-#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */\r
-#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */\r
-#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */\r
-#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */\r
-\r
-/**\r
- * @}\r
- */\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** @defgroup RCCEx_Prediv1_Source Prediv1 Source\r
- * @{\r
- */\r
-\r
-#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE\r
-#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2\r
-\r
-/**\r
- * @}\r
- */\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor\r
- * @{\r
- */\r
-\r
-#define RCC_HSE_PREDIV_DIV1 0x00000000U\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\\r
- || defined(STM32F100xE)\r
-#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2\r
-#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3\r
-#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4\r
-#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5\r
-#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6\r
-#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7\r
-#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8\r
-#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9\r
-#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10\r
-#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11\r
-#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12\r
-#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13\r
-#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14\r
-#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15\r
-#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16\r
-#else\r
-#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE\r
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor\r
- * @{\r
- */\r
-\r
-#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */\r
-#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */\r
-#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */\r
-#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */\r
-#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */\r
-#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */\r
-#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */\r
-#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */\r
-#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */\r
-#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */\r
-#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */\r
-#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */\r
-#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */\r
-#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */\r
-#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */\r
-#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_PLL2_Config PLL Config\r
- * @{\r
- */\r
-#define RCC_PLL2_NONE 0x00000000U\r
-#define RCC_PLL2_OFF 0x00000001U\r
-#define RCC_PLL2_ON 0x00000002U\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor\r
- * @{\r
- */\r
-\r
-#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */\r
-#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */\r
-#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */\r
-#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */\r
-#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */\r
-#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */\r
-#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */\r
-#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */\r
-#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor\r
- * @{\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#else\r
-#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2\r
-#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3\r
-#endif /* STM32F105xC || STM32F107xC */\r
-#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4\r
-#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5\r
-#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6\r
-#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7\r
-#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8\r
-#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5\r
-#else\r
-#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10\r
-#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11\r
-#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12\r
-#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13\r
-#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14\r
-#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15\r
-#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source\r
- * @{\r
- */\r
-#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)\r
-#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)\r
-#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)\r
-#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)\r
-#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)\r
-#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)\r
-#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)\r
-#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)\r
-#endif /* STM32F105xC || STM32F107xC*/\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** @defgroup RCCEx_Interrupt RCCEx Interrupt\r
- * @{\r
- */\r
-#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)\r
-#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RCCEx_Flag RCCEx Flag\r
- * Elements values convention: 0XXYYYYYb\r
- * - YYYYY : Flag position in the register\r
- * - XX : Register index\r
- * - 01: CR register\r
- * @{\r
- */\r
-/* Flags in the CR register */\r
-#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos))\r
-#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos))\r
-/**\r
- * @}\r
- */ \r
-#endif /* STM32F105xC || STM32F107xC*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r
- * @{\r
- */\r
-\r
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable\r
- * @brief Enable or disable the AHB1 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it. \r
- * @{\r
- */\r
-\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\\r
- || defined (STM32F100xE)\r
-#define __HAL_RCC_DMA2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */\r
-\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG) || defined (STM32F100xE)\r
-#define __HAL_RCC_FSMC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */\r
-\r
-#if defined(STM32F103xE) || defined(STM32F103xG)\r
-#define __HAL_RCC_SDIO_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-\r
-#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))\r
-#endif /* STM32F103xE || STM32F103xG */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-\r
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))\r
-#endif /* STM32F105xC || STM32F107xC*/\r
-\r
-#if defined(STM32F107xC)\r
-#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))\r
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))\r
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))\r
-\r
-/**\r
- * @brief Enable ETHERNET clock.\r
- */\r
-#define __HAL_RCC_ETH_CLK_ENABLE() do { \\r
- __HAL_RCC_ETHMAC_CLK_ENABLE(); \\r
- __HAL_RCC_ETHMACTX_CLK_ENABLE(); \\r
- __HAL_RCC_ETHMACRX_CLK_ENABLE(); \\r
- } while(0U)\r
-/**\r
- * @brief Disable ETHERNET clock.\r
- */\r
-#define __HAL_RCC_ETH_CLK_DISABLE() do { \\r
- __HAL_RCC_ETHMACTX_CLK_DISABLE(); \\r
- __HAL_RCC_ETHMACRX_CLK_DISABLE(); \\r
- __HAL_RCC_ETHMAC_CLK_DISABLE(); \\r
- } while(0U)\r
- \r
-#endif /* STM32F107xC*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\r
- * @brief Get the enable or disable status of the AHB1 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\\r
- || defined (STM32F100xE)\r
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)\r
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG) || defined (STM32F100xE)\r
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)\r
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */\r
-#if defined(STM32F103xE) || defined(STM32F103xG)\r
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)\r
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)\r
-#endif /* STM32F103xE || STM32F103xG */\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)\r
-#endif /* STM32F105xC || STM32F107xC*/\r
-#if defined(STM32F107xC)\r
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)\r
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)\r
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)\r
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)\r
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)\r
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)\r
-#endif /* STM32F107xC*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable\r
- * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it. \r
- * @{ \r
- */\r
-\r
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\\r
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)\r
-#define __HAL_RCC_CAN1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\r
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\\r
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\\r
- || defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_TIM4_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\r
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))\r
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\r
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))\r
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\r
-#define __HAL_RCC_USB_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */\r
-\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_DAC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))\r
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\r
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\r
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\r
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\r
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\r
-#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F100xB) || defined (STM32F100xE)\r
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_DAC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_CEC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\r
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\r
-#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\r
-#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))\r
-#endif /* STM32F100xB || STM32F100xE */\r
-\r
-#ifdef STM32F100xE\r
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM12_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM13_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM14_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))\r
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\r
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\r
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\r
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\r
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\r
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\r
-#endif /* STM32F100xE */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_CAN2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F101xG) || defined(STM32F103xG)\r
-#define __HAL_RCC_TIM12_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM13_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM14_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\r
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\r
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\r
-#endif /* STM32F101xG || STM32F103xG*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\r
- * @brief Get the enable or disable status of the APB1 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\\r
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)\r
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)\r
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)\r
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\\r
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\\r
- || defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)\r
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)\r
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)\r
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)\r
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)\r
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)\r
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)\r
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)\r
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\r
-#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)\r
-#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)\r
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)\r
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)\r
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)\r
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)\r
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)\r
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)\r
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)\r
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)\r
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)\r
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)\r
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)\r
-#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)\r
-#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */\r
-#if defined(STM32F100xB) || defined (STM32F100xE)\r
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)\r
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)\r
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)\r
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)\r
-#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)\r
-#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)\r
-#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)\r
-#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)\r
-#endif /* STM32F100xB || STM32F100xE */\r
-#ifdef STM32F100xE\r
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)\r
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)\r
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)\r
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)\r
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)\r
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)\r
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)\r
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)\r
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)\r
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)\r
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)\r
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)\r
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)\r
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)\r
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)\r
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)\r
-#endif /* STM32F100xE */\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)\r
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)\r
-#endif /* STM32F105xC || STM32F107xC */\r
-#if defined(STM32F101xG) || defined(STM32F103xG)\r
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)\r
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)\r
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)\r
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)\r
-#endif /* STM32F101xG || STM32F103xG*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable\r
- * @brief Enable or disable the High Speed APB (APB2) peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it.\r
- * @{ \r
- */\r
-\r
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\\r
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\\r
- || defined(STM32F103xG)\r
-#define __HAL_RCC_ADC2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))\r
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */\r
-\r
-#if defined(STM32F100xB) || defined(STM32F100xE)\r
-#define __HAL_RCC_TIM15_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM16_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM17_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))\r
-#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))\r
-#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))\r
-#endif /* STM32F100xB || STM32F100xE */\r
-\r
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\\r
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\\r
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\\r
- || defined(STM32F107xC)\r
-#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))\r
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG)\r
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))\r
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/\r
-\r
-#if defined(STM32F103xE) || defined(STM32F103xG)\r
-#define __HAL_RCC_TIM8_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_ADC3_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\r
-#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))\r
-#endif /* STM32F103xE || STM32F103xG */\r
-\r
-#if defined(STM32F100xE)\r
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))\r
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))\r
-#endif /* STM32F100xE */\r
-\r
-#if defined(STM32F101xG) || defined(STM32F103xG)\r
-#define __HAL_RCC_TIM9_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM10_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM11_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
- UNUSED(tmpreg); \\r
- } while(0U)\r
-\r
-#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))\r
-#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\r
-#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))\r
-#endif /* STM32F101xG || STM32F103xG */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\r
- * @brief Get the enable or disable status of the APB2 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\\r
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\\r
- || defined(STM32F103xG)\r
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)\r
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)\r
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */\r
-#if defined(STM32F100xB) || defined(STM32F100xE)\r
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)\r
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)\r
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)\r
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)\r
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)\r
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)\r
-#endif /* STM32F100xB || STM32F100xE */\r
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\\r
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\\r
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\\r
- || defined(STM32F107xC)\r
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)\r
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)\r
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG)\r
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)\r
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)\r
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)\r
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/\r
-#if defined(STM32F103xE) || defined(STM32F103xG)\r
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)\r
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\r
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)\r
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)\r
-#endif /* STM32F103xE || STM32F103xG */\r
-#if defined(STM32F100xE)\r
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)\r
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)\r
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)\r
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)\r
-#endif /* STM32F100xE */\r
-#if defined(STM32F101xG) || defined(STM32F103xG)\r
-#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)\r
-#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)\r
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)\r
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)\r
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)\r
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)\r
-#endif /* STM32F101xG || STM32F103xG */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release\r
- * @brief Force or release AHB peripheral reset.\r
- * @{\r
- */ \r
-#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)\r
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))\r
-#if defined(STM32F107xC)\r
-#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))\r
-#endif /* STM32F107xC */\r
-\r
-#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)\r
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))\r
-#if defined(STM32F107xC)\r
-#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))\r
-#endif /* STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset\r
- * @brief Force or release APB1 peripheral reset.\r
- * @{ \r
- */\r
-\r
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\\r
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)\r
-#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\r
-\r
-#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\r
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\\r
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\\r
- || defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\r
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))\r
-#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\r
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))\r
-\r
-#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\r
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))\r
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\r
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))\r
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\r
-#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))\r
-#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */\r
-\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))\r
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\r
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\r
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\r
-#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\r
-#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\r
-#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\r
-\r
-#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))\r
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\r
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\r
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\r
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\r
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\r
-#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F100xB) || defined (STM32F100xE)\r
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\r
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\r
-#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\r
-#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))\r
-\r
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\r
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\r
-#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\r
-#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))\r
-#endif /* STM32F100xB || STM32F100xE */\r
-\r
-#if defined (STM32F100xE)\r
-#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))\r
-#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\r
-#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\r
-#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\r
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\r
-#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\r
-#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\r
-\r
-#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))\r
-#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\r
-#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\r
-#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\r
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\r
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\r
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\r
-#endif /* STM32F100xE */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\r
-\r
-#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F101xG) || defined(STM32F103xG)\r
-#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\r
-#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\r
-#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\r
-\r
-#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\r
-#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\r
-#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\r
-#endif /* STM32F101xG || STM32F103xG */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset\r
- * @brief Force or release APB2 peripheral reset.\r
- * @{ \r
- */\r
-\r
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\\r
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\\r
- || defined(STM32F103xG)\r
-#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))\r
-\r
-#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))\r
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */\r
-\r
-#if defined(STM32F100xB) || defined(STM32F100xE)\r
-#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))\r
-#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))\r
-#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))\r
-\r
-#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))\r
-#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))\r
-#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))\r
-#endif /* STM32F100xB || STM32F100xE */\r
-\r
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\\r
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\\r
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\\r
- || defined(STM32F107xC)\r
-#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))\r
-\r
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))\r
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\\r
- || defined(STM32F103xG)\r
-#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))\r
-#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))\r
-\r
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))\r
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))\r
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/\r
-\r
-#if defined(STM32F103xE) || defined(STM32F103xG)\r
-#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\r
-#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))\r
-\r
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\r
-#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))\r
-#endif /* STM32F103xE || STM32F103xG */\r
-\r
-#if defined(STM32F100xE)\r
-#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))\r
-#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))\r
-\r
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))\r
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))\r
-#endif /* STM32F100xE */\r
-\r
-#if defined(STM32F101xG) || defined(STM32F103xG)\r
-#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))\r
-#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\r
-#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))\r
-\r
-#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))\r
-#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\r
-#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))\r
-#endif /* STM32F101xG || STM32F103xG*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_HSE_Configuration HSE Configuration\r
- * @{ \r
- */ \r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\\r
- || defined(STM32F100xE)\r
-/**\r
- * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.\r
- * @note Predivision factor can not be changed if PLL is used as system clock\r
- * In this case, you have to select another source of the system clock, disable the PLL and\r
- * then change the HSE predivision factor.\r
- * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.\r
- * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.\r
- */\r
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))\r
-#else\r
-/**\r
- * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.\r
- * @note Predivision factor can not be changed if PLL is used as system clock\r
- * In this case, you have to select another source of the system clock, disable the PLL and\r
- * then change the HSE predivision factor.\r
- * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.\r
- * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.\r
- */\r
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \\r
- MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\\r
- || defined(STM32F100xE)\r
-/**\r
- * @brief Macro to get prediv1 factor for PLL.\r
- */\r
-#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)\r
-\r
-#else\r
-/**\r
- * @brief Macro to get prediv1 factor for PLL.\r
- */\r
-#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)\r
-\r
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration\r
- * @{ \r
- */ \r
-\r
-/** @brief Macros to enable the main PLLI2S.\r
- * @note After enabling the main PLLI2S, the application software should wait on \r
- * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can\r
- * be used as system clock source.\r
- * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.\r
- */\r
-#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)\r
-\r
-/** @brief Macros to disable the main PLLI2S.\r
- * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.\r
- */\r
-#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)\r
-\r
-/** @brief macros to configure the main PLLI2S multiplication factor.\r
- * @note This function must be used only when the main PLLI2S is disabled.\r
- * \r
- * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8\r
- * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9\r
- * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10\r
- * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11\r
- * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12\r
- * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13\r
- * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14\r
- * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16\r
- * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20\r
- * \r
- */\r
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\\r
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration\r
- * @brief Macros to configure clock source of different peripherals.\r
- * @{\r
- */ \r
-\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\r
-/** @brief Macro to configure the USB clock.\r
- * @param __USBCLKSOURCE__ specifies the USB clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock\r
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock\r
- */\r
-#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))\r
-\r
-/** @brief Macro to get the USB clock (USBCLK).\r
- * @retval The clock source can be one of the following values:\r
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock\r
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock\r
- */\r
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))\r
-\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-\r
-/** @brief Macro to configure the USB OTSclock.\r
- * @param __USBCLKSOURCE__ specifies the USB clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock\r
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock\r
- */\r
-#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))\r
-\r
-/** @brief Macro to get the USB clock (USBCLK).\r
- * @retval The clock source can be one of the following values:\r
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock\r
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock\r
- */\r
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).\r
- * @param __ADCCLKSOURCE__ specifies the ADC clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock\r
- * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock\r
- * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock\r
- * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock\r
- */\r
-#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))\r
-\r
-/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).\r
- * @retval The clock source can be one of the following values:\r
- * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock\r
- * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock\r
- * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock\r
- * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock\r
- */\r
-#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-\r
-/** @addtogroup RCCEx_HSE_Configuration\r
- * @{ \r
- */ \r
-\r
-/**\r
- * @brief Macro to configure the PLL2 & PLLI2S Predivision factor.\r
- * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock\r
- * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and\r
- * then change the PREDIV2 factor.\r
- * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.\r
- * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.\r
- */\r
-#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \\r
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))\r
- \r
-/**\r
- * @brief Macro to get prediv2 factor for PLL2 & PLL3.\r
- */\r
-#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup RCCEx_PLLI2S_Configuration\r
- * @{ \r
- */ \r
-\r
-/** @brief Macros to enable the main PLL2.\r
- * @note After enabling the main PLL2, the application software should wait on \r
- * PLL2RDY flag to be set indicating that PLL2 clock is stable and can\r
- * be used as system clock source.\r
- * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.\r
- */\r
-#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)\r
-\r
-/** @brief Macros to disable the main PLL2.\r
- * @note The main PLL2 can not be disabled if it is used indirectly as system clock source\r
- * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.\r
- */\r
-#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)\r
-\r
-/** @brief macros to configure the main PLL2 multiplication factor.\r
- * @note This function must be used only when the main PLL2 is disabled.\r
- * \r
- * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8\r
- * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9\r
- * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10\r
- * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11\r
- * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12\r
- * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13\r
- * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14\r
- * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16\r
- * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20\r
- * \r
- */\r
-#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\\r
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_I2S_Configuration I2S Configuration\r
- * @brief Macros to configure clock source of I2S peripherals.\r
- * @{\r
- */ \r
-\r
-/** @brief Macro to configure the I2S2 clock.\r
- * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry\r
- * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry\r
- */\r
-#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \\r
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))\r
-\r
-/** @brief Macro to get the I2S2 clock (I2S2CLK).\r
- * @retval The clock source can be one of the following values:\r
- * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry\r
- * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry\r
- */\r
-#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))\r
-\r
-/** @brief Macro to configure the I2S3 clock.\r
- * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry\r
- * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry\r
- */\r
-#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \\r
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))\r
-\r
-/** @brief Macro to get the I2S3 clock (I2S3CLK).\r
- * @retval The clock source can be one of the following values:\r
- * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry\r
- * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry\r
- */\r
-#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup RCCEx_Exported_Functions\r
- * @{\r
- */\r
-\r
-/** @addtogroup RCCEx_Exported_Functions_Group1\r
- * @{\r
- */\r
-\r
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** @addtogroup RCCEx_Exported_Functions_Group2\r
- * @{\r
- */\r
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);\r
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup RCCEx_Exported_Functions_Group3\r
- * @{\r
- */\r
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);\r
-HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);\r
-\r
-/**\r
- * @}\r
- */\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
- \r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_RCC_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_tim.h\r
- * @author MCD Application Team\r
- * @brief Header file of TIM HAL module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_TIM_H\r
-#define __STM32F1xx_HAL_TIM_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup TIM\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup TIM_Exported_Types TIM Exported Types\r
- * @{\r
- */\r
-/**\r
- * @brief TIM Time base Configuration Structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
-\r
- uint32_t CounterMode; /*!< Specifies the counter mode.\r
- This parameter can be a value of @ref TIM_Counter_Mode */\r
-\r
- uint32_t Period; /*!< Specifies the period value to be loaded into the active\r
- Auto-Reload Register at the next update event.\r
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
-\r
- uint32_t ClockDivision; /*!< Specifies the clock division.\r
- This parameter can be a value of @ref TIM_ClockDivision */\r
-\r
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
- reaches zero, an update event is generated and counting restarts\r
- from the RCR value (N).\r
- This means in PWM mode that (N+1) corresponds to:\r
- - the number of PWM periods in edge-aligned mode\r
- - the number of half PWM period in center-aligned mode\r
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
- \r
- uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.\r
- This parameter can be a value of @ref TIM_AutoReloadPreload */\r
-} TIM_Base_InitTypeDef;\r
-\r
-/**\r
- * @brief TIM Output Compare Configuration Structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t OCMode; /*!< Specifies the TIM mode.\r
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
-\r
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
-\r
- uint32_t OCPolarity; /*!< Specifies the output polarity.\r
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
-\r
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.\r
- This parameter can be a value of @ref TIM_Output_Fast_State\r
- @note This parameter is valid only in PWM1 and PWM2 mode. */\r
-\r
-\r
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-} TIM_OC_InitTypeDef;\r
-\r
-/**\r
- * @brief TIM One Pulse Mode Configuration Structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t OCMode; /*!< Specifies the TIM mode.\r
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
-\r
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
-\r
- uint32_t OCPolarity; /*!< Specifies the output polarity.\r
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
-\r
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
- uint32_t ICSelection; /*!< Specifies the input.\r
- This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
- uint32_t ICFilter; /*!< Specifies the input capture filter.\r
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-} TIM_OnePulse_InitTypeDef;\r
-\r
-\r
-/**\r
- * @brief TIM Input Capture Configuration Structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
- uint32_t ICSelection; /*!< Specifies the input.\r
- This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
- uint32_t ICFilter; /*!< Specifies the input capture filter.\r
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-} TIM_IC_InitTypeDef;\r
-\r
-/**\r
- * @brief TIM Encoder Configuration Structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.\r
- This parameter can be a value of @ref TIM_Encoder_Mode */\r
-\r
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.\r
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
- uint32_t IC1Selection; /*!< Specifies the input.\r
- This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.\r
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
- uint32_t IC1Filter; /*!< Specifies the input capture filter.\r
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-\r
- uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.\r
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
- uint32_t IC2Selection; /*!< Specifies the input.\r
- This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
- uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.\r
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
- uint32_t IC2Filter; /*!< Specifies the input capture filter.\r
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-} TIM_Encoder_InitTypeDef;\r
-\r
-\r
-/**\r
- * @brief TIM Clock Configuration Handle Structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t ClockSource; /*!< TIM clock sources\r
- This parameter can be a value of @ref TIM_Clock_Source */\r
- uint32_t ClockPolarity; /*!< TIM clock polarity\r
- This parameter can be a value of @ref TIM_Clock_Polarity */\r
- uint32_t ClockPrescaler; /*!< TIM clock prescaler\r
- This parameter can be a value of @ref TIM_Clock_Prescaler */\r
- uint32_t ClockFilter; /*!< TIM clock filter\r
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-}TIM_ClockConfigTypeDef;\r
-\r
-/**\r
- * @brief TIM Clear Input Configuration Handle Structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t ClearInputState; /*!< TIM clear Input state\r
- This parameter can be ENABLE or DISABLE */\r
- uint32_t ClearInputSource; /*!< TIM clear Input sources\r
- This parameter can be a value of @ref TIM_ClearInput_Source */\r
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity\r
- This parameter can be a value of @ref TIM_ClearInput_Polarity */\r
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler\r
- This parameter can be a value of @ref TIM_ClearInput_Prescaler */\r
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter\r
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-}TIM_ClearInputConfigTypeDef;\r
-\r
-/**\r
- * @brief TIM Slave configuration Structure definition\r
- */\r
-typedef struct {\r
- uint32_t SlaveMode; /*!< Slave mode selection\r
- This parameter can be a value of @ref TIM_Slave_Mode */\r
- uint32_t InputTrigger; /*!< Input Trigger source\r
- This parameter can be a value of @ref TIM_Trigger_Selection */\r
- uint32_t TriggerPolarity; /*!< Input Trigger polarity\r
- This parameter can be a value of @ref TIM_Trigger_Polarity */\r
- uint32_t TriggerPrescaler; /*!< Input trigger prescaler\r
- This parameter can be a value of @ref TIM_Trigger_Prescaler */\r
- uint32_t TriggerFilter; /*!< Input trigger filter\r
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
-\r
-}TIM_SlaveConfigTypeDef;\r
-\r
-/**\r
- * @brief HAL State structures definition\r
- */\r
-typedef enum\r
-{\r
- HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */\r
- HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */\r
- HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */\r
- HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */\r
- HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */\r
-}HAL_TIM_StateTypeDef;\r
-\r
-/**\r
- * @brief HAL Active channel structures definition\r
- */\r
-typedef enum\r
-{\r
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */\r
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */\r
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */\r
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */\r
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */\r
-}HAL_TIM_ActiveChannel;\r
-\r
-/**\r
- * @brief TIM Time Base Handle Structure definition\r
- */\r
-typedef struct\r
-{\r
- TIM_TypeDef *Instance; /*!< Register base address */\r
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */\r
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */\r
- DMA_HandleTypeDef *hdma[7U]; /*!< DMA Handlers array\r
- This array is accessed by a @ref TIM_DMA_Handle_index */\r
- HAL_LockTypeDef Lock; /*!< Locking object */\r
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */\r
-}TIM_HandleTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup TIM_Exported_Constants TIM Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity\r
- * @{\r
- */\r
-#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */\r
-#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */\r
-#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity\r
- * @{\r
- */\r
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */\r
-#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler\r
- * @{\r
- */\r
-#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */\r
-#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */\r
-#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */\r
-#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Counter_Mode TIM Counter Mode\r
- * @{\r
- */\r
-#define TIM_COUNTERMODE_UP 0x00000000U\r
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR\r
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0\r
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1\r
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_ClockDivision TIM ClockDivision\r
- * @{\r
- */\r
-#define TIM_CLOCKDIVISION_DIV1 0x00000000U\r
-#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)\r
-#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload\r
- * @{\r
- */\r
-#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /*!< TIMx_ARR register is not buffered */\r
-#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes\r
- * @{\r
- */\r
-#define TIM_OCMODE_TIMING 0x00000000U\r
-#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)\r
-#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)\r
-#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)\r
-#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)\r
-#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)\r
-#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)\r
-#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State\r
- * @{\r
- */\r
-#define TIM_OUTPUTSTATE_DISABLE 0x00000000U\r
-#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State\r
- * @{\r
- */\r
-#define TIM_OCFAST_DISABLE 0x00000000U\r
-#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\r
- * @{\r
- */\r
-#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U\r
-#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity\r
- * @{\r
- */\r
-#define TIM_OCPOLARITY_HIGH 0x00000000U\r
-#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity\r
- * @{\r
- */\r
-#define TIM_OCNPOLARITY_HIGH 0x00000000U\r
-#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State\r
- * @{\r
- */\r
-#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)\r
-#define TIM_OCIDLESTATE_RESET 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State\r
- * @{\r
- */\r
-#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)\r
-#define TIM_OCNIDLESTATE_RESET 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Channel TIM Channel\r
- * @{\r
- */\r
-#define TIM_CHANNEL_1 0x00000000U\r
-#define TIM_CHANNEL_2 0x00000004U\r
-#define TIM_CHANNEL_3 0x00000008U\r
-#define TIM_CHANNEL_4 0x0000000CU\r
-#define TIM_CHANNEL_ALL 0x00000018U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity\r
- * @{\r
- */\r
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */\r
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */\r
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection\r
- * @{\r
- */\r
-#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
- connected to IC1, IC2, IC3 or IC4, respectively */\r
-#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
- connected to IC2, IC1, IC4 or IC3, respectively */\r
-#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler\r
- * @{\r
- */\r
-#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */\r
-#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */\r
-#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */\r
-#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\r
- * @{\r
- */\r
-#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)\r
-#define TIM_OPMODE_REPETITIVE 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\r
- * @{\r
- */\r
-#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)\r
-#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)\r
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition\r
- * @{\r
- */\r
-#define TIM_IT_UPDATE (TIM_DIER_UIE)\r
-#define TIM_IT_CC1 (TIM_DIER_CC1IE)\r
-#define TIM_IT_CC2 (TIM_DIER_CC2IE)\r
-#define TIM_IT_CC3 (TIM_DIER_CC3IE)\r
-#define TIM_IT_CC4 (TIM_DIER_CC4IE)\r
-#define TIM_IT_COM (TIM_DIER_COMIE)\r
-#define TIM_IT_TRIGGER (TIM_DIER_TIE)\r
-#define TIM_IT_BREAK (TIM_DIER_BIE)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Commutation_Source TIM Commutation Source\r
- * @{\r
- */\r
-#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)\r
-#define TIM_COMMUTATION_SOFTWARE 0x00000000U\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_DMA_sources TIM DMA Sources\r
- * @{\r
- */\r
-#define TIM_DMA_UPDATE (TIM_DIER_UDE)\r
-#define TIM_DMA_CC1 (TIM_DIER_CC1DE)\r
-#define TIM_DMA_CC2 (TIM_DIER_CC2DE)\r
-#define TIM_DMA_CC3 (TIM_DIER_CC3DE)\r
-#define TIM_DMA_CC4 (TIM_DIER_CC4DE)\r
-#define TIM_DMA_COM (TIM_DIER_COMDE)\r
-#define TIM_DMA_TRIGGER (TIM_DIER_TDE)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Event_Source TIM Event Source\r
- * @{\r
- */\r
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG\r
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G\r
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G\r
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G\r
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G\r
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG\r
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG\r
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Flag_definition TIM Flag Definition\r
- * @{\r
- */\r
-#define TIM_FLAG_UPDATE (TIM_SR_UIF)\r
-#define TIM_FLAG_CC1 (TIM_SR_CC1IF)\r
-#define TIM_FLAG_CC2 (TIM_SR_CC2IF)\r
-#define TIM_FLAG_CC3 (TIM_SR_CC3IF)\r
-#define TIM_FLAG_CC4 (TIM_SR_CC4IF)\r
-#define TIM_FLAG_COM (TIM_SR_COMIF)\r
-#define TIM_FLAG_TRIGGER (TIM_SR_TIF)\r
-#define TIM_FLAG_BREAK (TIM_SR_BIF)\r
-#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)\r
-#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)\r
-#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)\r
-#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Clock_Source TIM Clock Source\r
- * @{\r
- */\r
-#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)\r
-#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)\r
-#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)\r
-#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)\r
-#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)\r
-#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)\r
-#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)\r
-#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)\r
-#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)\r
-#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity\r
- * @{\r
- */\r
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */\r
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */\r
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */\r
-#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */\r
-#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler\r
- * @{\r
- */\r
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\r
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\r
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_ClearInput_Source TIM ClearInput Source\r
- * @{\r
- */\r
-#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U\r
-#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity\r
- * @{\r
- */\r
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */\r
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\r
- * @{\r
- */\r
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\r
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\r
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state\r
- * @{\r
- */\r
-#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)\r
-#define TIM_OSSR_DISABLE 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state\r
- * @{\r
- */\r
-#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)\r
-#define TIM_OSSI_DISABLE 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Lock_level TIM Lock level\r
- * @{\r
- */\r
-#define TIM_LOCKLEVEL_OFF 0x00000000U\r
-#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)\r
-#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)\r
-#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable\r
- * @{\r
- */\r
-#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)\r
-#define TIM_BREAK_DISABLE 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity\r
- * @{\r
- */\r
-#define TIM_BREAKPOLARITY_LOW 0x00000000U\r
-#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)\r
-/**\r
- * @}\r
- */\r
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable\r
- * @{\r
- */\r
-#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)\r
-#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\r
- * @{\r
- */\r
-#define TIM_TRGO_RESET 0x00000000U\r
-#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)\r
-#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)\r
-#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))\r
-#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)\r
-#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))\r
-#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))\r
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Slave_Mode TIM Slave Mode\r
- * @{\r
- */\r
-#define TIM_SLAVEMODE_DISABLE 0x00000000U\r
-#define TIM_SLAVEMODE_RESET 0x00000004U\r
-#define TIM_SLAVEMODE_GATED 0x00000005U\r
-#define TIM_SLAVEMODE_TRIGGER 0x00000006U\r
-#define TIM_SLAVEMODE_EXTERNAL1 0x00000007U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode\r
- * @{\r
- */\r
-#define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U\r
-#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection\r
- * @{\r
- */\r
-#define TIM_TS_ITR0 0x00000000U\r
-#define TIM_TS_ITR1 0x00000010U\r
-#define TIM_TS_ITR2 0x00000020U\r
-#define TIM_TS_ITR3 0x00000030U\r
-#define TIM_TS_TI1F_ED 0x00000040U\r
-#define TIM_TS_TI1FP1 0x00000050U\r
-#define TIM_TS_TI2FP2 0x00000060U\r
-#define TIM_TS_ETRF 0x00000070U\r
-#define TIM_TS_NONE 0x0000FFFFU\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\r
- * @{\r
- */\r
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */\r
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */\r
-#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
-#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
-#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\r
- * @{\r
- */\r
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\r
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\r
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection\r
- * @{\r
- */\r
-#define TIM_TI1SELECTION_CH1 0x00000000U\r
-#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address\r
- * @{\r
- */\r
-#define TIM_DMABASE_CR1 0x00000000U\r
-#define TIM_DMABASE_CR2 0x00000001U\r
-#define TIM_DMABASE_SMCR 0x00000002U\r
-#define TIM_DMABASE_DIER 0x00000003U\r
-#define TIM_DMABASE_SR 0x00000004U\r
-#define TIM_DMABASE_EGR 0x00000005U\r
-#define TIM_DMABASE_CCMR1 0x00000006U\r
-#define TIM_DMABASE_CCMR2 0x00000007U\r
-#define TIM_DMABASE_CCER 0x00000008U\r
-#define TIM_DMABASE_CNT 0x00000009U\r
-#define TIM_DMABASE_PSC 0x0000000AU\r
-#define TIM_DMABASE_ARR 0x0000000BU\r
-#define TIM_DMABASE_RCR 0x0000000CU\r
-#define TIM_DMABASE_CCR1 0x0000000DU\r
-#define TIM_DMABASE_CCR2 0x0000000EU\r
-#define TIM_DMABASE_CCR3 0x0000000FU\r
-#define TIM_DMABASE_CCR4 0x00000010U\r
-#define TIM_DMABASE_BDTR 0x00000011U\r
-#define TIM_DMABASE_DCR 0x00000012U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length\r
- * @{\r
- */\r
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U\r
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U\r
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U\r
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U\r
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U\r
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U\r
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U\r
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U\r
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U\r
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U\r
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U\r
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U\r
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U\r
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U\r
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U\r
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U\r
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U\r
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index\r
- * @{\r
- */\r
-#define TIM_DMA_ID_UPDATE ((uint16_t)0x0) /*!< Index of the DMA handle used for Update DMA requests */\r
-#define TIM_DMA_ID_CC1 ((uint16_t)0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\r
-#define TIM_DMA_ID_CC2 ((uint16_t)0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\r
-#define TIM_DMA_ID_CC3 ((uint16_t)0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\r
-#define TIM_DMA_ID_CC4 ((uint16_t)0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\r
-#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x5) /*!< Index of the DMA handle used for Commutation DMA requests */\r
-#define TIM_DMA_ID_TRIGGER ((uint16_t)0x6) /*!< Index of the DMA handle used for Trigger DMA requests */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State\r
- * @{\r
- */\r
-#define TIM_CCx_ENABLE 0x00000001U\r
-#define TIM_CCx_DISABLE 0x00000000U\r
-#define TIM_CCxN_ENABLE 0x00000004U\r
-#define TIM_CCxN_DISABLE 0x00000000U\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private Constants -----------------------------------------------------------*/\r
-/** @defgroup TIM_Private_Constants TIM Private Constants\r
- * @{\r
- */\r
-\r
-/* The counter of a timer instance is disabled only if all the CCx and CCxN\r
- channels have been disabled */\r
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\r
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private Macros -----------------------------------------------------------*/\r
-/** @defgroup TIM_Private_Macros TIM Private Macros\r
- * @{\r
- */\r
-\r
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \\r
- ((MODE) == TIM_COUNTERMODE_DOWN) || \\r
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \\r
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \\r
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))\r
-\r
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \\r
- ((DIV) == TIM_CLOCKDIVISION_DIV2) || \\r
- ((DIV) == TIM_CLOCKDIVISION_DIV4))\r
-\r
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \\r
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))\r
-\r
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \\r
- ((MODE) == TIM_OCMODE_PWM2))\r
- \r
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \\r
- ((MODE) == TIM_OCMODE_ACTIVE) || \\r
- ((MODE) == TIM_OCMODE_INACTIVE) || \\r
- ((MODE) == TIM_OCMODE_TOGGLE) || \\r
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \\r
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE))\r
-\r
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \\r
- ((STATE) == TIM_OCFAST_ENABLE))\r
-\r
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \\r
- ((POLARITY) == TIM_OCPOLARITY_LOW))\r
-\r
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \\r
- ((POLARITY) == TIM_OCNPOLARITY_LOW))\r
-\r
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \\r
- ((STATE) == TIM_OCIDLESTATE_RESET))\r
-\r
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \\r
- ((STATE) == TIM_OCNIDLESTATE_RESET))\r
-\r
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3) || \\r
- ((CHANNEL) == TIM_CHANNEL_4) || \\r
- ((CHANNEL) == TIM_CHANNEL_ALL))\r
-\r
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2))\r
-\r
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2) || \\r
- ((CHANNEL) == TIM_CHANNEL_3))\r
-\r
-#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \\r
- ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \\r
- ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\r
-\r
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \\r
- ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \\r
- ((SELECTION) == TIM_ICSELECTION_TRC))\r
-\r
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV8))\r
-\r
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \\r
- ((MODE) == TIM_OPMODE_REPETITIVE))\r
-\r
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \\r
- ((MODE) == TIM_ENCODERMODE_TI2) || \\r
- ((MODE) == TIM_ENCODERMODE_TI12)) \r
-\r
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))\r
-\r
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))\r
-\r
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \\r
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \\r
- ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \\r
- ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \\r
- ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \\r
- ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \\r
- ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \\r
- ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \\r
- ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \\r
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))\r
-\r
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \\r
- ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \\r
- ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \\r
- ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \\r
- ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))\r
-\r
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \\r
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \\r
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \\r
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) \r
-\r
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) \r
-\r
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \\r
- ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))\r
-\r
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\r
- ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\r
-\r
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \\r
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \\r
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \\r
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))\r
-\r
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)\r
-\r
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \\r
- ((STATE) == TIM_OSSR_DISABLE))\r
-\r
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \\r
- ((STATE) == TIM_OSSI_DISABLE))\r
-\r
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \\r
- ((LEVEL) == TIM_LOCKLEVEL_1) || \\r
- ((LEVEL) == TIM_LOCKLEVEL_2) || \\r
- ((LEVEL) == TIM_LOCKLEVEL_3))\r
-\r
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \\r
- ((STATE) == TIM_BREAK_DISABLE))\r
-\r
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \\r
- ((POLARITY) == TIM_BREAKPOLARITY_HIGH))\r
-\r
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \\r
- ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))\r
-\r
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \\r
- ((SOURCE) == TIM_TRGO_ENABLE) || \\r
- ((SOURCE) == TIM_TRGO_UPDATE) || \\r
- ((SOURCE) == TIM_TRGO_OC1) || \\r
- ((SOURCE) == TIM_TRGO_OC1REF) || \\r
- ((SOURCE) == TIM_TRGO_OC2REF) || \\r
- ((SOURCE) == TIM_TRGO_OC3REF) || \\r
- ((SOURCE) == TIM_TRGO_OC4REF))\r
-\r
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \\r
- ((MODE) == TIM_SLAVEMODE_GATED) || \\r
- ((MODE) == TIM_SLAVEMODE_RESET) || \\r
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \\r
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1))\r
-\r
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \\r
- ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))\r
-\r
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
- ((SELECTION) == TIM_TS_ITR1) || \\r
- ((SELECTION) == TIM_TS_ITR2) || \\r
- ((SELECTION) == TIM_TS_ITR3) || \\r
- ((SELECTION) == TIM_TS_TI1F_ED) || \\r
- ((SELECTION) == TIM_TS_TI1FP1) || \\r
- ((SELECTION) == TIM_TS_TI2FP2) || \\r
- ((SELECTION) == TIM_TS_ETRF))\r
-\r
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
- ((SELECTION) == TIM_TS_ITR1) || \\r
- ((SELECTION) == TIM_TS_ITR2) || \\r
- ((SELECTION) == TIM_TS_ITR3) || \\r
- ((SELECTION) == TIM_TS_NONE))\r
-\r
-#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \\r
- ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\r
- ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \\r
- ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \\r
- ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))\r
-\r
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \\r
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \\r
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \\r
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))\r
-\r
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)\r
-\r
-#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \\r
- ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))\r
-\r
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \\r
- ((BASE) == TIM_DMABASE_CR2) || \\r
- ((BASE) == TIM_DMABASE_SMCR) || \\r
- ((BASE) == TIM_DMABASE_DIER) || \\r
- ((BASE) == TIM_DMABASE_SR) || \\r
- ((BASE) == TIM_DMABASE_EGR) || \\r
- ((BASE) == TIM_DMABASE_CCMR1) || \\r
- ((BASE) == TIM_DMABASE_CCMR2) || \\r
- ((BASE) == TIM_DMABASE_CCER) || \\r
- ((BASE) == TIM_DMABASE_CNT) || \\r
- ((BASE) == TIM_DMABASE_PSC) || \\r
- ((BASE) == TIM_DMABASE_ARR) || \\r
- ((BASE) == TIM_DMABASE_RCR) || \\r
- ((BASE) == TIM_DMABASE_CCR1) || \\r
- ((BASE) == TIM_DMABASE_CCR2) || \\r
- ((BASE) == TIM_DMABASE_CCR3) || \\r
- ((BASE) == TIM_DMABASE_CCR4) || \\r
- ((BASE) == TIM_DMABASE_BDTR) || \\r
- ((BASE) == TIM_DMABASE_DCR))\r
-\r
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\r
- ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))\r
-\r
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)\r
-\r
-/** @brief Set TIM IC prescaler\r
- * @param __HANDLE__: TIM handle\r
- * @param __CHANNEL__: specifies TIM Channel\r
- * @param __ICPSC__: specifies the prescaler value.\r
- * @retval None\r
- */\r
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\r
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))\r
-\r
-/** @brief Reset TIM IC prescaler\r
- * @param __HANDLE__: TIM handle\r
- * @param __CHANNEL__: specifies TIM Channel\r
- * @retval None\r
- */\r
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\r
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\\r
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))\r
-\r
-\r
-/** @brief Set TIM IC polarity\r
- * @param __HANDLE__: TIM handle\r
- * @param __CHANNEL__: specifies TIM Channel\r
- * @param __POLARITY__: specifies TIM Channel Polarity\r
- * @retval None\r
- */\r
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\\r
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))\r
-\r
-/** @brief Reset TIM IC polarity\r
- * @param __HANDLE__: TIM handle\r
- * @param __CHANNEL__: specifies TIM Channel\r
- * @retval None\r
- */\r
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\r
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\r
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private Functions --------------------------------------------------------*/\r
-/** @addtogroup TIM_Private_Functions\r
- * @{\r
- */\r
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\r
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\r
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\r
-void TIM_DMAError(DMA_HandleTypeDef *hdma);\r
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\r
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-/** @defgroup TIM_Exported_Macros TIM Exported Macros\r
- * @{\r
- */\r
-\r
-/** @brief Reset TIM handle state\r
- * @param __HANDLE__: TIM handle.\r
- * @retval None\r
- */\r
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)\r
-\r
-/**\r
- * @brief Enable the TIM peripheral.\r
- * @param __HANDLE__: TIM handle\r
- * @retval None\r
- */\r
-#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\r
-\r
-/**\r
- * @brief Enable the TIM main Output.\r
- * @param __HANDLE__: TIM handle\r
- * @retval None\r
- */\r
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))\r
-\r
-/**\r
- * @brief Disable the TIM peripheral.\r
- * @param __HANDLE__: TIM handle\r
- * @retval None\r
- */\r
-#define __HAL_TIM_DISABLE(__HANDLE__) \\r
- do { \\r
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \\r
- { \\r
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \\r
- { \\r
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\r
- } \\r
- } \\r
- } while(0U)\r
-/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN\r
- channels have been disabled */\r
-/**\r
- * @brief Disable the TIM main Output.\r
- * @param __HANDLE__: TIM handle\r
- * @retval None\r
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled\r
- */\r
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \\r
- do { \\r
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \\r
- { \\r
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \\r
- { \\r
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \\r
- } \\r
- } \\r
- } while(0U)\r
-\r
-/**\r
- * @brief Disable the TIM main Output.\r
- * @param __HANDLE__: TIM handle\r
- * @retval None\r
- * @note The Main Output Enable of a timer instance is disabled unconditionally\r
- */\r
-#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)\r
-\r
-/**\r
- * @brief Enables the specified TIM interrupt.\r
- * @param __HANDLE__: specifies the TIM Handle.\r
- * @param __INTERRUPT__: specifies the TIM interrupt source to enable.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_IT_UPDATE: Update interrupt\r
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
- * @arg TIM_IT_COM: Commutation interrupt\r
- * @arg TIM_IT_TRIGGER: Trigger interrupt\r
- * @arg TIM_IT_BREAK: Break interrupt\r
- * @retval None\r
- */\r
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\r
-\r
-/**\r
- * @brief Disables the specified TIM interrupt.\r
- * @param __HANDLE__: specifies the TIM Handle.\r
- * @param __INTERRUPT__: specifies the TIM interrupt source to disable.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_IT_UPDATE: Update interrupt\r
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
- * @arg TIM_IT_COM: Commutation interrupt\r
- * @arg TIM_IT_TRIGGER: Trigger interrupt\r
- * @arg TIM_IT_BREAK: Break interrupt\r
- * @retval None\r
- */\r
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\r
-\r
-/**\r
- * @brief Enables the specified DMA request.\r
- * @param __HANDLE__: specifies the TIM Handle.\r
- * @param __DMA__: specifies the TIM DMA request to enable.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMA_UPDATE: Update DMA request\r
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request\r
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request\r
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request\r
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request\r
- * @arg TIM_DMA_COM: Commutation DMA request\r
- * @arg TIM_DMA_TRIGGER: Trigger DMA request\r
- * @retval None\r
- */\r
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))\r
-\r
-/**\r
- * @brief Disables the specified DMA request.\r
- * @param __HANDLE__: specifies the TIM Handle.\r
- * @param __DMA__: specifies the TIM DMA request to disable.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMA_UPDATE: Update DMA request\r
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request\r
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request\r
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request\r
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request\r
- * @arg TIM_DMA_COM: Commutation DMA request\r
- * @arg TIM_DMA_TRIGGER: Trigger DMA request\r
- * @retval None\r
- */\r
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\r
-\r
-/**\r
- * @brief Checks whether the specified TIM interrupt flag is set or not.\r
- * @param __HANDLE__: specifies the TIM Handle.\r
- * @param __FLAG__: specifies the TIM interrupt flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_FLAG_UPDATE: Update interrupt flag\r
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
- * @arg TIM_FLAG_COM: Commutation interrupt flag\r
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
- * @arg TIM_FLAG_BREAK: Break interrupt flag \r
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
- * @retval The new state of __FLAG__ (TRUE or FALSE).\r
- */\r
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\r
-\r
-/**\r
- * @brief Clears the specified TIM interrupt flag.\r
- * @param __HANDLE__: specifies the TIM Handle.\r
- * @param __FLAG__: specifies the TIM interrupt flag to clear.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_FLAG_UPDATE: Update interrupt flag\r
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
- * @arg TIM_FLAG_COM: Commutation interrupt flag\r
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
- * @arg TIM_FLAG_BREAK: Break interrupt flag \r
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
- * @retval The new state of __FLAG__ (TRUE or FALSE).\r
- */\r
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r
-\r
-/**\r
- * @brief Checks whether the specified TIM interrupt has occurred or not.\r
- * @param __HANDLE__: TIM handle\r
- * @param __INTERRUPT__: specifies the TIM interrupt source to check.\r
- * @retval The state of TIM_IT (SET or RESET).\r
- */\r
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
-\r
-/**\r
- * @brief Clear the TIM interrupt pending bits\r
- * @param __HANDLE__: TIM handle\r
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.\r
- * @retval None\r
- */\r
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\r
-\r
-/**\r
- * @brief Indicates whether or not the TIM Counter is used as downcounter\r
- * @param __HANDLE__: TIM handle.\r
- * @retval False (Counter used as upcounter) or True (Counter used as downcounter)\r
- * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder\r
-mode.\r
- */\r
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))\r
-\r
-/**\r
- * @brief Sets the TIM active prescaler register value on update event.\r
- * @param __HANDLE__: TIM handle.\r
- * @param __PRESC__: specifies the active prescaler register new value.\r
- * @retval None\r
- */\r
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))\r
-\r
-/**\r
- * @brief Sets the TIM Capture Compare Register value on runtime without\r
- * calling another time ConfigChannel function.\r
- * @param __HANDLE__: TIM handle.\r
- * @param __CHANNEL__ : TIM Channels to be configured.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @param __COMPARE__: specifies the Capture Compare register new value.\r
- * @retval None\r
- */\r
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\r
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))\r
-\r
-/**\r
- * @brief Gets the TIM Capture Compare Register value on runtime\r
- * @param __HANDLE__: TIM handle.\r
- * @param __CHANNEL__ : TIM Channel associated with the capture compare register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value\r
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value\r
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value\r
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value\r
- * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)\r
- */\r
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\r
- (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))\r
-\r
-/**\r
- * @brief Sets the TIM Counter Register value on runtime.\r
- * @param __HANDLE__: TIM handle.\r
- * @param __COUNTER__: specifies the Counter register new value.\r
- * @retval None\r
- */\r
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))\r
-\r
-/**\r
- * @brief Gets the TIM Counter Register value on runtime.\r
- * @param __HANDLE__: TIM handle.\r
- * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)\r
- */\r
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \\r
- ((__HANDLE__)->Instance->CNT)\r
-\r
-/**\r
- * @brief Sets the TIM Autoreload Register value on runtime without calling\r
- * another time any Init function.\r
- * @param __HANDLE__: TIM handle.\r
- * @param __AUTORELOAD__: specifies the Counter register new value.\r
- * @retval None\r
- */\r
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \\r
- do{ \\r
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \\r
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \\r
- } while(0U)\r
-\r
-/**\r
- * @brief Gets the TIM Autoreload Register value on runtime\r
- * @param __HANDLE__: TIM handle.\r
- * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)\r
- */\r
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \\r
- ((__HANDLE__)->Instance->ARR)\r
-\r
-/**\r
- * @brief Sets the TIM Clock Division value on runtime without calling\r
- * another time any Init function.\r
- * @param __HANDLE__: TIM handle.\r
- * @param __CKD__: specifies the clock division value.\r
- * This parameter can be one of the following value:\r
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT \r
- * @retval None\r
- */\r
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\r
- do{ \\r
- (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \\r
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \\r
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \\r
- } while(0U)\r
-\r
-/**\r
- * @brief Gets the TIM Clock Division value on runtime\r
- * @param __HANDLE__: TIM handle.\r
- * @retval The clock division can be one of the following values:\r
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT \r
- */\r
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \\r
- ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\r
-\r
-/**\r
- * @brief Sets the TIM Input Capture prescaler on runtime without calling\r
- * another time HAL_TIM_IC_ConfigChannel() function.\r
- * @param __HANDLE__: TIM handle.\r
- * @param __CHANNEL__ : TIM Channels to be configured.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @param __ICPSC__: specifies the Input Capture4 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
- do{ \\r
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \\r
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\r
- } while(0U)\r
-\r
-/**\r
- * @brief Gets the TIM Input Capture prescaler on runtime\r
- * @param __HANDLE__: TIM handle.\r
- * @param __CHANNEL__: TIM Channels to be configured.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: get input capture 1 prescaler value\r
- * @arg TIM_CHANNEL_2: get input capture 2 prescaler value\r
- * @arg TIM_CHANNEL_3: get input capture 3 prescaler value\r
- * @arg TIM_CHANNEL_4: get input capture 4 prescaler value\r
- * @retval The input capture prescaler can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- */\r
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \\r
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\r
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)\r
-\r
-/**\r
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register\r
- * @param __HANDLE__: TIM handle.\r
- * @note When the USR bit of the TIMx_CR1 register is set, only counter\r
- * overflow/underflow generates an update interrupt or DMA request (if\r
- * enabled)\r
- * @retval None\r
- */\r
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \\r
- ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))\r
-\r
-/**\r
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register\r
- * @param __HANDLE__: TIM handle.\r
- * @note When the USR bit of the TIMx_CR1 register is reset, any of the\r
- * following events generate an update interrupt or DMA request (if\r
- * enabled):\r
- * (+) Counter overflow/underflow\r
- * (+) Setting the UG bit\r
- * (+) Update generation through the slave mode controller\r
- * @retval None\r
- */\r
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \\r
- ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))\r
-\r
-/**\r
- * @brief Sets the TIM Capture x input polarity on runtime.\r
- * @param __HANDLE__: TIM handle.\r
- * @param __CHANNEL__: TIM Channels to be configured.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @param __POLARITY__: Polarity for TIx source \r
- * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\r
- * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\r
- * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\r
- * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. \r
- * @retval None\r
- */\r
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
- do{ \\r
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \\r
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\r
- }while(0U)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Include TIM HAL Extension module */\r
-#include "stm32f1xx_hal_tim_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup TIM_Exported_Functions\r
- * @{\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group1\r
- * @{\r
- */\r
-/* Time Base functions ********************************************************/\r
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group2\r
- * @{\r
- */\r
-/* Timer Output Compare functions **********************************************/\r
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group3\r
- * @{\r
- */\r
-/* Timer PWM functions *********************************************************/\r
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group4\r
- * @{\r
- */\r
-/* Timer Input Capture functions ***********************************************/\r
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group5\r
- * @{\r
- */\r
-/* Timer One Pulse functions ***************************************************/\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group6\r
- * @{\r
- */\r
-/* Timer Encoder functions *****************************************************/\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);\r
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\r
- /* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group7\r
- * @{\r
- */\r
-/* Interrupt Handler functions **********************************************/\r
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group8\r
- * @{\r
- */\r
-/* Control functions *********************************************************/\r
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);\r
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);\r
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\r
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);\r
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\r
- uint32_t *BurstBuffer, uint32_t BurstLength);\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\r
- uint32_t *BurstBuffer, uint32_t BurstLength);\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\r
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group9\r
- * @{\r
- */\r
-/* Callback in non blocking modes (Interrupt and DMA) *************************/\r
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Exported_Functions_Group10\r
- * @{\r
- */\r
-/* Peripheral State functions **************************************************/\r
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\r
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_TIM_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_tim_ex.h\r
- * @author MCD Application Team\r
- * @brief Header file of TIM HAL Extension module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_TIM_EX_H\r
-#define __STM32F1xx_HAL_TIM_EX_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal_def.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup TIMEx\r
- * @{\r
- */ \r
-\r
-/* Exported types ------------------------------------------------------------*/ \r
-/** @defgroup TIMEx_Exported_Types TIMEx Exported Types\r
- * @{\r
- */\r
-\r
-\r
-/** \r
- * @brief TIM Hall sensor Configuration Structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
-\r
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.\r
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.\r
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
- uint32_t IC1Filter; /*!< Specifies the input capture filter.\r
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ \r
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
-} TIM_HallSensor_InitTypeDef;\r
-\r
-\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-\r
-/** \r
- * @brief TIM Break and Dead time configuration Structure definition \r
- */ \r
-typedef struct\r
-{\r
- uint32_t OffStateRunMode; /*!< TIM off state in run mode\r
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode\r
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r
- uint32_t LockLevel; /*!< TIM Lock level\r
- This parameter can be a value of @ref TIM_Lock_level */ \r
- uint32_t DeadTime; /*!< TIM dead Time \r
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
- uint32_t BreakState; /*!< TIM Break State \r
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r
- uint32_t BreakPolarity; /*!< TIM Break input polarity \r
- This parameter can be a value of @ref TIM_Break_Polarity */\r
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state \r
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ \r
-} TIM_BreakDeadTimeConfigTypeDef;\r
-\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-\r
-/** \r
- * @brief TIM Master configuration Structure definition \r
- */ \r
-typedef struct {\r
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection \r
- This parameter can be a value of @ref TIM_Master_Mode_Selection */ \r
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection \r
- This parameter can be a value of @ref TIM_Master_Slave_Mode */\r
-}TIM_MasterConfigTypeDef;\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants\r
- * @{\r
- */\r
- \r
-/** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter\r
- * @{\r
- */\r
-#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/**\r
- * @brief Sets the TIM Output compare preload.\r
- * @param __HANDLE__: TIM handle.\r
- * @param __CHANNEL__: TIM Channels to be configured.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval None\r
- */\r
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \\r
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\\r
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))\r
-\r
-/**\r
- * @brief Resets the TIM Output compare preload.\r
- * @param __HANDLE__: TIM handle.\r
- * @param __CHANNEL__: TIM Channels to be configured.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval None\r
- */\r
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \\r
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\\r
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\\r
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup TIMEx_Exported_Functions\r
- * @{\r
- */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group1\r
- * @{\r
- */\r
-/* Timer Hall Sensor functions **********************************************/\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);\r
-\r
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);\r
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);\r
-\r
- /* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group2\r
- * @{\r
- */\r
-/* Timer Complementary Output Compare functions *****************************/\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group3\r
- * @{\r
- */\r
-/* Timer Complementary PWM functions ****************************************/\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/* Non-Blocking mode: DMA */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group4\r
- * @{\r
- */\r
-/* Timer Complementary One Pulse functions **********************************/\r
-/* Blocking mode: Polling */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-\r
-/* Non-Blocking mode: Interrupt */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
-/**\r
- * @}\r
- */\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group5\r
- * @{\r
- */\r
-/* Extended Control functions ************************************************/\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIMEx_Exported_Functions_Group6\r
- * @{\r
- */\r
-/* Extension Callback *********************************************************/\r
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);\r
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-/** @addtogroup TIMEx_Exported_Functions_Group7\r
- * @{\r
- */\r
-/* Extension Peripheral State functions **************************************/\r
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);\r
-/**\r
- * @}\r
- */\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-\r
-/**\r
- * @}\r
- */ \r
-/* End of exported functions -------------------------------------------------*/\r
-\r
-/* Private functions----------------------------------------------------------*/\r
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions\r
-* @{\r
-*/\r
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r
-/**\r
-* @}\r
-*/ \r
-/* End of private functions --------------------------------------------------*/\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
- \r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* __STM32F1xx_HAL_TIM_EX_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal.c\r
- * @author MCD Application Team\r
- * @brief HAL module driver.\r
- * This is the common part of the HAL initialization\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..]\r
- The common HAL driver contains a set of generic and common APIs that can be\r
- used by the PPP peripheral drivers and the user to start using the HAL.\r
- [..]\r
- The HAL contains two APIs' categories:\r
- (+) Common HAL APIs\r
- (+) Services HAL APIs\r
-\r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup HAL HAL\r
- * @brief HAL module driver.\r
- * @{\r
- */\r
-\r
-#ifdef HAL_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_Private_Constants HAL Private Constants\r
- * @{\r
- */\r
-/**\r
- * @brief STM32F1xx HAL Driver version number V1.1.3\r
- */\r
-#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */\r
-#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */\r
-#define __STM32F1xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */\r
-#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */\r
-#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\\r
- |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\\r
- |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\\r
- |(__STM32F1xx_HAL_VERSION_RC))\r
-\r
-#define IDCODE_DEVID_MASK 0x00000FFFU\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_Private_Variables HAL Private Variables\r
- * @{\r
- */\r
-__IO uint32_t uwTick;\r
-uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */\r
-HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */\r
-/**\r
- * @}\r
- */\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Exported functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_Exported_Functions HAL Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions\r
- * @brief Initialization and de-initialization functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to:\r
- (+) Initializes the Flash interface, the NVIC allocation and initial clock\r
- configuration. It initializes the systick also when timeout is needed\r
- and the backup domain when enabled.\r
- (+) de-Initializes common part of the HAL.\r
- (+) Configure The time base source to have 1ms time base with a dedicated\r
- Tick interrupt priority.\r
- (++) SysTick timer is used by default as source of time base, but user\r
- can eventually implement his proper time base source (a general purpose\r
- timer for example or other time source), keeping in mind that Time base\r
- duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and\r
- handled in milliseconds basis.\r
- (++) Time base configuration function (HAL_InitTick ()) is called automatically\r
- at the beginning of the program after reset by HAL_Init() or at any time\r
- when clock is configured, by HAL_RCC_ClockConfig().\r
- (++) Source of time base is configured to generate interrupts at regular\r
- time intervals. Care must be taken if HAL_Delay() is called from a\r
- peripheral ISR process, the Tick interrupt line must have higher priority\r
- (numerically lower) than the peripheral interrupt. Otherwise the caller\r
- ISR process will be blocked.\r
- (++) functions affecting time base configurations are declared as __weak\r
- to make override possible in case of other implementations in user file.\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief This function is used to initialize the HAL Library; it must be the first\r
- * instruction to be executed in the main program (before to call any other\r
- * HAL function), it performs the following:\r
- * Configure the Flash prefetch.\r
- * Configures the SysTick to generate an interrupt each 1 millisecond,\r
- * which is clocked by the HSI (at this stage, the clock is not yet\r
- * configured and thus the system is running from the internal HSI at 16 MHz).\r
- * Set NVIC Group Priority to 4.\r
- * Calls the HAL_MspInit() callback function defined in user file\r
- * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization\r
- *\r
- * @note SysTick is used as time base for the HAL_Delay() function, the application\r
- * need to ensure that the SysTick time base is always set to 1 millisecond\r
- * to have correct HAL operation.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_Init(void)\r
-{\r
- /* Configure Flash prefetch */\r
-#if (PREFETCH_ENABLE != 0)\r
-#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \\r
- defined(STM32F102x6) || defined(STM32F102xB) || \\r
- defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \\r
- defined(STM32F105xC) || defined(STM32F107xC)\r
-\r
- /* Prefetch buffer is not available on value line devices */\r
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();\r
-#endif\r
-#endif /* PREFETCH_ENABLE */\r
-\r
- /* Set Interrupt Group Priority */\r
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r
-\r
- /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */\r
- HAL_InitTick(TICK_INT_PRIORITY);\r
-\r
- /* Init the low level hardware */\r
- HAL_MspInit();\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief This function de-Initializes common part of the HAL and stops the systick.\r
- * of time base.\r
- * @note This function is optional.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_DeInit(void)\r
-{\r
- /* Reset of all peripherals */\r
- __HAL_RCC_APB1_FORCE_RESET();\r
- __HAL_RCC_APB1_RELEASE_RESET();\r
-\r
- __HAL_RCC_APB2_FORCE_RESET();\r
- __HAL_RCC_APB2_RELEASE_RESET();\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- __HAL_RCC_AHB_FORCE_RESET();\r
- __HAL_RCC_AHB_RELEASE_RESET();\r
-#endif\r
-\r
- /* De-Init the low level hardware */\r
- HAL_MspDeInit();\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initialize the MSP.\r
- * @retval None\r
- */\r
-__weak void HAL_MspInit(void)\r
-{\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_MspInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief DeInitializes the MSP.\r
- * @retval None\r
- */\r
-__weak void HAL_MspDeInit(void)\r
-{\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_MspDeInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief This function configures the source of the time base.\r
- * The time source is configured to have 1ms time base with a dedicated\r
- * Tick interrupt priority.\r
- * @note This function is called automatically at the beginning of program after\r
- * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().\r
- * @note In the default implementation, SysTick timer is the source of time base.\r
- * It is used to generate interrupts at regular time intervals.\r
- * Care must be taken if HAL_Delay() is called from a peripheral ISR process,\r
- * The SysTick interrupt must have higher priority (numerically lower)\r
- * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r
- * The function is declared as __weak to be overwritten in case of other\r
- * implementation in user file.\r
- * @param TickPriority Tick interrupt priority.\r
- * @retval HAL status\r
- */\r
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
-{\r
- /* Configure the SysTick to have interrupt in 1ms time basis*/\r
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Configure the SysTick IRQ priority */\r
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))\r
- {\r
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);\r
- uwTickPrio = TickPriority;\r
- }\r
- else\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions\r
- * @brief HAL Control functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### HAL Control functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to:\r
- (+) Provide a tick value in millisecond\r
- (+) Provide a blocking delay in millisecond\r
- (+) Suspend the time base source interrupt\r
- (+) Resume the time base source interrupt\r
- (+) Get the HAL API driver version\r
- (+) Get the device identifier\r
- (+) Get the device revision identifier\r
- (+) Enable/Disable Debug module during SLEEP mode\r
- (+) Enable/Disable Debug module during STOP mode\r
- (+) Enable/Disable Debug module during STANDBY mode\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief This function is called to increment a global variable "uwTick"\r
- * used as application time base.\r
- * @note In the default implementation, this variable is incremented each 1ms\r
- * in SysTick ISR.\r
- * @note This function is declared as __weak to be overwritten in case of other\r
- * implementations in user file.\r
- * @retval None\r
- */\r
-__weak void HAL_IncTick(void)\r
-{\r
- uwTick += uwTickFreq;\r
-}\r
-\r
-/**\r
- * @brief Provides a tick value in millisecond.\r
- * @note This function is declared as __weak to be overwritten in case of other\r
- * implementations in user file.\r
- * @retval tick value\r
- */\r
-__weak uint32_t HAL_GetTick(void)\r
-{\r
- return uwTick;\r
-}\r
-\r
-/**\r
- * @brief This function returns a tick priority.\r
- * @retval tick priority\r
- */\r
-uint32_t HAL_GetTickPrio(void)\r
-{\r
- return uwTickPrio;\r
-}\r
-\r
-/**\r
- * @brief Set new tick Freq.\r
- * @retval Status\r
- */\r
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- assert_param(IS_TICKFREQ(Freq));\r
-\r
- if (uwTickFreq != Freq)\r
- {\r
- uwTickFreq = Freq;\r
-\r
- /* Apply the new tick Freq */\r
- status = HAL_InitTick(uwTickPrio);\r
- }\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Return tick frequency.\r
- * @retval tick period in Hz\r
- */\r
-HAL_TickFreqTypeDef HAL_GetTickFreq(void)\r
-{\r
- return uwTickFreq;\r
-}\r
-\r
-/**\r
- * @brief This function provides minimum delay (in milliseconds) based\r
- * on variable incremented.\r
- * @note In the default implementation , SysTick timer is the source of time base.\r
- * It is used to generate interrupts at regular time intervals where uwTick\r
- * is incremented.\r
- * @note This function is declared as __weak to be overwritten in case of other\r
- * implementations in user file.\r
- * @param Delay specifies the delay time length, in milliseconds.\r
- * @retval None\r
- */\r
-__weak void HAL_Delay(uint32_t Delay)\r
-{\r
- uint32_t tickstart = HAL_GetTick();\r
- uint32_t wait = Delay;\r
-\r
- /* Add a freq to guarantee minimum wait */\r
- if (wait < HAL_MAX_DELAY)\r
- {\r
- wait += (uint32_t)(uwTickFreq);\r
- }\r
-\r
- while ((HAL_GetTick() - tickstart) < wait)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief Suspend Tick increment.\r
- * @note In the default implementation , SysTick timer is the source of time base. It is\r
- * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r
- * is called, the SysTick interrupt will be disabled and so Tick increment\r
- * is suspended.\r
- * @note This function is declared as __weak to be overwritten in case of other\r
- * implementations in user file.\r
- * @retval None\r
- */\r
-__weak void HAL_SuspendTick(void)\r
-{\r
- /* Disable SysTick Interrupt */\r
- CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);\r
-}\r
-\r
-/**\r
- * @brief Resume Tick increment.\r
- * @note In the default implementation , SysTick timer is the source of time base. It is\r
- * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r
- * is called, the SysTick interrupt will be enabled and so Tick increment\r
- * is resumed.\r
- * @note This function is declared as __weak to be overwritten in case of other\r
- * implementations in user file.\r
- * @retval None\r
- */\r
-__weak void HAL_ResumeTick(void)\r
-{\r
- /* Enable SysTick Interrupt */\r
- SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);\r
-}\r
-\r
-/**\r
- * @brief Returns the HAL revision\r
- * @retval version 0xXYZR (8bits for each decimal, R for RC)\r
- */\r
-uint32_t HAL_GetHalVersion(void)\r
-{\r
- return __STM32F1xx_HAL_VERSION;\r
-}\r
-\r
-/**\r
- * @brief Returns the device revision identifier.\r
- * Note: On devices STM32F10xx8 and STM32F10xxB,\r
- * STM32F101xC/D/E and STM32F103xC/D/E,\r
- * STM32F101xF/G and STM32F103xF/G\r
- * STM32F10xx4 and STM32F10xx6\r
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in\r
- * debug mode (not accessible by the user software in normal mode).\r
- * Refer to errata sheet of these devices for more details.\r
- * @retval Device revision identifier\r
- */\r
-uint32_t HAL_GetREVID(void)\r
-{\r
- return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos);\r
-}\r
-\r
-/**\r
- * @brief Returns the device identifier.\r
- * Note: On devices STM32F10xx8 and STM32F10xxB,\r
- * STM32F101xC/D/E and STM32F103xC/D/E,\r
- * STM32F101xF/G and STM32F103xF/G\r
- * STM32F10xx4 and STM32F10xx6\r
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in\r
- * debug mode (not accessible by the user software in normal mode).\r
- * Refer to errata sheet of these devices for more details.\r
- * @retval Device identifier\r
- */\r
-uint32_t HAL_GetDEVID(void)\r
-{\r
- return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\r
-}\r
-\r
-/**\r
- * @brief Enable the Debug Module during SLEEP mode\r
- * @retval None\r
- */\r
-void HAL_DBGMCU_EnableDBGSleepMode(void)\r
-{\r
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
-}\r
-\r
-/**\r
- * @brief Disable the Debug Module during SLEEP mode\r
- * Note: On devices STM32F10xx8 and STM32F10xxB,\r
- * STM32F101xC/D/E and STM32F103xC/D/E,\r
- * STM32F101xF/G and STM32F103xF/G\r
- * STM32F10xx4 and STM32F10xx6\r
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in\r
- * debug mode (not accessible by the user software in normal mode).\r
- * Refer to errata sheet of these devices for more details.\r
- * @retval None\r
- */\r
-void HAL_DBGMCU_DisableDBGSleepMode(void)\r
-{\r
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
-}\r
-\r
-/**\r
- * @brief Enable the Debug Module during STOP mode\r
- * Note: On devices STM32F10xx8 and STM32F10xxB,\r
- * STM32F101xC/D/E and STM32F103xC/D/E,\r
- * STM32F101xF/G and STM32F103xF/G\r
- * STM32F10xx4 and STM32F10xx6\r
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in\r
- * debug mode (not accessible by the user software in normal mode).\r
- * Refer to errata sheet of these devices for more details.\r
- * Note: On all STM32F1 devices:\r
- * If the system tick timer interrupt is enabled during the Stop mode\r
- * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup\r
- * the system from Stop mode.\r
- * Workaround: To debug the Stop mode, disable the system tick timer\r
- * interrupt.\r
- * Refer to errata sheet of these devices for more details.\r
- * Note: On all STM32F1 devices:\r
- * If the system tick timer interrupt is enabled during the Stop mode\r
- * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup\r
- * the system from Stop mode.\r
- * Workaround: To debug the Stop mode, disable the system tick timer\r
- * interrupt.\r
- * Refer to errata sheet of these devices for more details.\r
- * @retval None\r
- */\r
-void HAL_DBGMCU_EnableDBGStopMode(void)\r
-{\r
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
-}\r
-\r
-/**\r
- * @brief Disable the Debug Module during STOP mode\r
- * Note: On devices STM32F10xx8 and STM32F10xxB,\r
- * STM32F101xC/D/E and STM32F103xC/D/E,\r
- * STM32F101xF/G and STM32F103xF/G\r
- * STM32F10xx4 and STM32F10xx6\r
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in\r
- * debug mode (not accessible by the user software in normal mode).\r
- * Refer to errata sheet of these devices for more details.\r
- * @retval None\r
- */\r
-void HAL_DBGMCU_DisableDBGStopMode(void)\r
-{\r
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
-}\r
-\r
-/**\r
- * @brief Enable the Debug Module during STANDBY mode\r
- * Note: On devices STM32F10xx8 and STM32F10xxB,\r
- * STM32F101xC/D/E and STM32F103xC/D/E,\r
- * STM32F101xF/G and STM32F103xF/G\r
- * STM32F10xx4 and STM32F10xx6\r
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in\r
- * debug mode (not accessible by the user software in normal mode).\r
- * Refer to errata sheet of these devices for more details.\r
- * @retval None\r
- */\r
-void HAL_DBGMCU_EnableDBGStandbyMode(void)\r
-{\r
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
-}\r
-\r
-/**\r
- * @brief Disable the Debug Module during STANDBY mode\r
- * Note: On devices STM32F10xx8 and STM32F10xxB,\r
- * STM32F101xC/D/E and STM32F103xC/D/E,\r
- * STM32F101xF/G and STM32F103xF/G\r
- * STM32F10xx4 and STM32F10xx6\r
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in\r
- * debug mode (not accessible by the user software in normal mode).\r
- * Refer to errata sheet of these devices for more details.\r
- * @retval None\r
- */\r
-void HAL_DBGMCU_DisableDBGStandbyMode(void)\r
-{\r
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
-}\r
-\r
-/**\r
- * @brief Return the unique device identifier (UID based on 96 bits)\r
- * @param UID pointer to 3 words array.\r
- * @retval Device identifier\r
- */\r
-void HAL_GetUID(uint32_t *UID)\r
-{\r
- UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));\r
- UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));\r
- UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_cortex.c\r
- * @author MCD Application Team\r
- * @brief CORTEX HAL module driver.\r
- * This file provides firmware functions to manage the following \r
- * functionalities of the CORTEX:\r
- * + Initialization and de-initialization functions\r
- * + Peripheral Control functions \r
- *\r
- @verbatim \r
- ==============================================================================\r
- ##### How to use this driver #####\r
- ==============================================================================\r
-\r
- [..] \r
- *** How to configure Interrupts using CORTEX HAL driver ***\r
- ===========================================================\r
- [..] \r
- This section provides functions allowing to configure the NVIC interrupts (IRQ).\r
- The Cortex-M3 exceptions are managed by CMSIS functions.\r
- \r
- (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()\r
- function according to the following table.\r
- (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). \r
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\r
- (#) please refer to programming manual for details in how to configure priority. \r
- \r
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. \r
- The pending IRQ priority will be managed only by the sub priority.\r
- \r
- -@- IRQ priority order (sorted by highest to lowest priority):\r
- (+@) Lowest preemption priority\r
- (+@) Lowest sub priority\r
- (+@) Lowest hardware priority (IRQ number)\r
- \r
- [..] \r
- *** How to configure Systick using CORTEX HAL driver ***\r
- ========================================================\r
- [..]\r
- Setup SysTick Timer for time base.\r
- \r
- (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which\r
- is a CMSIS function that:\r
- (++) Configures the SysTick Reload register with value passed as function parameter.\r
- (++) Configures the SysTick IRQ priority to the lowest value 0x0F.\r
- (++) Resets the SysTick Counter register.\r
- (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r
- (++) Enables the SysTick Interrupt.\r
- (++) Starts the SysTick Counter.\r
- \r
- (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r
- __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r
- HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\r
- inside the stm32f1xx_hal_cortex.h file.\r
-\r
- (+) You can change the SysTick IRQ priority by calling the\r
- HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function \r
- call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r
-\r
- (+) To adjust the SysTick time base, use the following formula:\r
- \r
- Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)\r
- (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r
- (++) Reload Value should not exceed 0xFFFFFF\r
- \r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup CORTEX CORTEX\r
- * @brief CORTEX HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_CORTEX_MODULE_ENABLED\r
-\r
-/* Private types -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private constants ---------------------------------------------------------*/\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r
- * @{\r
- */\r
-\r
-\r
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions\r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Initialization and de-initialization functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides the CORTEX HAL driver functions allowing to configure Interrupts\r
- Systick functionalities \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-\r
-/**\r
- * @brief Sets the priority grouping field (preemption priority and subpriority)\r
- * using the required unlock sequence.\r
- * @param PriorityGroup: The priority grouping bits length. \r
- * This parameter can be one of the following values:\r
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
- * 4 bits for subpriority\r
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
- * 3 bits for subpriority\r
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
- * 2 bits for subpriority\r
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
- * 1 bits for subpriority\r
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
- * 0 bits for subpriority\r
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. \r
- * The pending IRQ priority will be managed only by the subpriority. \r
- * @retval None\r
- */\r
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
- \r
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r
- NVIC_SetPriorityGrouping(PriorityGroup);\r
-}\r
-\r
-/**\r
- * @brief Sets the priority of an interrupt.\r
- * @param IRQn: External interrupt number.\r
- * This parameter can be an enumerator of IRQn_Type enumeration\r
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))\r
- * @param PreemptPriority: The preemption priority for the IRQn channel.\r
- * This parameter can be a value between 0 and 15\r
- * A lower priority value indicates a higher priority \r
- * @param SubPriority: the subpriority level for the IRQ channel.\r
- * This parameter can be a value between 0 and 15\r
- * A lower priority value indicates a higher priority. \r
- * @retval None\r
- */\r
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{ \r
- uint32_t prioritygroup = 0x00U;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r
- \r
- prioritygroup = NVIC_GetPriorityGrouping();\r
- \r
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r
-}\r
-\r
-/**\r
- * @brief Enables a device specific interrupt in the NVIC interrupt controller.\r
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
- * function should be called before. \r
- * @param IRQn External interrupt number.\r
- * This parameter can be an enumerator of IRQn_Type enumeration\r
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))\r
- * @retval None\r
- */\r
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
- /* Enable interrupt */\r
- NVIC_EnableIRQ(IRQn);\r
-}\r
-\r
-/**\r
- * @brief Disables a device specific interrupt in the NVIC interrupt controller.\r
- * @param IRQn External interrupt number.\r
- * This parameter can be an enumerator of IRQn_Type enumeration\r
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) \r
- * @retval None\r
- */\r
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
- /* Disable interrupt */\r
- NVIC_DisableIRQ(IRQn);\r
-}\r
-\r
-/**\r
- * @brief Initiates a system reset request to reset the MCU.\r
- * @retval None\r
- */\r
-void HAL_NVIC_SystemReset(void)\r
-{\r
- /* System Reset */\r
- NVIC_SystemReset();\r
-}\r
-\r
-/**\r
- * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- * Counter is in free running mode to generate periodic interrupts.\r
- * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.\r
- * @retval status: - 0 Function succeeded.\r
- * - 1 Function failed.\r
- */\r
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r
-{\r
- return SysTick_Config(TicksNumb);\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r
- * @brief Cortex control functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Peripheral Control functions #####\r
- ==============================================================================\r
- [..]\r
- This subsection provides a set of functions allowing to control the CORTEX\r
- (NVIC, SYSTICK, MPU) functionalities. \r
- \r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-/**\r
- * @brief Disables the MPU\r
- * @retval None\r
- */\r
-void HAL_MPU_Disable(void)\r
-{\r
- /* Make sure outstanding transfers are done */\r
- __DMB();\r
-\r
- /* Disable fault exceptions */\r
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
- \r
- /* Disable the MPU and clear the control register*/\r
- MPU->CTRL = 0U;\r
-}\r
-\r
-/**\r
- * @brief Enable the MPU.\r
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault, \r
- * NMI, FAULTMASK and privileged access to the default memory \r
- * This parameter can be one of the following values:\r
- * @arg MPU_HFNMI_PRIVDEF_NONE\r
- * @arg MPU_HARDFAULT_NMI\r
- * @arg MPU_PRIVILEGED_DEFAULT\r
- * @arg MPU_HFNMI_PRIVDEF\r
- * @retval None\r
- */\r
-void HAL_MPU_Enable(uint32_t MPU_Control)\r
-{\r
- /* Enable the MPU */\r
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
- \r
- /* Enable fault exceptions */\r
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
- \r
- /* Ensure MPU setting take effects */\r
- __DSB();\r
- __ISB();\r
-}\r
-\r
-/**\r
- * @brief Initializes and configures the Region and the memory to be protected.\r
- * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains\r
- * the initialization and configuration information.\r
- * @retval None\r
- */\r
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r
- assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r
-\r
- /* Set the Region number */\r
- MPU->RNR = MPU_Init->Number;\r
-\r
- if ((MPU_Init->Enable) != RESET)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r
- \r
- MPU->RBAR = MPU_Init->BaseAddress;\r
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |\r
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |\r
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |\r
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |\r
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |\r
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |\r
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |\r
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |\r
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);\r
- }\r
- else\r
- {\r
- MPU->RBAR = 0x00U;\r
- MPU->RASR = 0x00U;\r
- }\r
-}\r
-#endif /* __MPU_PRESENT */\r
-\r
-/**\r
- * @brief Gets the priority grouping field from the NVIC Interrupt Controller.\r
- * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r
- */\r
-uint32_t HAL_NVIC_GetPriorityGrouping(void)\r
-{\r
- /* Get the PRIGROUP[10:8] field value */\r
- return NVIC_GetPriorityGrouping();\r
-}\r
-\r
-/**\r
- * @brief Gets the priority of an interrupt.\r
- * @param IRQn: External interrupt number.\r
- * This parameter can be an enumerator of IRQn_Type enumeration\r
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))\r
- * @param PriorityGroup: the priority grouping bits length.\r
- * This parameter can be one of the following values:\r
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
- * 4 bits for subpriority\r
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
- * 3 bits for subpriority\r
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
- * 2 bits for subpriority\r
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
- * 1 bits for subpriority\r
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
- * 0 bits for subpriority\r
- * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).\r
- * @param pSubPriority: Pointer on the Subpriority value (starting from 0).\r
- * @retval None\r
- */\r
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
- /* Get priority for Cortex-M system or device specific interrupts */\r
- NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r
-}\r
-\r
-/**\r
- * @brief Sets Pending bit of an external interrupt.\r
- * @param IRQn External interrupt number\r
- * This parameter can be an enumerator of IRQn_Type enumeration\r
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) \r
- * @retval None\r
- */\r
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
- \r
- /* Set interrupt pending */\r
- NVIC_SetPendingIRQ(IRQn);\r
-}\r
-\r
-/**\r
- * @brief Gets Pending Interrupt (reads the pending register in the NVIC \r
- * and returns the pending bit for the specified interrupt).\r
- * @param IRQn External interrupt number.\r
- * This parameter can be an enumerator of IRQn_Type enumeration\r
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) \r
- * @retval status: - 0 Interrupt status is not pending.\r
- * - 1 Interrupt status is pending.\r
- */\r
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
- /* Return 1 if pending else 0 */\r
- return NVIC_GetPendingIRQ(IRQn);\r
-}\r
-\r
-/**\r
- * @brief Clears the pending bit of an external interrupt.\r
- * @param IRQn External interrupt number.\r
- * This parameter can be an enumerator of IRQn_Type enumeration\r
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) \r
- * @retval None\r
- */\r
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
- /* Clear pending interrupt */\r
- NVIC_ClearPendingIRQ(IRQn);\r
-}\r
-\r
-/**\r
- * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).\r
- * @param IRQn External interrupt number\r
- * This parameter can be an enumerator of IRQn_Type enumeration\r
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) \r
- * @retval status: - 0 Interrupt status is not pending.\r
- * - 1 Interrupt status is pending.\r
- */\r
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
-\r
- /* Return 1 if active else 0 */\r
- return NVIC_GetActive(IRQn);\r
-}\r
-\r
-/**\r
- * @brief Configures the SysTick clock source.\r
- * @param CLKSource: specifies the SysTick clock source.\r
- * This parameter can be one of the following values:\r
- * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r
- * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r
- * @retval None\r
- */\r
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r
- if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r
- {\r
- SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r
- }\r
- else\r
- {\r
- SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles SYSTICK interrupt request.\r
- * @retval None\r
- */\r
-void HAL_SYSTICK_IRQHandler(void)\r
-{\r
- HAL_SYSTICK_Callback();\r
-}\r
-\r
-/**\r
- * @brief SYSTICK callback.\r
- * @retval None\r
- */\r
-__weak void HAL_SYSTICK_Callback(void)\r
-{\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_SYSTICK_Callback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_CORTEX_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_dma.c\r
- * @author MCD Application Team\r
- * @brief DMA HAL module driver.\r
- * This file provides firmware functions to manage the following\r
- * functionalities of the Direct Memory Access (DMA) peripheral:\r
- * + Initialization and de-initialization functions\r
- * + IO operation functions\r
- * + Peripheral State and errors functions\r
- @verbatim\r
- ==============================================================================\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..]\r
- (#) Enable and configure the peripheral to be connected to the DMA Channel\r
- (except for internal SRAM / FLASH memories: no initialization is \r
- necessary). Please refer to the Reference manual for connection between peripherals\r
- and DMA requests.\r
-\r
- (#) For a given Channel, program the required configuration through the following parameters:\r
- Channel request, Transfer Direction, Source and Destination data formats,\r
- Circular or Normal mode, Channel Priority level, Source and Destination Increment mode\r
- using HAL_DMA_Init() function.\r
-\r
- (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error \r
- detection.\r
- \r
- (#) Use HAL_DMA_Abort() function to abort the current transfer\r
- \r
- -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.\r
- *** Polling mode IO operation ***\r
- =================================\r
- [..]\r
- (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source\r
- address and destination address and the Length of data to be transferred\r
- (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this\r
- case a fixed Timeout can be configured by User depending from his application.\r
-\r
- *** Interrupt mode IO operation ***\r
- ===================================\r
- [..]\r
- (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()\r
- (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of\r
- Source address and destination address and the Length of data to be transferred.\r
- In this case the DMA interrupt is configured\r
- (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r
- (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can\r
- add his own function by customization of function pointer XferCpltCallback and\r
- XferErrorCallback (i.e. a member of DMA handle structure).\r
-\r
- *** DMA HAL driver macros list ***\r
- ============================================= \r
- [..]\r
- Below the list of most used macros in DMA HAL driver.\r
-\r
- (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.\r
- (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.\r
- (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.\r
- (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.\r
- (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.\r
- (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.\r
- (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. \r
-\r
- [..] \r
- (@) You can refer to the DMA HAL driver header file for more useful macros \r
-\r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA DMA\r
- * @brief DMA HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_DMA_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup DMA_Private_Functions DMA Private Functions\r
- * @{\r
- */\r
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup DMA_Exported_Functions DMA Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r
- * @brief Initialization and de-initialization functions \r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
- [..]\r
- This section provides functions allowing to initialize the DMA Channel source\r
- and destination addresses, incrementation and data sizes, transfer direction, \r
- circular/normal mode selection, memory-to-memory mode selection and Channel priority value.\r
- [..]\r
- The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r
- reference manual. \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initialize the DMA according to the specified\r
- * parameters in the DMA_InitTypeDef and initialize the associated handle.\r
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r
-{\r
- uint32_t tmp = 0U;\r
-\r
- /* Check the DMA handle allocation */\r
- if(hdma == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
- assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r
- assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r
- assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r
- assert_param(IS_DMA_MODE(hdma->Init.Mode));\r
- assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r
-\r
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)\r
- /* calculation of the channel index */\r
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))\r
- {\r
- /* DMA1 */\r
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;\r
- hdma->DmaBaseAddress = DMA1;\r
- }\r
- else \r
- {\r
- /* DMA2 */\r
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;\r
- hdma->DmaBaseAddress = DMA2;\r
- }\r
-#else\r
- /* DMA1 */\r
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;\r
- hdma->DmaBaseAddress = DMA1;\r
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */\r
-\r
- /* Change DMA peripheral state */\r
- hdma->State = HAL_DMA_STATE_BUSY;\r
-\r
- /* Get the CR register value */\r
- tmp = hdma->Instance->CCR;\r
-\r
- /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
- tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \\r
- DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \\r
- DMA_CCR_DIR));\r
-\r
- /* Prepare the DMA Channel configuration */\r
- tmp |= hdma->Init.Direction |\r
- hdma->Init.PeriphInc | hdma->Init.MemInc |\r
- hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r
- hdma->Init.Mode | hdma->Init.Priority;\r
-\r
- /* Write to DMA Channel CR register */\r
- hdma->Instance->CCR = tmp;\r
-\r
- /* Initialise the error code */\r
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
-\r
- /* Initialize the DMA state*/\r
- hdma->State = HAL_DMA_STATE_READY;\r
- /* Allocate lock resource and initialize it */\r
- hdma->Lock = HAL_UNLOCKED;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief DeInitialize the DMA peripheral.\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r
-{\r
- /* Check the DMA handle allocation */\r
- if(hdma == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
-\r
- /* Disable the selected DMA Channelx */\r
- __HAL_DMA_DISABLE(hdma);\r
-\r
- /* Reset DMA Channel control register */\r
- hdma->Instance->CCR = 0U;\r
-\r
- /* Reset DMA Channel Number of Data to Transfer register */\r
- hdma->Instance->CNDTR = 0U;\r
-\r
- /* Reset DMA Channel peripheral address register */\r
- hdma->Instance->CPAR = 0U;\r
-\r
- /* Reset DMA Channel memory address register */\r
- hdma->Instance->CMAR = 0U;\r
-\r
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)\r
- /* calculation of the channel index */\r
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))\r
- {\r
- /* DMA1 */\r
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;\r
- hdma->DmaBaseAddress = DMA1;\r
- }\r
- else\r
- {\r
- /* DMA2 */\r
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;\r
- hdma->DmaBaseAddress = DMA2;\r
- }\r
-#else\r
- /* DMA1 */\r
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;\r
- hdma->DmaBaseAddress = DMA1;\r
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */\r
-\r
- /* Clear all flags */\r
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));\r
-\r
- /* Clean all callbacks */\r
- hdma->XferCpltCallback = NULL;\r
- hdma->XferHalfCpltCallback = NULL;\r
- hdma->XferErrorCallback = NULL;\r
- hdma->XferAbortCallback = NULL;\r
-\r
- /* Reset the error code */\r
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
-\r
- /* Reset the DMA state */\r
- hdma->State = HAL_DMA_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(hdma);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions\r
- * @brief Input and Output operation functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### IO operation functions #####\r
- ===============================================================================\r
- [..] This section provides functions allowing to:\r
- (+) Configure the source, destination address and data length and Start DMA transfer\r
- (+) Configure the source, destination address and data length and\r
- Start DMA transfer with interrupt\r
- (+) Abort DMA transfer\r
- (+) Poll for transfer complete\r
- (+) Handle DMA interrupt request\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Start the DMA Transfer.\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @param SrcAddress: The source memory Buffer address\r
- * @param DstAddress: The destination memory Buffer address\r
- * @param DataLength: The length of data to be transferred from source to destination\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hdma);\r
-\r
- if(HAL_DMA_STATE_READY == hdma->State)\r
- {\r
- /* Change DMA peripheral state */\r
- hdma->State = HAL_DMA_STATE_BUSY;\r
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
- \r
- /* Disable the peripheral */\r
- __HAL_DMA_DISABLE(hdma);\r
- \r
- /* Configure the source, destination address and the data length & clear flags*/\r
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
- \r
- /* Enable the Peripheral */\r
- __HAL_DMA_ENABLE(hdma);\r
- }\r
- else\r
- {\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hdma); \r
- status = HAL_BUSY;\r
- } \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Start the DMA Transfer with interrupt enabled.\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @param SrcAddress: The source memory Buffer address\r
- * @param DstAddress: The destination memory Buffer address\r
- * @param DataLength: The length of data to be transferred from source to destination\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hdma);\r
- \r
- if(HAL_DMA_STATE_READY == hdma->State)\r
- {\r
- /* Change DMA peripheral state */\r
- hdma->State = HAL_DMA_STATE_BUSY;\r
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
- \r
- /* Disable the peripheral */\r
- __HAL_DMA_DISABLE(hdma);\r
- \r
- /* Configure the source, destination address and the data length & clear flags*/\r
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
- \r
- /* Enable the transfer complete interrupt */\r
- /* Enable the transfer Error interrupt */\r
- if(NULL != hdma->XferHalfCpltCallback)\r
- {\r
- /* Enable the Half transfer complete interrupt as well */\r
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
- }\r
- else\r
- {\r
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));\r
- }\r
- /* Enable the Peripheral */\r
- __HAL_DMA_ENABLE(hdma);\r
- }\r
- else\r
- { \r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hdma); \r
-\r
- /* Remain BUSY */\r
- status = HAL_BUSY;\r
- } \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Abort the DMA Transfer.\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
-\r
- /* Disable DMA IT */\r
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
- \r
- /* Disable the channel */\r
- __HAL_DMA_DISABLE(hdma);\r
- \r
- /* Clear all flags */\r
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);\r
-\r
- /* Change the DMA state */\r
- hdma->State = HAL_DMA_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hdma); \r
- \r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Aborts the DMA Transfer in Interrupt mode.\r
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\r
-{ \r
- HAL_StatusTypeDef status = HAL_OK;\r
- \r
- if(HAL_DMA_STATE_BUSY != hdma->State)\r
- {\r
- /* no transfer ongoing */\r
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
- \r
- status = HAL_ERROR;\r
- }\r
- else\r
- { \r
- /* Disable DMA IT */\r
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
-\r
- /* Disable the channel */\r
- __HAL_DMA_DISABLE(hdma);\r
-\r
- /* Clear all flags */\r
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));\r
-\r
- /* Change the DMA state */\r
- hdma->State = HAL_DMA_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hdma);\r
-\r
- /* Call User Abort callback */\r
- if(hdma->XferAbortCallback != NULL)\r
- {\r
- hdma->XferAbortCallback(hdma);\r
- } \r
- }\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Polling for transfer complete.\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @param CompleteLevel: Specifies the DMA level complete.\r
- * @param Timeout: Timeout duration.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)\r
-{\r
- uint32_t temp;\r
- uint32_t tickstart = 0U;\r
-\r
- if(HAL_DMA_STATE_BUSY != hdma->State)\r
- {\r
- /* no transfer ongoing */\r
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
- __HAL_UNLOCK(hdma);\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Polling mode not supported in circular mode */\r
- if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))\r
- {\r
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
- return HAL_ERROR;\r
- }\r
- \r
- /* Get the level transfer complete flag */\r
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
- {\r
- /* Transfer Complete flag */\r
- temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);\r
- }\r
- else\r
- {\r
- /* Half Transfer Complete flag */\r
- temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);\r
- }\r
-\r
- /* Get tick */\r
- tickstart = HAL_GetTick();\r
-\r
- while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)\r
- {\r
- if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))\r
- {\r
- /* When a DMA transfer error occurs */\r
- /* A hardware clear of its EN bits is performed */\r
- /* Clear all flags */\r
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);\r
-\r
- /* Update error code */\r
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);\r
-\r
- /* Change the DMA state */\r
- hdma->State= HAL_DMA_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hdma);\r
-\r
- return HAL_ERROR;\r
- }\r
- /* Check for the Timeout */\r
- if(Timeout != HAL_MAX_DELAY)\r
- {\r
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))\r
- {\r
- /* Update error code */\r
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);\r
-\r
- /* Change the DMA state */\r
- hdma->State = HAL_DMA_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hdma);\r
-\r
- return HAL_ERROR;\r
- }\r
- }\r
- }\r
-\r
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
- {\r
- /* Clear the transfer complete flag */\r
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r
-\r
- /* The selected Channelx EN bit is cleared (DMA is disabled and\r
- all transfers are complete) */\r
- hdma->State = HAL_DMA_STATE_READY;\r
- }\r
- else\r
- {\r
- /* Clear the half transfer complete flag */\r
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
- }\r
- \r
- /* Process unlocked */\r
- __HAL_UNLOCK(hdma);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Handles DMA interrupt request.\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel. \r
- * @retval None\r
- */\r
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r
-{\r
- uint32_t flag_it = hdma->DmaBaseAddress->ISR;\r
- uint32_t source_it = hdma->Instance->CCR;\r
- \r
- /* Half Transfer Complete Interrupt management ******************************/\r
- if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))\r
- {\r
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
- {\r
- /* Disable the half transfer interrupt */\r
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
- }\r
- /* Clear the half transfer complete flag */\r
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
-\r
- /* DMA peripheral state is not updated in Half Transfer */\r
- /* but in Transfer Complete case */\r
-\r
- if(hdma->XferHalfCpltCallback != NULL)\r
- {\r
- /* Half transfer callback */\r
- hdma->XferHalfCpltCallback(hdma);\r
- }\r
- }\r
-\r
- /* Transfer Complete Interrupt management ***********************************/\r
- else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))\r
- {\r
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)\r
- {\r
- /* Disable the transfer complete and error interrupt */\r
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); \r
-\r
- /* Change the DMA state */\r
- hdma->State = HAL_DMA_STATE_READY;\r
- }\r
- /* Clear the transfer complete flag */\r
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hdma);\r
-\r
- if(hdma->XferCpltCallback != NULL)\r
- {\r
- /* Transfer complete callback */\r
- hdma->XferCpltCallback(hdma);\r
- }\r
- }\r
-\r
- /* Transfer Error Interrupt management **************************************/\r
- else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))\r
- {\r
- /* When a DMA transfer error occurs */\r
- /* A hardware clear of its EN bits is performed */\r
- /* Disable ALL DMA IT */\r
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
-\r
- /* Clear all flags */\r
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);\r
-\r
- /* Update error code */\r
- hdma->ErrorCode = HAL_DMA_ERROR_TE;\r
-\r
- /* Change the DMA state */\r
- hdma->State = HAL_DMA_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hdma);\r
-\r
- if (hdma->XferErrorCallback != NULL)\r
- {\r
- /* Transfer error callback */\r
- hdma->XferErrorCallback(hdma);\r
- }\r
- }\r
- return;\r
-}\r
-\r
-/**\r
- * @brief Register callbacks\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @param CallbackID: User Callback identifer\r
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
- * @param pCallback: pointer to private callbacsk function which has pointer to \r
- * a DMA_HandleTypeDef structure as parameter.\r
- * @retval HAL status\r
- */ \r
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hdma);\r
- \r
- if(HAL_DMA_STATE_READY == hdma->State)\r
- {\r
- switch (CallbackID)\r
- {\r
- case HAL_DMA_XFER_CPLT_CB_ID:\r
- hdma->XferCpltCallback = pCallback;\r
- break;\r
- \r
- case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
- hdma->XferHalfCpltCallback = pCallback;\r
- break; \r
-\r
- case HAL_DMA_XFER_ERROR_CB_ID:\r
- hdma->XferErrorCallback = pCallback;\r
- break; \r
- \r
- case HAL_DMA_XFER_ABORT_CB_ID:\r
- hdma->XferAbortCallback = pCallback;\r
- break; \r
- \r
- default:\r
- status = HAL_ERROR;\r
- break; \r
- }\r
- }\r
- else\r
- {\r
- status = HAL_ERROR;\r
- } \r
- \r
- /* Release Lock */\r
- __HAL_UNLOCK(hdma);\r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief UnRegister callbacks\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @param CallbackID: User Callback identifer\r
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
- * @retval HAL status\r
- */ \r
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hdma);\r
- \r
- if(HAL_DMA_STATE_READY == hdma->State)\r
- {\r
- switch (CallbackID)\r
- {\r
- case HAL_DMA_XFER_CPLT_CB_ID:\r
- hdma->XferCpltCallback = NULL;\r
- break;\r
-\r
- case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
- hdma->XferHalfCpltCallback = NULL;\r
- break; \r
-\r
- case HAL_DMA_XFER_ERROR_CB_ID:\r
- hdma->XferErrorCallback = NULL;\r
- break; \r
-\r
- case HAL_DMA_XFER_ABORT_CB_ID:\r
- hdma->XferAbortCallback = NULL;\r
- break; \r
-\r
- case HAL_DMA_XFER_ALL_CB_ID:\r
- hdma->XferCpltCallback = NULL;\r
- hdma->XferHalfCpltCallback = NULL;\r
- hdma->XferErrorCallback = NULL;\r
- hdma->XferAbortCallback = NULL;\r
- break; \r
-\r
- default:\r
- status = HAL_ERROR;\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_ERROR;\r
- } \r
- \r
- /* Release Lock */\r
- __HAL_UNLOCK(hdma);\r
- \r
- return status;\r
-}\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions\r
- * @brief Peripheral State and Errors functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Peripheral State and Errors functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection provides functions allowing to\r
- (+) Check the DMA state\r
- (+) Get error code\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Return the DMA hande state.\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @retval HAL state\r
- */\r
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r
-{\r
- /* Return DMA handle state */\r
- return hdma->State;\r
-}\r
-\r
-/**\r
- * @brief Return the DMA error code.\r
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @retval DMA Error Code\r
- */\r
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r
-{\r
- return hdma->ErrorCode;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup DMA_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the DMA Transfer parameter.\r
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA Channel.\r
- * @param SrcAddress: The source memory Buffer address\r
- * @param DstAddress: The destination memory Buffer address\r
- * @param DataLength: The length of data to be transferred from source to destination\r
- * @retval HAL status\r
- */\r
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
-{\r
- /* Clear all flags */\r
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);\r
-\r
- /* Configure DMA Channel data length */\r
- hdma->Instance->CNDTR = DataLength;\r
-\r
- /* Memory to Peripheral */\r
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
- {\r
- /* Configure DMA Channel destination address */\r
- hdma->Instance->CPAR = DstAddress;\r
-\r
- /* Configure DMA Channel source address */\r
- hdma->Instance->CMAR = SrcAddress;\r
- }\r
- /* Peripheral to Memory */\r
- else\r
- {\r
- /* Configure DMA Channel source address */\r
- hdma->Instance->CPAR = SrcAddress;\r
-\r
- /* Configure DMA Channel destination address */\r
- hdma->Instance->CMAR = DstAddress;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_DMA_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_flash.c\r
- * @author MCD Application Team\r
- * @brief FLASH HAL module driver.\r
- * This file provides firmware functions to manage the following \r
- * functionalities of the internal FLASH memory:\r
- * + Program operations functions\r
- * + Memory Control functions \r
- * + Peripheral State functions\r
- * \r
- @verbatim\r
- ==============================================================================\r
- ##### FLASH peripheral features #####\r
- ==============================================================================\r
- [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses \r
- to the Flash memory. It implements the erase and program Flash memory operations \r
- and the read and write protection mechanisms.\r
-\r
- [..] The Flash memory interface accelerates code execution with a system of instruction\r
- prefetch. \r
-\r
- [..] The FLASH main features are:\r
- (+) Flash memory read operations\r
- (+) Flash memory program/erase operations\r
- (+) Read / write protections\r
- (+) Prefetch on I-Code\r
- (+) Option Bytes programming\r
-\r
-\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..] \r
- This driver provides functions and macros to configure and program the FLASH \r
- memory of all STM32F1xx devices.\r
- \r
- (#) FLASH Memory I/O Programming functions: this group includes all needed\r
- functions to erase and program the main memory:\r
- (++) Lock and Unlock the FLASH interface\r
- (++) Erase function: Erase page, erase all pages\r
- (++) Program functions: half word, word and doubleword\r
- (#) FLASH Option Bytes Programming functions: this group includes all needed\r
- functions to manage the Option Bytes:\r
- (++) Lock and Unlock the Option Bytes\r
- (++) Set/Reset the write protection\r
- (++) Set the Read protection Level\r
- (++) Program the user Option Bytes\r
- (++) Launch the Option Bytes loader\r
- (++) Erase Option Bytes\r
- (++) Program the data Option Bytes\r
- (++) Get the Write protection.\r
- (++) Get the user option bytes.\r
- \r
- (#) Interrupts and flags management functions : this group \r
- includes all needed functions to:\r
- (++) Handle FLASH interrupts\r
- (++) Wait for last FLASH operation according to its status\r
- (++) Get error flag status\r
-\r
- [..] In addition to these function, this driver includes a set of macros allowing\r
- to handle the following operations:\r
- \r
- (+) Set/Get the latency\r
- (+) Enable/Disable the prefetch buffer\r
- (+) Enable/Disable the half cycle access\r
- (+) Enable/Disable the FLASH interrupts\r
- (+) Monitor the FLASH flags status\r
- \r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ****************************************************************************** \r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_FLASH_MODULE_ENABLED\r
-\r
-/** @defgroup FLASH FLASH\r
- * @brief FLASH HAL module driver\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @defgroup FLASH_Private_Constants FLASH Private Constants\r
- * @{\r
- */\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macro ---------------------------- ---------------------------------*/\r
-/** @defgroup FLASH_Private_Macros FLASH Private Macros\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/** @defgroup FLASH_Private_Variables FLASH Private Variables\r
- * @{\r
- */\r
-/* Variables used for Erase pages under interruption*/\r
-FLASH_ProcessTypeDef pFlash;\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup FLASH_Private_Functions FLASH Private Functions\r
- * @{\r
- */\r
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);\r
-static void FLASH_SetErrorCode(void);\r
-extern void FLASH_PageErase(uint32_t PageAddress);\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions ---------------------------------------------------------*/\r
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\r
- * @{\r
- */\r
- \r
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions \r
- * @brief Programming operation functions \r
- *\r
-@verbatim \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Program halfword, word or double word at a specified address\r
- * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface\r
- * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface\r
- *\r
- * @note If an erase and a program operations are requested simultaneously, \r
- * the erase operation is performed before the program one.\r
- * \r
- * @note FLASH should be previously erased before new programmation (only exception to this \r
- * is when 0x0000 is programmed)\r
- *\r
- * @param TypeProgram: Indicate the way to program at a specified address.\r
- * This parameter can be a value of @ref FLASH_Type_Program\r
- * @param Address: Specifies the address to be programmed.\r
- * @param Data: Specifies the data to be programmed\r
- * \r
- * @retval HAL_StatusTypeDef HAL Status\r
- */\r
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
- uint8_t index = 0;\r
- uint8_t nbiterations = 0;\r
- \r
- /* Process Locked */\r
- __HAL_LOCK(&pFlash);\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
-\r
-#if defined(FLASH_BANK2_END)\r
- if(Address <= FLASH_BANK1_END)\r
- {\r
-#endif /* FLASH_BANK2_END */\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
-#if defined(FLASH_BANK2_END)\r
- }\r
- else\r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);\r
- }\r
-#endif /* FLASH_BANK2_END */\r
- \r
- if(status == HAL_OK)\r
- {\r
- if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)\r
- {\r
- /* Program halfword (16-bit) at a specified address. */\r
- nbiterations = 1U;\r
- }\r
- else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)\r
- {\r
- /* Program word (32-bit = 2*16-bit) at a specified address. */\r
- nbiterations = 2U;\r
- }\r
- else\r
- {\r
- /* Program double word (64-bit = 4*16-bit) at a specified address. */\r
- nbiterations = 4U;\r
- }\r
-\r
- for (index = 0U; index < nbiterations; index++)\r
- {\r
- FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));\r
-\r
-#if defined(FLASH_BANK2_END)\r
- if(Address <= FLASH_BANK1_END)\r
- {\r
-#endif /* FLASH_BANK2_END */\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);\r
- \r
- /* If the program operation is completed, disable the PG Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_PG);\r
-#if defined(FLASH_BANK2_END)\r
- }\r
- else\r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);\r
- \r
- /* If the program operation is completed, disable the PG Bit */\r
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);\r
- }\r
-#endif /* FLASH_BANK2_END */\r
- /* In case of error, stop programation procedure */\r
- if (status != HAL_OK)\r
- {\r
- break;\r
- }\r
- }\r
- }\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(&pFlash);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Program halfword, word or double word at a specified address with interrupt enabled.\r
- * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface\r
- * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface\r
- *\r
- * @note If an erase and a program operations are requested simultaneously, \r
- * the erase operation is performed before the program one.\r
- *\r
- * @param TypeProgram: Indicate the way to program at a specified address.\r
- * This parameter can be a value of @ref FLASH_Type_Program\r
- * @param Address: Specifies the address to be programmed.\r
- * @param Data: Specifies the data to be programmed\r
- * \r
- * @retval HAL_StatusTypeDef HAL Status\r
- */\r
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- \r
- /* Process Locked */\r
- __HAL_LOCK(&pFlash);\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
-\r
-#if defined(FLASH_BANK2_END)\r
- /* If procedure already ongoing, reject the next one */\r
- if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)\r
- {\r
- return HAL_ERROR;\r
- }\r
- \r
- if(Address <= FLASH_BANK1_END)\r
- {\r
- /* Enable End of FLASH Operation and Error source interrupts */\r
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1);\r
-\r
- }else\r
- {\r
- /* Enable End of FLASH Operation and Error source interrupts */\r
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);\r
- }\r
-#else\r
- /* Enable End of FLASH Operation and Error source interrupts */\r
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);\r
-#endif /* FLASH_BANK2_END */\r
- \r
- pFlash.Address = Address;\r
- pFlash.Data = Data;\r
-\r
- if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)\r
- {\r
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;\r
- /* Program halfword (16-bit) at a specified address. */\r
- pFlash.DataRemaining = 1U;\r
- }\r
- else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)\r
- {\r
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;\r
- /* Program word (32-bit : 2*16-bit) at a specified address. */\r
- pFlash.DataRemaining = 2U;\r
- }\r
- else\r
- {\r
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;\r
- /* Program double word (64-bit : 4*16-bit) at a specified address. */\r
- pFlash.DataRemaining = 4U;\r
- }\r
-\r
- /* Program halfword (16-bit) at a specified address. */\r
- FLASH_Program_HalfWord(Address, (uint16_t)Data);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief This function handles FLASH interrupt request.\r
- * @retval None\r
- */\r
-void HAL_FLASH_IRQHandler(void)\r
-{\r
- uint32_t addresstmp = 0U;\r
- \r
- /* Check FLASH operation error flags */\r
-#if defined(FLASH_BANK2_END)\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \\r
- (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))\r
-#else\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))\r
-#endif /* FLASH_BANK2_END */\r
- {\r
- /* Return the faulty address */\r
- addresstmp = pFlash.Address;\r
- /* Reset address */\r
- pFlash.Address = 0xFFFFFFFFU;\r
- \r
- /* Save the Error code */\r
- FLASH_SetErrorCode();\r
- \r
- /* FLASH error interrupt user callback */\r
- HAL_FLASH_OperationErrorCallback(addresstmp);\r
-\r
- /* Stop the procedure ongoing */\r
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
- }\r
-\r
- /* Check FLASH End of Operation flag */\r
-#if defined(FLASH_BANK2_END)\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1))\r
- {\r
- /* Clear FLASH End of Operation pending bit */\r
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);\r
-#else\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))\r
- {\r
- /* Clear FLASH End of Operation pending bit */\r
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
-#endif /* FLASH_BANK2_END */\r
- \r
- /* Process can continue only if no error detected */\r
- if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)\r
- {\r
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)\r
- {\r
- /* Nb of pages to erased can be decreased */\r
- pFlash.DataRemaining--;\r
-\r
- /* Check if there are still pages to erase */\r
- if(pFlash.DataRemaining != 0U)\r
- {\r
- addresstmp = pFlash.Address;\r
- /*Indicate user which sector has been erased */\r
- HAL_FLASH_EndOfOperationCallback(addresstmp);\r
-\r
- /*Increment sector number*/\r
- addresstmp = pFlash.Address + FLASH_PAGE_SIZE;\r
- pFlash.Address = addresstmp;\r
-\r
- /* If the erase operation is completed, disable the PER Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_PER);\r
-\r
- FLASH_PageErase(addresstmp);\r
- }\r
- else\r
- {\r
- /* No more pages to Erase, user callback can be called. */\r
- /* Reset Sector and stop Erase pages procedure */\r
- pFlash.Address = addresstmp = 0xFFFFFFFFU;\r
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
- /* FLASH EOP interrupt user callback */\r
- HAL_FLASH_EndOfOperationCallback(addresstmp);\r
- }\r
- }\r
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)\r
- {\r
- /* Operation is completed, disable the MER Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);\r
-\r
-#if defined(FLASH_BANK2_END)\r
- /* Stop Mass Erase procedure if no pending mass erase on other bank */\r
- if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER))\r
- {\r
-#endif /* FLASH_BANK2_END */\r
- /* MassErase ended. Return the selected bank */\r
- /* FLASH EOP interrupt user callback */\r
- HAL_FLASH_EndOfOperationCallback(0U);\r
-\r
- /* Stop Mass Erase procedure*/\r
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
- }\r
-#if defined(FLASH_BANK2_END)\r
- }\r
-#endif /* FLASH_BANK2_END */\r
- else\r
- {\r
- /* Nb of 16-bit data to program can be decreased */\r
- pFlash.DataRemaining--;\r
- \r
- /* Check if there are still 16-bit data to program */\r
- if(pFlash.DataRemaining != 0U)\r
- {\r
- /* Increment address to 16-bit */\r
- pFlash.Address += 2U;\r
- addresstmp = pFlash.Address;\r
- \r
- /* Shift to have next 16-bit data */\r
- pFlash.Data = (pFlash.Data >> 16U);\r
- \r
- /* Operation is completed, disable the PG Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_PG);\r
-\r
- /*Program halfword (16-bit) at a specified address.*/\r
- FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);\r
- }\r
- else\r
- {\r
- /* Program ended. Return the selected address */\r
- /* FLASH EOP interrupt user callback */\r
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)\r
- {\r
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
- }\r
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)\r
- {\r
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);\r
- }\r
- else \r
- {\r
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);\r
- }\r
- \r
- /* Reset Address and stop Program procedure */\r
- pFlash.Address = 0xFFFFFFFFU;\r
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
- }\r
- }\r
- }\r
- }\r
- \r
-#if defined(FLASH_BANK2_END)\r
- /* Check FLASH End of Operation flag */\r
- if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2))\r
- {\r
- /* Clear FLASH End of Operation pending bit */\r
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);\r
- \r
- /* Process can continue only if no error detected */\r
- if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)\r
- {\r
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)\r
- {\r
- /* Nb of pages to erased can be decreased */\r
- pFlash.DataRemaining--;\r
- \r
- /* Check if there are still pages to erase*/\r
- if(pFlash.DataRemaining != 0U)\r
- {\r
- /* Indicate user which page address has been erased*/\r
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
- \r
- /* Increment page address to next page */\r
- pFlash.Address += FLASH_PAGE_SIZE;\r
- addresstmp = pFlash.Address;\r
-\r
- /* Operation is completed, disable the PER Bit */\r
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);\r
-\r
- FLASH_PageErase(addresstmp);\r
- }\r
- else\r
- {\r
- /*No more pages to Erase*/\r
- \r
- /*Reset Address and stop Erase pages procedure*/\r
- pFlash.Address = 0xFFFFFFFFU;\r
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
-\r
- /* FLASH EOP interrupt user callback */\r
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
- }\r
- }\r
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)\r
- {\r
- /* Operation is completed, disable the MER Bit */\r
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);\r
-\r
- if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER))\r
- {\r
- /* MassErase ended. Return the selected bank*/\r
- /* FLASH EOP interrupt user callback */\r
- HAL_FLASH_EndOfOperationCallback(0U);\r
- \r
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
- }\r
- }\r
- else\r
- {\r
- /* Nb of 16-bit data to program can be decreased */\r
- pFlash.DataRemaining--;\r
- \r
- /* Check if there are still 16-bit data to program */\r
- if(pFlash.DataRemaining != 0U)\r
- {\r
- /* Increment address to 16-bit */\r
- pFlash.Address += 2U;\r
- addresstmp = pFlash.Address;\r
- \r
- /* Shift to have next 16-bit data */\r
- pFlash.Data = (pFlash.Data >> 16U);\r
- \r
- /* Operation is completed, disable the PG Bit */\r
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);\r
-\r
- /*Program halfword (16-bit) at a specified address.*/\r
- FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);\r
- }\r
- else\r
- {\r
- /*Program ended. Return the selected address*/\r
- /* FLASH EOP interrupt user callback */\r
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)\r
- {\r
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
- }\r
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)\r
- {\r
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U);\r
- }\r
- else \r
- {\r
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U);\r
- }\r
- \r
- /* Reset Address and stop Program procedure*/\r
- pFlash.Address = 0xFFFFFFFFU;\r
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
- }\r
- }\r
- }\r
- }\r
-#endif \r
-\r
- if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\r
- {\r
-#if defined(FLASH_BANK2_END)\r
- /* Operation is completed, disable the PG, PER and MER Bits for both bank */\r
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));\r
- CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); \r
- \r
- /* Disable End of FLASH Operation and Error source interrupts for both banks */\r
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);\r
-#else\r
- /* Operation is completed, disable the PG, PER and MER Bits */\r
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));\r
-\r
- /* Disable End of FLASH Operation and Error source interrupts */\r
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);\r
-#endif /* FLASH_BANK2_END */\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(&pFlash);\r
- }\r
-}\r
-\r
-/**\r
- * @brief FLASH end of operation interrupt callback\r
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
- * - Mass Erase: No return value expected\r
- * - Pages Erase: Address of the page which has been erased \r
- * (if 0xFFFFFFFF, it means that all the selected pages have been erased)\r
- * - Program: Address which was selected for data program\r
- * @retval none\r
- */\r
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(ReturnValue);\r
-\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\r
- */ \r
-}\r
-\r
-/**\r
- * @brief FLASH operation error interrupt callback\r
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
- * - Mass Erase: No return value expected\r
- * - Pages Erase: Address of the page which returned an error\r
- * - Program: Address which was selected for data program\r
- * @retval none\r
- */\r
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(ReturnValue);\r
-\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_FLASH_OperationErrorCallback could be implemented in the user file\r
- */ \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions \r
- * @brief management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Peripheral Control functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection provides a set of functions allowing to control the FLASH \r
- memory operations.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Unlock the FLASH control register access\r
- * @retval HAL Status\r
- */\r
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
-\r
- if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)\r
- {\r
- /* Authorize the FLASH Registers access */\r
- WRITE_REG(FLASH->KEYR, FLASH_KEY1);\r
- WRITE_REG(FLASH->KEYR, FLASH_KEY2);\r
-\r
- /* Verify Flash is unlocked */\r
- if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)\r
- {\r
- status = HAL_ERROR;\r
- }\r
- }\r
-#if defined(FLASH_BANK2_END)\r
- if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET)\r
- {\r
- /* Authorize the FLASH BANK2 Registers access */\r
- WRITE_REG(FLASH->KEYR2, FLASH_KEY1);\r
- WRITE_REG(FLASH->KEYR2, FLASH_KEY2);\r
- \r
- /* Verify Flash BANK2 is unlocked */\r
- if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET)\r
- {\r
- status = HAL_ERROR;\r
- }\r
- }\r
-#endif /* FLASH_BANK2_END */\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Locks the FLASH control register access\r
- * @retval HAL Status\r
- */\r
-HAL_StatusTypeDef HAL_FLASH_Lock(void)\r
-{\r
- /* Set the LOCK Bit to lock the FLASH Registers access */\r
- SET_BIT(FLASH->CR, FLASH_CR_LOCK);\r
- \r
-#if defined(FLASH_BANK2_END)\r
- /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */\r
- SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);\r
-\r
-#endif /* FLASH_BANK2_END */\r
- return HAL_OK; \r
-}\r
-\r
-/**\r
- * @brief Unlock the FLASH Option Control Registers access.\r
- * @retval HAL Status\r
- */\r
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\r
-{\r
- if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))\r
- {\r
- /* Authorizes the Option Byte register programming */\r
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);\r
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);\r
- }\r
- else\r
- {\r
- return HAL_ERROR;\r
- } \r
- \r
- return HAL_OK; \r
-}\r
-\r
-/**\r
- * @brief Lock the FLASH Option Control Registers access.\r
- * @retval HAL Status \r
- */\r
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\r
-{\r
- /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);\r
- \r
- return HAL_OK; \r
-}\r
- \r
-/**\r
- * @brief Launch the option byte loading.\r
- * @note This function will reset automatically the MCU.\r
- * @retval None\r
- */\r
-void HAL_FLASH_OB_Launch(void)\r
-{\r
- /* Initiates a system reset request to launch the option byte loading */\r
- HAL_NVIC_SystemReset();\r
-}\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions \r
- * @brief Peripheral errors functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Peripheral Errors functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection permit to get in run-time errors of the FLASH peripheral.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Get the specific FLASH error flag.\r
- * @retval FLASH_ErrorCode The returned value can be:\r
- * @ref FLASH_Error_Codes\r
- */\r
-uint32_t HAL_FLASH_GetError(void)\r
-{\r
- return pFlash.ErrorCode;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASH_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Program a half-word (16-bit) at a specified address.\r
- * @param Address specify the address to be programmed.\r
- * @param Data specify the data to be programmed.\r
- * @retval None\r
- */\r
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)\r
-{\r
- /* Clean the error context */\r
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
- \r
-#if defined(FLASH_BANK2_END)\r
- if(Address <= FLASH_BANK1_END)\r
- {\r
-#endif /* FLASH_BANK2_END */\r
- /* Proceed to program the new data */\r
- SET_BIT(FLASH->CR, FLASH_CR_PG);\r
-#if defined(FLASH_BANK2_END)\r
- }\r
- else\r
- {\r
- /* Proceed to program the new data */\r
- SET_BIT(FLASH->CR2, FLASH_CR2_PG);\r
- }\r
-#endif /* FLASH_BANK2_END */\r
-\r
- /* Write data in the address */\r
- *(__IO uint16_t*)Address = Data;\r
-}\r
-\r
-/**\r
- * @brief Wait for a FLASH operation to complete.\r
- * @param Timeout maximum flash operation timeout\r
- * @retval HAL Status\r
- */\r
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\r
-{\r
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r
- Even if the FLASH operation fails, the BUSY flag will be reset and an error\r
- flag will be set */\r
- \r
- uint32_t tickstart = HAL_GetTick();\r
- \r
- while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) \r
- { \r
- if (Timeout != HAL_MAX_DELAY)\r
- {\r
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- \r
- /* Check FLASH End of Operation flag */\r
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))\r
- {\r
- /* Clear FLASH End of Operation pending bit */\r
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
- }\r
- \r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || \r
- __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || \r
- __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))\r
- {\r
- /*Save the error code*/\r
- FLASH_SetErrorCode();\r
- return HAL_ERROR;\r
- }\r
-\r
- /* There is no error flag set */\r
- return HAL_OK;\r
-}\r
-\r
-#if defined(FLASH_BANK2_END)\r
-/**\r
- * @brief Wait for a FLASH BANK2 operation to complete.\r
- * @param Timeout maximum flash operation timeout\r
- * @retval HAL_StatusTypeDef HAL Status\r
- */\r
-HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)\r
-{ \r
- /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.\r
- Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error\r
- flag will be set */\r
- \r
- uint32_t tickstart = HAL_GetTick();\r
- \r
- while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) \r
- { \r
- if (Timeout != HAL_MAX_DELAY)\r
- {\r
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- \r
- /* Check FLASH End of Operation flag */\r
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2))\r
- {\r
- /* Clear FLASH End of Operation pending bit */\r
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);\r
- }\r
-\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))\r
- {\r
- /*Save the error code*/\r
- FLASH_SetErrorCode();\r
- return HAL_ERROR;\r
- }\r
-\r
- /* If there is an error flag set */\r
- return HAL_OK;\r
- \r
-}\r
-#endif /* FLASH_BANK2_END */\r
-\r
-/**\r
- * @brief Set the specific FLASH error flag.\r
- * @retval None\r
- */\r
-static void FLASH_SetErrorCode(void)\r
-{\r
- uint32_t flags = 0U;\r
- \r
-#if defined(FLASH_BANK2_END)\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))\r
-#else\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))\r
-#endif /* FLASH_BANK2_END */\r
- {\r
- pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;\r
-#if defined(FLASH_BANK2_END)\r
- flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;\r
-#else\r
- flags |= FLASH_FLAG_WRPERR;\r
-#endif /* FLASH_BANK2_END */\r
- }\r
-#if defined(FLASH_BANK2_END)\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))\r
-#else\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))\r
-#endif /* FLASH_BANK2_END */\r
- {\r
- pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;\r
-#if defined(FLASH_BANK2_END)\r
- flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;\r
-#else\r
- flags |= FLASH_FLAG_PGERR;\r
-#endif /* FLASH_BANK2_END */\r
- }\r
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))\r
- {\r
- pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;\r
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);\r
- }\r
-\r
- /* Clear FLASH error pending bits */\r
- __HAL_FLASH_CLEAR_FLAG(flags);\r
-} \r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_FLASH_MODULE_ENABLED */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_flash_ex.c\r
- * @author MCD Application Team\r
- * @brief Extended FLASH HAL module driver.\r
- * \r
- * This file provides firmware functions to manage the following \r
- * functionalities of the FLASH peripheral:\r
- * + Extended Initialization/de-initialization functions\r
- * + Extended I/O operation functions\r
- * + Extended Peripheral Control functions \r
- * \r
- @verbatim\r
- ==============================================================================\r
- ##### Flash peripheral extended features #####\r
- ==============================================================================\r
- \r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..] This driver provides functions to configure and program the FLASH memory \r
- of all STM32F1xxx devices. It includes\r
- \r
- (++) Set/Reset the write protection\r
- (++) Program the user Option Bytes\r
- (++) Get the Read protection Level\r
- \r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ****************************************************************************** \r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-#ifdef HAL_FLASH_MODULE_ENABLED\r
-\r
-/** @addtogroup FLASH\r
- * @{\r
- */\r
-/** @addtogroup FLASH_Private_Variables\r
- * @{\r
- */\r
-/* Variables used for Erase pages under interruption*/\r
-extern FLASH_ProcessTypeDef pFlash;\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FLASHEx FLASHEx\r
- * @brief FLASH HAL Extension module driver\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants\r
- * @{\r
- */\r
-#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos\r
-#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos\r
-#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros\r
- * @{\r
- */\r
-/**\r
- * @}\r
- */ \r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions\r
- * @{\r
- */\r
-/* Erase operations */\r
-static void FLASH_MassErase(uint32_t Banks);\r
-void FLASH_PageErase(uint32_t PageAddress);\r
-\r
-/* Option bytes control */\r
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);\r
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);\r
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);\r
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);\r
-static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);\r
-static uint32_t FLASH_OB_GetWRP(void);\r
-static uint32_t FLASH_OB_GetRDP(void);\r
-static uint8_t FLASH_OB_GetUser(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions ---------------------------------------------------------*/\r
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\r
- * @{\r
- */\r
- \r
-/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions\r
- * @brief FLASH Memory Erasing functions\r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### FLASH Erasing Programming functions ##### \r
- ==============================================================================\r
-\r
- [..] The FLASH Memory Erasing functions, includes the following functions:\r
- (+) @ref HAL_FLASHEx_Erase: return only when erase has been done\r
- (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback \r
- is called with parameter 0xFFFFFFFF\r
-\r
- [..] Any operation of erase should follow these steps:\r
- (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and \r
- program memory access.\r
- (#) Call the desired function to erase page.\r
- (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access \r
- (recommended to protect the FLASH memory against possible unwanted operation).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-\r
-/**\r
- * @brief Perform a mass erase or erase the specified FLASH memory pages\r
- * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function\r
- * must be called before.\r
- * Call the @ref HAL_FLASH_Lock() to disable the flash memory access \r
- * (recommended to protect the FLASH memory against possible unwanted operation)\r
- * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\r
- * contains the configuration information for the erasing.\r
- *\r
- * @param[out] PageError pointer to variable that\r
- * contains the configuration information on faulty page in case of error\r
- * (0xFFFFFFFF means that all the pages have been correctly erased)\r
- *\r
- * @retval HAL_StatusTypeDef HAL Status\r
- */\r
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
- uint32_t address = 0U;\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(&pFlash);\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
-\r
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
- {\r
-#if defined(FLASH_BANK2_END)\r
- if (pEraseInit->Banks == FLASH_BANK_BOTH)\r
- {\r
- /* Mass Erase requested for Bank1 and Bank2 */\r
- /* Wait for last operation to be completed */\r
- if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \\r
- (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))\r
- {\r
- /*Mass erase to be done*/\r
- FLASH_MassErase(FLASH_BANK_BOTH);\r
- \r
- /* Wait for last operation to be completed */\r
- if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \\r
- (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))\r
- {\r
- status = HAL_OK;\r
- }\r
- \r
- /* If the erase operation is completed, disable the MER Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);\r
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);\r
- }\r
- }\r
- else if (pEraseInit->Banks == FLASH_BANK_2)\r
- {\r
- /* Mass Erase requested for Bank2 */\r
- /* Wait for last operation to be completed */\r
- if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)\r
- {\r
- /*Mass erase to be done*/\r
- FLASH_MassErase(FLASH_BANK_2);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);\r
- \r
- /* If the erase operation is completed, disable the MER Bit */\r
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);\r
- }\r
- }\r
- else \r
-#endif /* FLASH_BANK2_END */\r
- {\r
- /* Mass Erase requested for Bank1 */\r
- /* Wait for last operation to be completed */\r
- if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)\r
- {\r
- /*Mass erase to be done*/\r
- FLASH_MassErase(FLASH_BANK_1);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- \r
- /* If the erase operation is completed, disable the MER Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Page Erase is requested */\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));\r
- assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));\r
- \r
-#if defined(FLASH_BANK2_END)\r
- /* Page Erase requested on address located on bank2 */\r
- if(pEraseInit->PageAddress > FLASH_BANK1_END)\r
- { \r
- /* Wait for last operation to be completed */\r
- if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)\r
- {\r
- /*Initialization of PageError variable*/\r
- *PageError = 0xFFFFFFFFU;\r
- \r
- /* Erase by page by page to be done*/\r
- for(address = pEraseInit->PageAddress;\r
- address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);\r
- address += FLASH_PAGE_SIZE)\r
- {\r
- FLASH_PageErase(address);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);\r
- \r
- /* If the erase operation is completed, disable the PER Bit */\r
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);\r
- \r
- if (status != HAL_OK)\r
- {\r
- /* In case of error, stop erase procedure and return the faulty address */\r
- *PageError = address;\r
- break;\r
- }\r
- }\r
- }\r
- }\r
- else\r
-#endif /* FLASH_BANK2_END */\r
- {\r
- /* Page Erase requested on address located on bank1 */\r
- /* Wait for last operation to be completed */\r
- if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)\r
- {\r
- /*Initialization of PageError variable*/\r
- *PageError = 0xFFFFFFFFU;\r
- \r
- /* Erase page by page to be done*/\r
- for(address = pEraseInit->PageAddress;\r
- address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);\r
- address += FLASH_PAGE_SIZE)\r
- {\r
- FLASH_PageErase(address);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- \r
- /* If the erase operation is completed, disable the PER Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_PER);\r
- \r
- if (status != HAL_OK)\r
- {\r
- /* In case of error, stop erase procedure and return the faulty address */\r
- *PageError = address;\r
- break;\r
- }\r
- }\r
- }\r
- }\r
- }\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(&pFlash);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled\r
- * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function\r
- * must be called before.\r
- * Call the @ref HAL_FLASH_Lock() to disable the flash memory access \r
- * (recommended to protect the FLASH memory against possible unwanted operation)\r
- * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\r
- * contains the configuration information for the erasing.\r
- *\r
- * @retval HAL_StatusTypeDef HAL Status\r
- */\r
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(&pFlash);\r
-\r
- /* If procedure already ongoing, reject the next one */\r
- if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)\r
- {\r
- return HAL_ERROR;\r
- }\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
-\r
- /* Enable End of FLASH Operation and Error source interrupts */\r
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);\r
-\r
-#if defined(FLASH_BANK2_END)\r
- /* Enable End of FLASH Operation and Error source interrupts */\r
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);\r
- \r
-#endif\r
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
- {\r
- /*Mass erase to be done*/\r
- pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;\r
- FLASH_MassErase(pEraseInit->Banks);\r
- }\r
- else\r
- {\r
- /* Erase by page to be done*/\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));\r
- assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));\r
-\r
- pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;\r
- pFlash.DataRemaining = pEraseInit->NbPages;\r
- pFlash.Address = pEraseInit->PageAddress;\r
-\r
- /*Erase 1st page and wait for IT*/\r
- FLASH_PageErase(pEraseInit->PageAddress);\r
- }\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions\r
- * @brief Option Bytes Programming functions\r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Option Bytes Programming functions ##### \r
- ============================================================================== \r
- [..]\r
- This subsection provides a set of functions allowing to control the FLASH \r
- option bytes operations.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Erases the FLASH option bytes.\r
- * @note This functions erases all option bytes except the Read protection (RDP).\r
- * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface\r
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes\r
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes\r
- * (system reset will occur)\r
- * @retval HAL status\r
- */\r
-\r
-HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)\r
-{\r
- uint8_t rdptmp = OB_RDP_LEVEL_0;\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
-\r
- /* Get the actual read protection Option Byte value */\r
- rdptmp = FLASH_OB_GetRDP();\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
- if(status == HAL_OK)\r
- {\r
- /* Clean the error context */\r
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
- /* If the previous operation is completed, proceed to erase the option bytes */\r
- SET_BIT(FLASH->CR, FLASH_CR_OPTER);\r
- SET_BIT(FLASH->CR, FLASH_CR_STRT);\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
- /* If the erase operation is completed, disable the OPTER Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);\r
-\r
- if(status == HAL_OK)\r
- {\r
- /* Restore the last read protection Option Byte value */\r
- status = FLASH_OB_RDP_LevelConfig(rdptmp);\r
- }\r
- }\r
-\r
- /* Return the erase status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Program option bytes\r
- * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface\r
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes\r
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes\r
- * (system reset will occur)\r
- *\r
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that\r
- * contains the configuration information for the programming.\r
- *\r
- * @retval HAL_StatusTypeDef HAL Status\r
- */\r
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(&pFlash);\r
-\r
- /* Check the parameters */\r
- assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\r
-\r
- /* Write protection configuration */\r
- if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)\r
- {\r
- assert_param(IS_WRPSTATE(pOBInit->WRPState));\r
- if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)\r
- {\r
- /* Enable of Write protection on the selected page */\r
- status = FLASH_OB_EnableWRP(pOBInit->WRPPage);\r
- }\r
- else\r
- {\r
- /* Disable of Write protection on the selected page */\r
- status = FLASH_OB_DisableWRP(pOBInit->WRPPage);\r
- }\r
- if (status != HAL_OK)\r
- {\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(&pFlash);\r
- return status;\r
- }\r
- }\r
-\r
- /* Read protection configuration */\r
- if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)\r
- {\r
- status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);\r
- if (status != HAL_OK)\r
- {\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(&pFlash);\r
- return status;\r
- }\r
- }\r
-\r
- /* USER configuration */\r
- if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)\r
- {\r
- status = FLASH_OB_UserConfig(pOBInit->USERConfig);\r
- if (status != HAL_OK)\r
- {\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(&pFlash);\r
- return status;\r
- }\r
- }\r
-\r
- /* DATA configuration*/\r
- if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)\r
- {\r
- status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);\r
- if (status != HAL_OK)\r
- {\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(&pFlash);\r
- return status;\r
- }\r
- }\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(&pFlash);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Get the Option byte configuration\r
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that\r
- * contains the configuration information for the programming.\r
- *\r
- * @retval None\r
- */\r
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\r
-{\r
- pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;\r
-\r
- /*Get WRP*/\r
- pOBInit->WRPPage = FLASH_OB_GetWRP();\r
-\r
- /*Get RDP Level*/\r
- pOBInit->RDPLevel = FLASH_OB_GetRDP();\r
-\r
- /*Get USER*/\r
- pOBInit->USERConfig = FLASH_OB_GetUser();\r
-}\r
-\r
-/**\r
- * @brief Get the Option byte user data\r
- * @param DATAAdress Address of the option byte DATA\r
- * This parameter can be one of the following values:\r
- * @arg @ref OB_DATA_ADDRESS_DATA0\r
- * @arg @ref OB_DATA_ADDRESS_DATA1\r
- * @retval Value programmed in USER data\r
- */\r
-uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)\r
-{\r
- uint32_t value = 0;\r
- \r
- if (DATAAdress == OB_DATA_ADDRESS_DATA0)\r
- {\r
- /* Get value programmed in OB USER Data0 */\r
- value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;\r
- }\r
- else\r
- {\r
- /* Get value programmed in OB USER Data1 */\r
- value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;\r
- }\r
- \r
- return value;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASHEx_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Full erase of FLASH memory Bank \r
- * @param Banks Banks to be erased\r
- * This parameter can be one of the following values:\r
- * @arg @ref FLASH_BANK_1 Bank1 to be erased\r
- @if STM32F101xG\r
- * @arg @ref FLASH_BANK_2 Bank2 to be erased\r
- * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased\r
- @endif\r
- @if STM32F103xG\r
- * @arg @ref FLASH_BANK_2 Bank2 to be erased\r
- * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased\r
- @endif\r
- *\r
- * @retval None\r
- */\r
-static void FLASH_MassErase(uint32_t Banks)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_BANK(Banks));\r
-\r
- /* Clean the error context */\r
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
-#if defined(FLASH_BANK2_END)\r
- if(Banks == FLASH_BANK_BOTH)\r
- {\r
- /* bank1 & bank2 will be erased*/\r
- SET_BIT(FLASH->CR, FLASH_CR_MER);\r
- SET_BIT(FLASH->CR2, FLASH_CR2_MER);\r
- SET_BIT(FLASH->CR, FLASH_CR_STRT);\r
- SET_BIT(FLASH->CR2, FLASH_CR2_STRT);\r
- }\r
- else if(Banks == FLASH_BANK_2)\r
- {\r
- /*Only bank2 will be erased*/\r
- SET_BIT(FLASH->CR2, FLASH_CR2_MER);\r
- SET_BIT(FLASH->CR2, FLASH_CR2_STRT);\r
- }\r
- else\r
- {\r
-#endif /* FLASH_BANK2_END */\r
-#if !defined(FLASH_BANK2_END)\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(Banks);\r
-#endif /* FLASH_BANK2_END */ \r
- /* Only bank1 will be erased*/\r
- SET_BIT(FLASH->CR, FLASH_CR_MER);\r
- SET_BIT(FLASH->CR, FLASH_CR_STRT);\r
-#if defined(FLASH_BANK2_END)\r
- }\r
-#endif /* FLASH_BANK2_END */\r
-}\r
-\r
-/**\r
- * @brief Enable the write protection of the desired pages\r
- * @note An option byte erase is done automatically in this function. \r
- * @note When the memory read protection level is selected (RDP level = 1), \r
- * it is not possible to program or erase the flash page i if\r
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \r
- * \r
- * @param WriteProtectPage specifies the page(s) to be write protected.\r
- * The value of this parameter depend on device used within the same series \r
- * @retval HAL status \r
- */\r
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- uint16_t WRP0_Data = 0xFFFF;\r
-#if defined(FLASH_WRP1_WRP1)\r
- uint16_t WRP1_Data = 0xFFFF;\r
-#endif /* FLASH_WRP1_WRP1 */\r
-#if defined(FLASH_WRP2_WRP2)\r
- uint16_t WRP2_Data = 0xFFFF;\r
-#endif /* FLASH_WRP2_WRP2 */\r
-#if defined(FLASH_WRP3_WRP3)\r
- uint16_t WRP3_Data = 0xFFFF;\r
-#endif /* FLASH_WRP3_WRP3 */\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_WRP(WriteProtectPage));\r
- \r
- /* Get current write protected pages and the new pages to be protected ******/\r
- WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));\r
- \r
-#if defined(OB_WRP_PAGES0TO15MASK)\r
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);\r
-#elif defined(OB_WRP_PAGES0TO31MASK)\r
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);\r
-#endif /* OB_WRP_PAGES0TO31MASK */\r
- \r
-#if defined(OB_WRP_PAGES16TO31MASK)\r
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);\r
-#elif defined(OB_WRP_PAGES32TO63MASK)\r
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);\r
-#endif /* OB_WRP_PAGES32TO63MASK */\r
- \r
-#if defined(OB_WRP_PAGES64TO95MASK)\r
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);\r
-#endif /* OB_WRP_PAGES64TO95MASK */\r
-#if defined(OB_WRP_PAGES32TO47MASK)\r
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);\r
-#endif /* OB_WRP_PAGES32TO47MASK */\r
-\r
-#if defined(OB_WRP_PAGES96TO127MASK)\r
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); \r
-#elif defined(OB_WRP_PAGES48TO255MASK)\r
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); \r
-#elif defined(OB_WRP_PAGES48TO511MASK)\r
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); \r
-#elif defined(OB_WRP_PAGES48TO127MASK)\r
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); \r
-#endif /* OB_WRP_PAGES96TO127MASK */\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
- if(status == HAL_OK)\r
- { \r
- /* Clean the error context */\r
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
- /* To be able to write again option byte, need to perform a option byte erase */\r
- status = HAL_FLASHEx_OBErase();\r
- if (status == HAL_OK) \r
- {\r
- /* Enable write protection */\r
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);\r
-\r
-#if defined(FLASH_WRP0_WRP0)\r
- if(WRP0_Data != 0xFFU)\r
- {\r
- OB->WRP0 &= WRP0_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- }\r
-#endif /* FLASH_WRP0_WRP0 */\r
-\r
-#if defined(FLASH_WRP1_WRP1)\r
- if((status == HAL_OK) && (WRP1_Data != 0xFFU))\r
- {\r
- OB->WRP1 &= WRP1_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- }\r
-#endif /* FLASH_WRP1_WRP1 */\r
-\r
-#if defined(FLASH_WRP2_WRP2)\r
- if((status == HAL_OK) && (WRP2_Data != 0xFFU))\r
- {\r
- OB->WRP2 &= WRP2_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- }\r
-#endif /* FLASH_WRP2_WRP2 */\r
-\r
-#if defined(FLASH_WRP3_WRP3)\r
- if((status == HAL_OK) && (WRP3_Data != 0xFFU))\r
- {\r
- OB->WRP3 &= WRP3_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- }\r
-#endif /* FLASH_WRP3_WRP3 */\r
-\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);\r
- }\r
- }\r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Disable the write protection of the desired pages\r
- * @note An option byte erase is done automatically in this function. \r
- * @note When the memory read protection level is selected (RDP level = 1), \r
- * it is not possible to program or erase the flash page i if \r
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \r
- * \r
- * @param WriteProtectPage specifies the page(s) to be write unprotected.\r
- * The value of this parameter depend on device used within the same series \r
- * @retval HAL status \r
- */\r
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- uint16_t WRP0_Data = 0xFFFF;\r
-#if defined(FLASH_WRP1_WRP1)\r
- uint16_t WRP1_Data = 0xFFFF;\r
-#endif /* FLASH_WRP1_WRP1 */\r
-#if defined(FLASH_WRP2_WRP2)\r
- uint16_t WRP2_Data = 0xFFFF;\r
-#endif /* FLASH_WRP2_WRP2 */\r
-#if defined(FLASH_WRP3_WRP3)\r
- uint16_t WRP3_Data = 0xFFFF;\r
-#endif /* FLASH_WRP3_WRP3 */\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_WRP(WriteProtectPage));\r
-\r
- /* Get current write protected pages and the new pages to be unprotected ******/\r
- WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);\r
-\r
-#if defined(OB_WRP_PAGES0TO15MASK)\r
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);\r
-#elif defined(OB_WRP_PAGES0TO31MASK)\r
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);\r
-#endif /* OB_WRP_PAGES0TO31MASK */\r
- \r
-#if defined(OB_WRP_PAGES16TO31MASK)\r
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);\r
-#elif defined(OB_WRP_PAGES32TO63MASK)\r
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);\r
-#endif /* OB_WRP_PAGES32TO63MASK */\r
- \r
-#if defined(OB_WRP_PAGES64TO95MASK)\r
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);\r
-#endif /* OB_WRP_PAGES64TO95MASK */\r
-#if defined(OB_WRP_PAGES32TO47MASK)\r
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);\r
-#endif /* OB_WRP_PAGES32TO47MASK */\r
-\r
-#if defined(OB_WRP_PAGES96TO127MASK)\r
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); \r
-#elif defined(OB_WRP_PAGES48TO255MASK)\r
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); \r
-#elif defined(OB_WRP_PAGES48TO511MASK)\r
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); \r
-#elif defined(OB_WRP_PAGES48TO127MASK)\r
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); \r
-#endif /* OB_WRP_PAGES96TO127MASK */\r
-\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
- if(status == HAL_OK)\r
- { \r
- /* Clean the error context */\r
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
- /* To be able to write again option byte, need to perform a option byte erase */\r
- status = HAL_FLASHEx_OBErase();\r
- if (status == HAL_OK) \r
- {\r
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);\r
-\r
-#if defined(FLASH_WRP0_WRP0)\r
- if(WRP0_Data != 0xFFU)\r
- {\r
- OB->WRP0 |= WRP0_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- }\r
-#endif /* FLASH_WRP0_WRP0 */\r
-\r
-#if defined(FLASH_WRP1_WRP1)\r
- if((status == HAL_OK) && (WRP1_Data != 0xFFU))\r
- {\r
- OB->WRP1 |= WRP1_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- }\r
-#endif /* FLASH_WRP1_WRP1 */\r
-\r
-#if defined(FLASH_WRP2_WRP2)\r
- if((status == HAL_OK) && (WRP2_Data != 0xFFU))\r
- {\r
- OB->WRP2 |= WRP2_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- }\r
-#endif /* FLASH_WRP2_WRP2 */\r
-\r
-#if defined(FLASH_WRP3_WRP3)\r
- if((status == HAL_OK) && (WRP3_Data != 0xFFU))\r
- {\r
- OB->WRP3 |= WRP3_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- }\r
-#endif /* FLASH_WRP3_WRP3 */\r
-\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);\r
- }\r
- }\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Set the read protection level.\r
- * @param ReadProtectLevel specifies the read protection level.\r
- * This parameter can be one of the following values:\r
- * @arg @ref OB_RDP_LEVEL_0 No protection\r
- * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory\r
- * @retval HAL status\r
- */\r
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- \r
- if(status == HAL_OK)\r
- { \r
- /* Clean the error context */\r
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
- \r
- /* If the previous operation is completed, proceed to erase the option bytes */\r
- SET_BIT(FLASH->CR, FLASH_CR_OPTER);\r
- SET_BIT(FLASH->CR, FLASH_CR_STRT);\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
- /* If the erase operation is completed, disable the OPTER Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);\r
-\r
- if(status == HAL_OK)\r
- {\r
- /* Enable the Option Bytes Programming operation */\r
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);\r
- \r
- WRITE_REG(OB->RDP, ReadProtectLevel);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); \r
- \r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);\r
- }\r
- }\r
- \r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Program the FLASH User Option Byte. \r
- * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)\r
- * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), \r
- * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).\r
- * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . \r
- * @retval HAL status\r
- */\r
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));\r
- assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));\r
- assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));\r
-#if defined(FLASH_BANK2_END)\r
- assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));\r
-#endif /* FLASH_BANK2_END */\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- \r
- if(status == HAL_OK)\r
- { \r
- /* Clean the error context */\r
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
- /* Enable the Option Bytes Programming operation */\r
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG); \r
- \r
-#if defined(FLASH_BANK2_END)\r
- OB->USER = (UserConfig | 0xF0U);\r
-#else\r
- OB->USER = (UserConfig | 0x88U);\r
-#endif /* FLASH_BANK2_END */\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
-\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);\r
- }\r
- \r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Programs a half word at a specified Option Byte Data address.\r
- * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface\r
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes\r
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes \r
- * (system reset will occur)\r
- * Programming of the OB should be performed only after an erase (otherwise PGERR occurs)\r
- * @param Address specifies the address to be programmed.\r
- * This parameter can be 0x1FFFF804 or 0x1FFFF806. \r
- * @param Data specifies the data to be programmed.\r
- * @retval HAL status\r
- */\r
-static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_OB_DATA_ADDRESS(Address));\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- \r
- if(status == HAL_OK)\r
- {\r
- /* Clean the error context */\r
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
- /* Enables the Option Bytes Programming operation */\r
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG); \r
- *(__IO uint16_t*)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
- \r
- /* If the program operation is completed, disable the OPTPG Bit */\r
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);\r
- }\r
- /* Return the Option Byte Data Program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Return the FLASH Write Protection Option Bytes value.\r
- * @retval The FLASH Write Protection Option Bytes value\r
- */\r
-static uint32_t FLASH_OB_GetWRP(void)\r
-{\r
- /* Return the FLASH write protection Register value */\r
- return (uint32_t)(READ_REG(FLASH->WRPR));\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Read Protection level.\r
- * @retval FLASH RDP level\r
- * This parameter can be one of the following values:\r
- * @arg @ref OB_RDP_LEVEL_0 No protection\r
- * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory\r
- */\r
-static uint32_t FLASH_OB_GetRDP(void)\r
-{\r
- uint32_t readstatus = OB_RDP_LEVEL_0;\r
- uint32_t tmp_reg = 0U;\r
- \r
- /* Read RDP level bits */\r
- tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);\r
-\r
- if (tmp_reg == FLASH_OBR_RDPRT)\r
- {\r
- readstatus = OB_RDP_LEVEL_1;\r
- }\r
- else \r
- {\r
- readstatus = OB_RDP_LEVEL_0;\r
- }\r
-\r
- return readstatus;\r
-}\r
-\r
-/**\r
- * @brief Return the FLASH User Option Byte value.\r
- * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), \r
- * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).\r
- * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . \r
- */\r
-static uint8_t FLASH_OB_GetUser(void)\r
-{\r
- /* Return the User Option Byte */\r
- return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup FLASH\r
- * @{\r
- */\r
-\r
-/** @addtogroup FLASH_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Erase the specified FLASH memory page\r
- * @param PageAddress FLASH page to erase\r
- * The value of this parameter depend on device used within the same series \r
- * \r
- * @retval None\r
- */\r
-void FLASH_PageErase(uint32_t PageAddress)\r
-{\r
- /* Clean the error context */\r
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
-\r
-#if defined(FLASH_BANK2_END)\r
- if(PageAddress > FLASH_BANK1_END)\r
- { \r
- /* Proceed to erase the page */\r
- SET_BIT(FLASH->CR2, FLASH_CR2_PER);\r
- WRITE_REG(FLASH->AR2, PageAddress);\r
- SET_BIT(FLASH->CR2, FLASH_CR2_STRT);\r
- }\r
- else\r
- {\r
-#endif /* FLASH_BANK2_END */\r
- /* Proceed to erase the page */\r
- SET_BIT(FLASH->CR, FLASH_CR_PER);\r
- WRITE_REG(FLASH->AR, PageAddress);\r
- SET_BIT(FLASH->CR, FLASH_CR_STRT);\r
-#if defined(FLASH_BANK2_END)\r
- }\r
-#endif /* FLASH_BANK2_END */\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_FLASH_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_gpio.c\r
- * @author MCD Application Team\r
- * @brief GPIO HAL module driver.\r
- * This file provides firmware functions to manage the following\r
- * functionalities of the General Purpose Input/Output (GPIO) peripheral:\r
- * + Initialization and de-initialization functions\r
- * + IO operation functions\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### GPIO Peripheral features #####\r
- ==============================================================================\r
- [..]\r
- Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each\r
- port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software\r
- in several modes:\r
- (+) Input mode\r
- (+) Analog mode\r
- (+) Output mode\r
- (+) Alternate function mode\r
- (+) External interrupt/event lines\r
-\r
- [..]\r
- During and just after reset, the alternate functions and external interrupt\r
- lines are not active and the I/O ports are configured in input floating mode.\r
-\r
- [..]\r
- All GPIO pins have weak internal pull-up and pull-down resistors, which can be\r
- activated or not.\r
-\r
- [..]\r
- In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r
- type and the IO speed can be selected depending on the VDD value.\r
-\r
- [..]\r
- All ports have external interrupt/event capability. To use external interrupt\r
- lines, the port must be configured in input mode. All available GPIO pins are\r
- connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r
-\r
- [..]\r
- The external interrupt/event controller consists of up to 20 edge detectors in connectivity\r
- line devices, or 19 edge detectors in other devices for generating event/interrupt requests.\r
- Each input line can be independently configured to select the type (event or interrupt) and\r
- the corresponding trigger event (rising or falling or both). Each line can also masked\r
- independently. A pending register maintains the status line of the interrupt requests\r
-\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..]\r
- (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().\r
-\r
- (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r
- (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure\r
- (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef\r
- structure.\r
- (++) In case of Output or alternate function mode selection: the speed is\r
- configured through "Speed" member from GPIO_InitTypeDef structure\r
- (++) Analog mode is required when a pin is to be used as ADC channel\r
- or DAC output.\r
- (++) In case of external interrupt/event selection the "Mode" member from\r
- GPIO_InitTypeDef structure select the type (interrupt or event) and\r
- the corresponding trigger event (rising or falling or both).\r
-\r
- (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority\r
- mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r
- HAL_NVIC_EnableIRQ().\r
-\r
- (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r
-\r
- (#) To set/reset the level of a pin configured in output mode use\r
- HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r
-\r
- (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r
-\r
- (#) During and just after reset, the alternate functions are not\r
- active and the GPIO pins are configured in input floating mode (except JTAG\r
- pins).\r
-\r
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose\r
- (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has\r
- priority over the GPIO function.\r
-\r
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as\r
- general purpose PD0 and PD1, respectively, when the HSE oscillator is off.\r
- The HSE has priority over the GPIO function.\r
-\r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIO GPIO\r
- * @brief GPIO HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_GPIO_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @addtogroup GPIO_Private_Constants GPIO Private Constants\r
- * @{\r
- */\r
-#define GPIO_MODE 0x00000003U\r
-#define EXTI_MODE 0x10000000U\r
-#define GPIO_MODE_IT 0x00010000U\r
-#define GPIO_MODE_EVT 0x00020000U\r
-#define RISING_EDGE 0x00100000U\r
-#define FALLING_EDGE 0x00200000U\r
-#define GPIO_OUTPUT_TYPE 0x00000010U\r
-\r
-#define GPIO_NUMBER 16U\r
-\r
-/* Definitions for bit manipulation of CRL and CRH register */\r
-#define GPIO_CR_MODE_INPUT 0x00000000U /*!< 00: Input mode (reset state) */\r
-#define GPIO_CR_CNF_ANALOG 0x00000000U /*!< 00: Analog mode */\r
-#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state) */\r
-#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008U /*!< 10: Input with pull-up / pull-down */\r
-#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U /*!< 00: General purpose output push-pull */\r
-#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U /*!< 01: General purpose output Open-drain */\r
-#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U /*!< 10: Alternate function output Push-pull */\r
-#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU /*!< 11: Alternate function output Open-drain */\r
-\r
-/**\r
- * @}\r
- */\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions\r
- * @brief Initialization and Configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
- [..]\r
- This section provides functions allowing to initialize and de-initialize the GPIOs\r
- to be ready for use.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-\r
-/**\r
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral\r
- * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains\r
- * the configuration information for the specified GPIO peripheral.\r
- * @retval None\r
- */\r
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r
-{\r
- uint32_t position;\r
- uint32_t ioposition = 0x00U;\r
- uint32_t iocurrent = 0x00U;\r
- uint32_t temp = 0x00U;\r
- uint32_t config = 0x00U;\r
- __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */\r
- uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */\r
-\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r
-\r
- /* Configure the port pins */\r
- for (position = 0U; position < GPIO_NUMBER; position++)\r
- {\r
- /* Get the IO position */\r
- ioposition = (0x01U << position);\r
-\r
- /* Get the current IO position */\r
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;\r
-\r
- if (iocurrent == ioposition)\r
- {\r
- /* Check the Alternate function parameters */\r
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));\r
-\r
- /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */\r
- switch (GPIO_Init->Mode)\r
- {\r
- /* If we are configuring the pin in OUTPUT push-pull mode */\r
- case GPIO_MODE_OUTPUT_PP:\r
- /* Check the GPIO speed parameter */\r
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
- config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;\r
- break;\r
-\r
- /* If we are configuring the pin in OUTPUT open-drain mode */\r
- case GPIO_MODE_OUTPUT_OD:\r
- /* Check the GPIO speed parameter */\r
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
- config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;\r
- break;\r
-\r
- /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */\r
- case GPIO_MODE_AF_PP:\r
- /* Check the GPIO speed parameter */\r
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
- config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;\r
- break;\r
-\r
- /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */\r
- case GPIO_MODE_AF_OD:\r
- /* Check the GPIO speed parameter */\r
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
- config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;\r
- break;\r
-\r
- /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */\r
- case GPIO_MODE_INPUT:\r
- case GPIO_MODE_IT_RISING:\r
- case GPIO_MODE_IT_FALLING:\r
- case GPIO_MODE_IT_RISING_FALLING:\r
- case GPIO_MODE_EVT_RISING:\r
- case GPIO_MODE_EVT_FALLING:\r
- case GPIO_MODE_EVT_RISING_FALLING:\r
- /* Check the GPIO pull parameter */\r
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\r
- if (GPIO_Init->Pull == GPIO_NOPULL)\r
- {\r
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;\r
- }\r
- else if (GPIO_Init->Pull == GPIO_PULLUP)\r
- {\r
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;\r
-\r
- /* Set the corresponding ODR bit */\r
- GPIOx->BSRR = ioposition;\r
- }\r
- else /* GPIO_PULLDOWN */\r
- {\r
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;\r
-\r
- /* Reset the corresponding ODR bit */\r
- GPIOx->BRR = ioposition;\r
- }\r
- break;\r
-\r
- /* If we are configuring the pin in INPUT analog mode */\r
- case GPIO_MODE_ANALOG:\r
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;\r
- break;\r
-\r
- /* Parameters are checked with assert_param */\r
- default:\r
- break;\r
- }\r
-\r
- /* Check if the current bit belongs to first half or last half of the pin count number\r
- in order to address CRH or CRL register*/\r
- configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;\r
- registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);\r
-\r
- /* Apply the new configuration of the pin to the register */\r
- MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));\r
-\r
- /*--------------------- EXTI Mode Configuration ------------------------*/\r
- /* Configure the External Interrupt or event for the current IO */\r
- if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\r
- {\r
- /* Enable AFIO Clock */\r
- __HAL_RCC_AFIO_CLK_ENABLE();\r
- temp = AFIO->EXTICR[position >> 2U];\r
- CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));\r
- SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));\r
- AFIO->EXTICR[position >> 2U] = temp;\r
-\r
-\r
- /* Configure the interrupt mask */\r
- if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r
- {\r
- SET_BIT(EXTI->IMR, iocurrent);\r
- }\r
- else\r
- {\r
- CLEAR_BIT(EXTI->IMR, iocurrent);\r
- }\r
-\r
- /* Configure the event mask */\r
- if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r
- {\r
- SET_BIT(EXTI->EMR, iocurrent);\r
- }\r
- else\r
- {\r
- CLEAR_BIT(EXTI->EMR, iocurrent);\r
- }\r
-\r
- /* Enable or disable the rising trigger */\r
- if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r
- {\r
- SET_BIT(EXTI->RTSR, iocurrent);\r
- }\r
- else\r
- {\r
- CLEAR_BIT(EXTI->RTSR, iocurrent);\r
- }\r
-\r
- /* Enable or disable the falling trigger */\r
- if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r
- {\r
- SET_BIT(EXTI->FTSR, iocurrent);\r
- }\r
- else\r
- {\r
- CLEAR_BIT(EXTI->FTSR, iocurrent);\r
- }\r
- }\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief De-initializes the GPIOx peripheral registers to their default reset values.\r
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral\r
- * @param GPIO_Pin: specifies the port bit to be written.\r
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
- * @retval None\r
- */\r
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)\r
-{\r
- uint32_t position = 0x00U;\r
- uint32_t iocurrent = 0x00U;\r
- uint32_t tmp = 0x00U;\r
- __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */\r
- uint32_t registeroffset = 0U;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
-\r
- /* Configure the port pins */\r
- while ((GPIO_Pin >> position) != 0U)\r
- {\r
- /* Get current io position */\r
- iocurrent = (GPIO_Pin) & (1U << position);\r
-\r
- if (iocurrent)\r
- {\r
- /*------------------------- GPIO Mode Configuration --------------------*/\r
- /* Check if the current bit belongs to first half or last half of the pin count number\r
- in order to address CRH or CRL register */\r
- configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;\r
- registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);\r
-\r
- /* CRL/CRH default value is floating input(0x04) shifted to correct position */\r
- MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset);\r
-\r
- /* ODR default value is 0 */\r
- CLEAR_BIT(GPIOx->ODR, iocurrent);\r
-\r
- /*------------------------- EXTI Mode Configuration --------------------*/\r
- /* Clear the External Interrupt or Event for the current IO */\r
-\r
- tmp = AFIO->EXTICR[position >> 2U];\r
- tmp &= 0x0FU << (4U * (position & 0x03U));\r
- if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))\r
- {\r
- tmp = 0x0FU << (4U * (position & 0x03U));\r
- CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp);\r
-\r
- /* Clear EXTI line configuration */\r
- CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);\r
- CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);\r
-\r
- /* Clear Rising Falling edge configuration */\r
- CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);\r
- CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);\r
- }\r
- }\r
-\r
- position++;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions\r
- * @brief GPIO Read and Write\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### IO operation functions #####\r
- ===============================================================================\r
- [..]\r
- This subsection provides a set of functions allowing to manage the GPIOs.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Reads the specified input port pin.\r
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral\r
- * @param GPIO_Pin: specifies the port bit to read.\r
- * This parameter can be GPIO_PIN_x where x can be (0..15).\r
- * @retval The input port pin value.\r
- */\r
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)\r
-{\r
- GPIO_PinState bitstatus;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
-\r
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)\r
- {\r
- bitstatus = GPIO_PIN_SET;\r
- }\r
- else\r
- {\r
- bitstatus = GPIO_PIN_RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Sets or clears the selected data port bit.\r
- *\r
- * @note This function uses GPIOx_BSRR register to allow atomic read/modify\r
- * accesses. In this way, there is no risk of an IRQ occurring between\r
- * the read and the modify access.\r
- *\r
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral\r
- * @param GPIO_Pin: specifies the port bit to be written.\r
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
- * @param PinState: specifies the value to be written to the selected bit.\r
- * This parameter can be one of the GPIO_PinState enum values:\r
- * @arg GPIO_PIN_RESET: to clear the port pin\r
- * @arg GPIO_PIN_SET: to set the port pin\r
- * @retval None\r
- */\r
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
- assert_param(IS_GPIO_PIN_ACTION(PinState));\r
-\r
- if (PinState != GPIO_PIN_RESET)\r
- {\r
- GPIOx->BSRR = GPIO_Pin;\r
- }\r
- else\r
- {\r
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Toggles the specified GPIO pin\r
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral\r
- * @param GPIO_Pin: Specifies the pins to be toggled.\r
- * @retval None\r
- */\r
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
-\r
- GPIOx->ODR ^= GPIO_Pin;\r
-}\r
-\r
-/**\r
-* @brief Locks GPIO Pins configuration registers.\r
-* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence\r
-* has been applied on a port bit, it is no longer possible to modify the value of the port bit until\r
-* the next reset.\r
-* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral\r
-* @param GPIO_Pin: specifies the port bit to be locked.\r
-* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
-* @retval None\r
-*/\r
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)\r
-{\r
- __IO uint32_t tmp = GPIO_LCKR_LCKK;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));\r
- assert_param(IS_GPIO_PIN(GPIO_Pin));\r
-\r
- /* Apply lock key write sequence */\r
- SET_BIT(tmp, GPIO_Pin);\r
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
- GPIOx->LCKR = tmp;\r
- /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r
- GPIOx->LCKR = GPIO_Pin;\r
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
- GPIOx->LCKR = tmp;\r
- /* Read LCKK bit*/\r
- tmp = GPIOx->LCKR;\r
-\r
- if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))\r
- {\r
- return HAL_OK;\r
- }\r
- else\r
- {\r
- return HAL_ERROR;\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles EXTI interrupt request.\r
- * @param GPIO_Pin: Specifies the pins connected EXTI line\r
- * @retval None\r
- */\r
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r
-{\r
- /* EXTI line interrupt detected */\r
- if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)\r
- {\r
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r
- HAL_GPIO_EXTI_Callback(GPIO_Pin);\r
- }\r
-}\r
-\r
-/**\r
- * @brief EXTI line detection callbacks.\r
- * @param GPIO_Pin: Specifies the pins connected EXTI line\r
- * @retval None\r
- */\r
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(GPIO_Pin);\r
- /* NOTE: This function Should not be modified, when the callback is needed,\r
- the HAL_GPIO_EXTI_Callback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_GPIO_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_gpio_ex.c\r
- * @author MCD Application Team\r
- * @brief GPIO Extension HAL module driver.\r
- * This file provides firmware functions to manage the following\r
- * functionalities of the General Purpose Input/Output (GPIO) extension peripheral.\r
- * + Extended features functions\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### GPIO Peripheral extension features #####\r
- ==============================================================================\r
- [..] GPIO module on STM32F1 family, manage also the AFIO register:\r
- (+) Possibility to use the EVENTOUT Cortex feature\r
-\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..] This driver provides functions to use EVENTOUT Cortex feature\r
- (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()\r
- (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()\r
- (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()\r
-\r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIOEx GPIOEx\r
- * @brief GPIO HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_GPIO_MODULE_ENABLED\r
-\r
-/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions\r
- * @brief Extended features functions\r
- *\r
-@verbatim\r
- ==============================================================================\r
- ##### Extended features functions #####\r
- ==============================================================================\r
- [..] This section provides functions allowing to:\r
- (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()\r
- (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()\r
- (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.\r
- * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.\r
- * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.\r
- * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.\r
- * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.\r
- * @retval None\r
- */\r
-void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)\r
-{\r
- /* Verify the parameters */\r
- assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));\r
- assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));\r
-\r
- /* Apply the new configuration */\r
- MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource));\r
-}\r
-\r
-/**\r
- * @brief Enables the Event Output.\r
- * @retval None\r
- */\r
-void HAL_GPIOEx_EnableEventout(void)\r
-{\r
- SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);\r
-}\r
-\r
-/**\r
- * @brief Disables the Event Output.\r
- * @retval None\r
- */\r
-void HAL_GPIOEx_DisableEventout(void)\r
-{\r
- CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_GPIO_MODULE_ENABLED */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_pwr.c\r
- * @author MCD Application Team\r
- * @brief PWR HAL module driver.\r
- *\r
- * This file provides firmware functions to manage the following\r
- * functionalities of the Power Controller (PWR) peripheral:\r
- * + Initialization/de-initialization functions\r
- * + Peripheral Control functions \r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup PWR PWR\r
- * @brief PWR HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_PWR_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Private_Constants PWR Private Constants\r
- * @{\r
- */\r
- \r
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r
- * @{\r
- */ \r
-#define PVD_MODE_IT 0x00010000U\r
-#define PVD_MODE_EVT 0x00020000U\r
-#define PVD_RISING_EDGE 0x00000001U\r
-#define PVD_FALLING_EDGE 0x00000002U\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup PWR_register_alias_address PWR Register alias address\r
- * @{\r
- */ \r
-/* ------------- PWR registers bit address in the alias region ---------------*/\r
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
-#define PWR_CR_OFFSET 0x00U\r
-#define PWR_CSR_OFFSET 0x04U\r
-#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)\r
-#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup PWR_CR_register_alias PWR CR Register alias address\r
- * @{\r
- */ \r
-/* --- CR Register ---*/\r
-/* Alias word address of LPSDSR bit */\r
-#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos\r
-#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))\r
-\r
-/* Alias word address of DBP bit */\r
-#define DBP_BIT_NUMBER PWR_CR_DBP_Pos\r
-#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))\r
-\r
-/* Alias word address of PVDE bit */\r
-#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos\r
-#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address\r
- * @{\r
- */\r
-\r
-/* --- CSR Register ---*/\r
-/* Alias word address of EWUP1 bit */\r
-#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup PWR_Private_Functions PWR Private Functions\r
- * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)\r
- * @{\r
- */\r
-static void PWR_OverloadWfe(void);\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-__NOINLINE\r
-static void PWR_OverloadWfe(void)\r
-{\r
- __asm volatile( "wfe" );\r
- __asm volatile( "nop" );\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r
- * @brief Initialization and de-initialization functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
- [..]\r
- After reset, the backup domain (RTC registers, RTC backup data\r
- registers) is protected against possible unwanted\r
- write accesses.\r
- To enable access to the RTC Domain and RTC registers, proceed as follows:\r
- (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
- __HAL_RCC_PWR_CLK_ENABLE() macro.\r
- (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the PWR peripheral registers to their default reset values. \r
- * @retval None\r
- */\r
-void HAL_PWR_DeInit(void)\r
-{\r
- __HAL_RCC_PWR_FORCE_RESET();\r
- __HAL_RCC_PWR_RELEASE_RESET();\r
-}\r
-\r
-/**\r
- * @brief Enables access to the backup domain (RTC registers, RTC\r
- * backup data registers ).\r
- * @note If the HSE divided by 128 is used as the RTC clock, the\r
- * Backup Domain Access should be kept enabled.\r
- * @retval None\r
- */\r
-void HAL_PWR_EnableBkUpAccess(void)\r
-{\r
- /* Enable access to RTC and backup registers */\r
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;\r
-}\r
-\r
-/**\r
- * @brief Disables access to the backup domain (RTC registers, RTC\r
- * backup data registers).\r
- * @note If the HSE divided by 128 is used as the RTC clock, the\r
- * Backup Domain Access should be kept enabled.\r
- * @retval None\r
- */\r
-void HAL_PWR_DisableBkUpAccess(void)\r
-{\r
- /* Disable access to RTC and backup registers */\r
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions \r
- * @brief Low Power modes configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Peripheral Control functions #####\r
- ===============================================================================\r
- \r
- *** PVD configuration ***\r
- =========================\r
- [..]\r
- (+) The PVD is used to monitor the VDD power supply by comparing it to a\r
- threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
-\r
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower\r
- than the PVD threshold. This event is internally connected to the EXTI\r
- line16 and can generate an interrupt if enabled. This is done through\r
- __HAL_PVD_EXTI_ENABLE_IT() macro.\r
- (+) The PVD is stopped in Standby mode.\r
-\r
- *** WakeUp pin configuration ***\r
- ================================\r
- [..]\r
- (+) WakeUp pin is used to wake up the system from Standby mode. This pin is\r
- forced in input pull-down configuration and is active on rising edges.\r
- (+) There is one WakeUp pin:\r
- WakeUp Pin 1 on PA.00.\r
-\r
- [..]\r
-\r
- *** Low Power modes configuration ***\r
- =====================================\r
- [..]\r
- The device features 3 low-power modes:\r
- (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like \r
- NVIC, SysTick, etc. are kept running\r
- (+) Stop mode: All clocks are stopped\r
- (+) Standby mode: 1.8V domain powered off\r
- \r
- \r
- *** Sleep mode ***\r
- ==================\r
- [..]\r
- (+) Entry:\r
- The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)\r
- functions with\r
- (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
- (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
- \r
- (+) Exit:\r
- (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt\r
- controller (NVIC) can wake up the device from Sleep mode.\r
- (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.\r
- (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)\r
- (+++) Any EXTI Line (Internal or External) configured in Event mode\r
-\r
- *** Stop mode ***\r
- =================\r
- [..]\r
- The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral\r
- clock gating. The voltage regulator can be configured either in normal or low-power mode.\r
- In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC \r
- oscillators are disabled. SRAM and register contents are preserved.\r
- In Stop mode, all I/O pins keep the same state as in Run mode.\r
-\r
- (+) Entry:\r
- The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )\r
- function with:\r
- (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.\r
- (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.\r
- (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction\r
- (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction\r
- (+) Exit:\r
- (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured\r
- (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.\r
-\r
- *** Standby mode ***\r
- ====================\r
- [..]\r
- The Standby mode allows to achieve the lowest power consumption. It is based on the\r
- Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is \r
- consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also \r
- switched off. SRAM and register contents are lost except for registers in the Backup domain \r
- and Standby circuitry\r
- \r
- (+) Entry:\r
- (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\r
- (+) Exit:\r
- (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in \r
- NRSTpin, IWDG Reset\r
-\r
- *** Auto-wakeup (AWU) from low-power mode ***\r
- =============================================\r
- [..]\r
- \r
- (+) The MCU can be woken up from low-power mode by an RTC Alarm event, \r
- without depending on an external interrupt (Auto-wakeup mode).\r
- \r
- (+) RTC auto-wakeup (AWU) from the Stop and Standby modes\r
-\r
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to \r
- configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r
-\r
- *** PWR Workarounds linked to Silicon Limitation ***\r
- ====================================================\r
- [..]\r
- Below the list of all silicon limitations known on STM32F1xx prouct.\r
-\r
- (#)Workarounds Implemented inside PWR HAL Driver\r
- (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function \r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
- * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration\r
- * information for the PVD.\r
- * @note Refer to the electrical characteristics of your device datasheet for\r
- * more details about the voltage threshold corresponding to each\r
- * detection level.\r
- * @retval None\r
- */\r
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
- assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
-\r
- /* Set PLS[7:5] bits according to PVDLevel value */\r
- MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);\r
- \r
- /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
- __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
- __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \r
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r
-\r
- /* Configure interrupt mode */\r
- if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
- {\r
- __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
- }\r
- \r
- /* Configure event mode */\r
- if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
- {\r
- __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
- }\r
- \r
- /* Configure the edge */\r
- if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
- {\r
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
- }\r
- \r
- if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
- {\r
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables the Power Voltage Detector(PVD).\r
- * @retval None\r
- */\r
-void HAL_PWR_EnablePVD(void)\r
-{\r
- /* Enable the power voltage detector */\r
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;\r
-}\r
-\r
-/**\r
- * @brief Disables the Power Voltage Detector(PVD).\r
- * @retval None\r
- */\r
-void HAL_PWR_DisablePVD(void)\r
-{\r
- /* Disable the power voltage detector */\r
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;\r
-}\r
-\r
-/**\r
- * @brief Enables the WakeUp PINx functionality.\r
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_WAKEUP_PIN1\r
- * @retval None\r
- */\r
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
- /* Enable the EWUPx pin */\r
- *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;\r
-}\r
-\r
-/**\r
- * @brief Disables the WakeUp PINx functionality.\r
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_WAKEUP_PIN1\r
- * @retval None\r
- */\r
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
- /* Disable the EWUPx pin */\r
- *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;\r
-}\r
-\r
-/**\r
- * @brief Enters Sleep mode.\r
- * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\r
- * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software\r
- * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.\r
- * When WFI entry is used, tick interrupt have to be disabled if not desired as \r
- * the interrupt wake up source.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
- * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
- * @retval None\r
- */\r
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
-{\r
- /* Check the parameters */\r
- /* No check on Regulator because parameter not used in SLEEP mode */\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(Regulator);\r
-\r
- assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
-\r
- /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-\r
- /* Select SLEEP mode entry -------------------------------------------------*/\r
- if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
- {\r
- /* Request Wait For Interrupt */\r
- __WFI();\r
- }\r
- else\r
- {\r
- /* Request Wait For Event */\r
- __SEV();\r
- __WFE();\r
- __WFE();\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enters Stop mode. \r
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
- * @note When exiting Stop mode by using an interrupt or a wakeup event,\r
- * HSI RC oscillator is selected as system clock.\r
- * @note When the voltage regulator operates in low power mode, an additional\r
- * startup delay is incurred when waking up from Stop mode. \r
- * By keeping the internal regulator ON during Stop mode, the consumption\r
- * is higher although the startup time is reduced. \r
- * @param Regulator: Specifies the regulator state in Stop mode.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r
- * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r
- * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\r
- * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction \r
- * @retval None\r
- */\r
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_PWR_REGULATOR(Regulator));\r
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
-\r
- /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ \r
- CLEAR_BIT(PWR->CR, PWR_CR_PDDS);\r
-\r
- /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */\r
- MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);\r
-\r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-\r
- /* Select Stop mode entry --------------------------------------------------*/\r
- if(STOPEntry == PWR_STOPENTRY_WFI)\r
- {\r
- /* Request Wait For Interrupt */\r
- __WFI();\r
- }\r
- else\r
- {\r
- /* Request Wait For Event */\r
- __SEV();\r
- PWR_OverloadWfe(); /* WFE redefine locally */\r
- PWR_OverloadWfe(); /* WFE redefine locally */\r
- }\r
- /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-}\r
-\r
-/**\r
- * @brief Enters Standby mode.\r
- * @note In Standby mode, all I/O pins are high impedance except for:\r
- * - Reset pad (still available) \r
- * - TAMPER pin if configured for tamper or calibration out.\r
- * - WKUP pin (PA0) if enabled.\r
- * @retval None\r
- */\r
-void HAL_PWR_EnterSTANDBYMode(void)\r
-{\r
- /* Select Standby mode */\r
- SET_BIT(PWR->CR, PWR_CR_PDDS);\r
-\r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
-\r
- /* This option is used to ensure that store operations are completed */\r
-#if defined ( __CC_ARM)\r
- __force_stores();\r
-#endif\r
- /* Request Wait For Interrupt */\r
- __WFI();\r
-}\r
-\r
-\r
-/**\r
- * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. \r
- * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
- * re-enters SLEEP mode when an interruption handling is over.\r
- * Setting this bit is useful when the processor is expected to run only on\r
- * interruptions handling. \r
- * @retval None\r
- */\r
-void HAL_PWR_EnableSleepOnExit(void)\r
-{\r
- /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
-}\r
-\r
-\r
-/**\r
- * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. \r
- * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
- * re-enters SLEEP mode when an interruption handling is over. \r
- * @retval None\r
- */\r
-void HAL_PWR_DisableSleepOnExit(void)\r
-{\r
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
-}\r
-\r
-\r
-/**\r
- * @brief Enables CORTEX M3 SEVONPEND bit. \r
- * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes \r
- * WFE to wake up when an interrupt moves from inactive to pended.\r
- * @retval None\r
- */\r
-void HAL_PWR_EnableSEVOnPend(void)\r
-{\r
- /* Set SEVONPEND bit of Cortex System Control Register */\r
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
-}\r
-\r
-\r
-/**\r
- * @brief Disables CORTEX M3 SEVONPEND bit. \r
- * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes \r
- * WFE to wake up when an interrupt moves from inactive to pended. \r
- * @retval None\r
- */\r
-void HAL_PWR_DisableSEVOnPend(void)\r
-{\r
- /* Clear SEVONPEND bit of Cortex System Control Register */\r
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
-}\r
-\r
-\r
-\r
-/**\r
- * @brief This function handles the PWR PVD interrupt request.\r
- * @note This API should be called under the PVD_IRQHandler().\r
- * @retval None\r
- */\r
-void HAL_PWR_PVD_IRQHandler(void)\r
-{\r
- /* Check PWR exti flag */\r
- if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
- {\r
- /* PWR PVD interrupt user callback */\r
- HAL_PWR_PVDCallback();\r
-\r
- /* Clear PWR Exti pending bit */\r
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
- }\r
-}\r
-\r
-/**\r
- * @brief PWR PVD interrupt callback\r
- * @retval None\r
- */\r
-__weak void HAL_PWR_PVDCallback(void)\r
-{\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_PWR_PVDCallback could be implemented in the user file\r
- */ \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_PWR_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_rcc.c\r
- * @author MCD Application Team\r
- * @brief RCC HAL module driver.\r
- * This file provides firmware functions to manage the following\r
- * functionalities of the Reset and Clock Control (RCC) peripheral:\r
- * + Initialization and de-initialization functions\r
- * + Peripheral Control functions\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### RCC specific features #####\r
- ==============================================================================\r
- [..]\r
- After reset the device is running from Internal High Speed oscillator\r
- (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, \r
- and all peripherals are off except internal SRAM, Flash and JTAG.\r
- (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;\r
- all peripherals mapped on these buses are running at HSI speed.\r
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
- (+) All GPIOs are in input floating state, except the JTAG pins which\r
- are assigned to be used for debug purpose.\r
- [..] Once the device started from reset, the user application has to:\r
- (+) Configure the clock source to be used to drive the System clock\r
- (if the application needs higher frequency/performance)\r
- (+) Configure the System clock frequency and Flash settings \r
- (+) Configure the AHB and APB buses prescalers\r
- (+) Enable the clock for the peripheral(s) to be used\r
- (+) Configure the clock source(s) for peripherals whose clocks are not\r
- derived from the System clock (I2S, RTC, ADC, USB OTG FS) \r
-\r
- ##### RCC Limitations #####\r
- ==============================================================================\r
- [..]\r
- A delay between an RCC peripheral clock enable and the effective peripheral \r
- enabling should be taken into account in order to manage the peripheral read/write \r
- from/to registers.\r
- (+) This delay depends on the peripheral mapping.\r
- (++) AHB & APB peripherals, 1 dummy read is necessary\r
-\r
- [..] \r
- Workarounds:\r
- (#) For AHB & APB peripherals, a dummy read to the peripheral register has been\r
- inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.\r
-\r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ****************************************************************************** \r
-*/\r
- \r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC RCC\r
-* @brief RCC HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_RCC_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @defgroup RCC_Private_Constants RCC Private Constants\r
- * @{\r
- */\r
-/**\r
- * @}\r
- */\r
-/* Private macro -------------------------------------------------------------*/\r
-/** @defgroup RCC_Private_Macros RCC Private Macros\r
- * @{\r
- */\r
-\r
-#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()\r
-#define MCO1_GPIO_PORT GPIOA\r
-#define MCO1_PIN GPIO_PIN_8\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/** @defgroup RCC_Private_Variables RCC Private Variables\r
- * @{\r
- */\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-static void RCC_Delay(uint32_t mdelay);\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Exported_Functions RCC Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions \r
- * @brief Initialization and Configuration functions \r
- *\r
- @verbatim \r
- ===============================================================================\r
- ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
- [..]\r
- This section provides functions allowing to configure the internal/external oscillators\r
- (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1\r
- and APB2).\r
-\r
- [..] Internal/external clock and PLL configuration\r
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through\r
- the PLL as System clock source.\r
- (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC\r
- clock source.\r
-\r
- (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or\r
- through the PLL as System clock source. Can be used also as RTC clock source.\r
-\r
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.\r
-\r
- (#) PLL (clocked by HSI or HSE), featuring different output clocks:\r
- (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)\r
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)\r
-\r
- (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()\r
- and if a HSE clock failure occurs(HSE used directly or through PLL as System \r
- clock source), the System clocks automatically switched to HSI and an interrupt\r
- is generated if enabled. The interrupt is linked to the Cortex-M3 NMI \r
- (Non-Maskable Interrupt) exception vector.\r
-\r
- (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,\r
- HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x\r
-\r
- [..] System, AHB and APB buses clocks configuration\r
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,\r
- HSE and PLL.\r
- The AHB clock (HCLK) is derived from System clock through configurable\r
- prescaler and used to clock the CPU, memory and peripherals mapped\r
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived\r
- from AHB clock through configurable prescalers and used to clock\r
- the peripherals mapped on these buses. You can use\r
- "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.\r
-\r
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
- (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock\r
- divided by 128. \r
- (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz\r
- to work correctly. This clock is derived of the main PLL through PLL Multiplier.\r
- (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK\r
- (+@) IWDG clock which is always the LSI clock.\r
-\r
- (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.\r
- For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. \r
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.\r
- @endverbatim\r
- * @{\r
- */\r
- \r
-/*\r
- Additional consideration on the SYSCLK based on Latency settings:\r
- +-----------------------------------------------+\r
- | Latency | SYSCLK clock frequency (MHz) |\r
- |---------------|-------------------------------|\r
- |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |\r
- |---------------|-------------------------------|\r
- |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |\r
- |---------------|-------------------------------|\r
- |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |\r
- +-----------------------------------------------+\r
- */\r
-\r
-/**\r
- * @brief Resets the RCC clock configuration to the default reset state.\r
- * @note The default reset state of the clock configuration is given below:\r
- * - HSI ON and used as system clock source\r
- * - HSE, PLL, PLL2 and PLL3 are OFF\r
- * - AHB, APB1 and APB2 prescaler set to 1.\r
- * - CSS and MCO1 OFF\r
- * - All interrupts disabled\r
- * - All flags are cleared\r
- * @note This function does not modify the configuration of the\r
- * - Peripheral clocks\r
- * - LSI, LSE and RTC clocks\r
- * @retval HAL_StatusTypeDef\r
- */\r
-HAL_StatusTypeDef HAL_RCC_DeInit(void)\r
-{\r
- uint32_t tickstart;\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Set HSION bit */\r
- SET_BIT(RCC->CR, RCC_CR_HSION);\r
-\r
- /* Wait till HSI is ready */\r
- while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)\r
- {\r
- if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Set HSITRIM bits to the reset value */\r
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Reset CFGR register */\r
- CLEAR_REG(RCC->CFGR);\r
-\r
- /* Wait till clock switch is ready */\r
- while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)\r
- {\r
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Update the SystemCoreClock global variable */\r
- SystemCoreClock = HSI_VALUE;\r
-\r
- /* Adapt Systick interrupt period */\r
- if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Second step is to clear PLLON bit */\r
- CLEAR_BIT(RCC->CR, RCC_CR_PLLON);\r
-\r
- /* Wait till PLL is disabled */\r
- while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)\r
- {\r
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Ensure to reset PLLSRC and PLLMUL bits */\r
- CLEAR_REG(RCC->CFGR);\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Reset HSEON & CSSON bits */\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);\r
-\r
- /* Wait till HSE is disabled */\r
- while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)\r
- {\r
- if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Reset HSEBYP bit */\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\r
-\r
-#if defined(RCC_PLL2_SUPPORT)\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Clear PLL2ON bit */\r
- CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);\r
-\r
- /* Wait till PLL2 is disabled */\r
- while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET)\r
- {\r
- if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-#endif /* RCC_PLL2_SUPPORT */\r
-\r
-#if defined(RCC_PLLI2S_SUPPORT)\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Clear PLL3ON bit */\r
- CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);\r
-\r
- /* Wait till PLL3 is disabled */\r
- while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET)\r
- {\r
- if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-#endif /* RCC_PLLI2S_SUPPORT */\r
-\r
-#if defined(RCC_CFGR2_PREDIV1)\r
- /* Reset CFGR2 register */\r
- CLEAR_REG(RCC->CFGR2);\r
-#endif /* RCC_CFGR2_PREDIV1 */\r
-\r
- /* Reset all CSR flags */\r
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);\r
-\r
- /* Disable all interrupts */\r
- CLEAR_REG(RCC->CIR);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the RCC Oscillators according to the specified parameters in the\r
- * RCC_OscInitTypeDef.\r
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\r
- * contains the configuration information for the RCC Oscillators.\r
- * @note The PLL is not disabled when used as system clock.\r
- * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)\r
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
- * supported by this macro. User should request a transition to LSE Off\r
- * first and then LSE On or LSE Bypass.\r
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
- * supported by this macro. User should request a transition to HSE Off\r
- * first and then HSE On or HSE Bypass.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
-{\r
- uint32_t tickstart = 0U;\r
- \r
- /* Check the parameters */\r
- assert_param(RCC_OscInitStruct != NULL);\r
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
- \r
- /*------------------------------- HSE Configuration ------------------------*/\r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
- \r
- /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */\r
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) \r
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))\r
- {\r
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- else\r
- {\r
- /* Set the new HSE configuration ---------------------------------------*/\r
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
- \r
-\r
- /* Check the HSE State */\r
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
- {\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till HSE is ready */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till HSE is disabled */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- /*----------------------------- HSI Configuration --------------------------*/ \r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
-\r
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ \r
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) \r
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))\r
- {\r
- /* When HSI is used as system clock it will not disabled */\r
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\r
- {\r
- return HAL_ERROR;\r
- }\r
- /* Otherwise, just the calibration is allowed */\r
- else\r
- {\r
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
- }\r
- }\r
- else\r
- {\r
- /* Check the HSI State */\r
- if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)\r
- {\r
- /* Enable the Internal High Speed oscillator (HSI). */\r
- __HAL_RCC_HSI_ENABLE();\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till HSI is ready */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
- }\r
- else\r
- {\r
- /* Disable the Internal High Speed oscillator (HSI). */\r
- __HAL_RCC_HSI_DISABLE();\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till HSI is disabled */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- /*------------------------------ LSI Configuration -------------------------*/ \r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
-\r
- /* Check the LSI State */\r
- if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)\r
- {\r
- /* Enable the Internal Low Speed oscillator (LSI). */\r
- __HAL_RCC_LSI_ENABLE();\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till LSI is ready */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- /* To have a fully stabilized clock in the specified range, a software delay of 1ms \r
- should be added.*/\r
- RCC_Delay(1);\r
- }\r
- else\r
- {\r
- /* Disable the Internal Low Speed oscillator (LSI). */\r
- __HAL_RCC_LSI_DISABLE();\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till LSI is disabled */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- /*------------------------------ LSE Configuration -------------------------*/ \r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
- {\r
- FlagStatus pwrclkchanged = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
-\r
- /* Update LSE configuration in Backup Domain control register */\r
- /* Requires to enable write access to Backup Domain of necessary */\r
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
- {\r
- __HAL_RCC_PWR_CLK_ENABLE();\r
- pwrclkchanged = SET;\r
- }\r
-\r
- if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\r
- {\r
- /* Enable write access to Backup domain */\r
- SET_BIT(PWR->CR, PWR_CR_DBP);\r
-\r
- /* Wait for Backup domain Write protection disable */\r
- tickstart = HAL_GetTick();\r
-\r
- while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\r
- {\r
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- /* Set the new LSE configuration -----------------------------------------*/\r
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
- /* Check the LSE State */\r
- if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)\r
- {\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till LSE is ready */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till LSE is disabled */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- /* Require to disable power clock if necessary */\r
- if(pwrclkchanged == SET)\r
- {\r
- __HAL_RCC_PWR_CLK_DISABLE();\r
- }\r
- }\r
-\r
-#if defined(RCC_CR_PLL2ON)\r
- /*-------------------------------- PLL2 Configuration -----------------------*/\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));\r
- if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)\r
- {\r
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system \r
- clock (i.e. it is used as PLL clock entry that is used as system clock). */\r
- if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \\r
- (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \\r
- ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));\r
- assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));\r
-\r
- /* Prediv2 can be written only when the PLLI2S is disabled. */\r
- /* Return an error only if new value is different from the programmed value */\r
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \\r
- (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))\r
- {\r
- return HAL_ERROR;\r
- }\r
- \r
- /* Disable the main PLL2. */\r
- __HAL_RCC_PLL2_DISABLE();\r
- \r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till PLL2 is disabled */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Configure the HSE prediv2 factor --------------------------------*/\r
- __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);\r
-\r
- /* Configure the main PLL2 multiplication factors. */\r
- __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);\r
-\r
- /* Enable the main PLL2. */\r
- __HAL_RCC_PLL2_ENABLE();\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till PLL2 is ready */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Set PREDIV1 source to HSE */\r
- CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);\r
-\r
- /* Disable the main PLL2. */\r
- __HAL_RCC_PLL2_DISABLE();\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till PLL2 is disabled */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- }\r
-\r
-#endif /* RCC_CR_PLL2ON */\r
- /*-------------------------------- PLL Configuration -----------------------*/\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r
- {\r
- /* Check if the PLL is used as system clock or not */\r
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
- { \r
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
- assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));\r
-\r
- /* Disable the main PLL. */\r
- __HAL_RCC_PLL_DISABLE();\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till PLL is disabled */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Configure the HSE prediv factor --------------------------------*/\r
- /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */\r
- if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)\r
- {\r
- /* Check the parameter */\r
- assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));\r
-#if defined(RCC_CFGR2_PREDIV1SRC)\r
- assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));\r
-\r
- /* Set PREDIV1 source */\r
- SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);\r
-#endif /* RCC_CFGR2_PREDIV1SRC */\r
-\r
- /* Set PREDIV1 Value */\r
- __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);\r
- }\r
-\r
- /* Configure the main PLL clock source and multiplication factors. */\r
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
- RCC_OscInitStruct->PLL.PLLMUL);\r
- /* Enable the main PLL. */\r
- __HAL_RCC_PLL_ENABLE();\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till PLL is ready */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Disable the main PLL. */\r
- __HAL_RCC_PLL_DISABLE();\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till PLL is disabled */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- else\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- \r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the CPU, AHB and APB buses clocks according to the specified \r
- * parameters in the RCC_ClkInitStruct.\r
- * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that\r
- * contains the configuration information for the RCC peripheral.\r
- * @param FLatency FLASH Latency \r
- * The value of this parameter depend on device used within the same series\r
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency \r
- * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function\r
- *\r
- * @note The HSI is used (enabled by hardware) as system clock source after\r
- * start-up from Reset, wake-up from STOP and STANDBY mode, or in case\r
- * of failure of the HSE used directly or indirectly as system clock\r
- * (if the Clock Security System CSS is enabled).\r
- * \r
- * @note A switch from one clock source to another occurs only if the target\r
- * clock source is ready (clock stable after start-up delay or PLL locked). \r
- * If a clock source which is not yet ready is selected, the switch will\r
- * occur when the clock source will be ready. \r
- * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is\r
- * currently used as system clock source.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)\r
-{\r
- uint32_t tickstart = 0U;\r
-\r
- /* Check the parameters */\r
- assert_param(RCC_ClkInitStruct != NULL);\r
- assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r
- assert_param(IS_FLASH_LATENCY(FLatency));\r
-\r
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY) \r
- must be correctly programmed according to the frequency of the CPU clock \r
- (HCLK) of the device. */\r
-\r
-#if defined(FLASH_ACR_LATENCY)\r
- /* Increasing the number of wait states because of higher CPU frequency */\r
- if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))\r
- { \r
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
- __HAL_FLASH_SET_LATENCY(FLatency);\r
-\r
- /* Check that the new number of wait states is taken into account to access the Flash\r
- memory by reading the FLASH_ACR register */\r
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
-\r
-#endif /* FLASH_ACR_LATENCY */\r
- /*-------------------------- HCLK Configuration --------------------------*/\r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
- {\r
- /* Set the highest APBx dividers in order to ensure that we do not go through\r
- a non-spec phase whatever we decrease or increase HCLK. */\r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
- {\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);\r
- }\r
-\r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
- {\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));\r
- }\r
-\r
- /* Set the new HCLK clock divider */\r
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
- }\r
-\r
- /*------------------------- SYSCLK Configuration ---------------------------*/ \r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
- { \r
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
-\r
- /* HSE is selected as System Clock Source */\r
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
- {\r
- /* Check the HSE ready flag */ \r
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- /* PLL is selected as System Clock Source */\r
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
- {\r
- /* Check the PLL ready flag */ \r
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- /* HSI is selected as System Clock Source */\r
- else\r
- {\r
- /* Check the HSI ready flag */ \r
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);\r
-\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
-\r
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
- {\r
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)\r
- {\r
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
- {\r
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
- {\r
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)\r
- {\r
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- } \r
- } \r
-#if defined(FLASH_ACR_LATENCY)\r
- /* Decreasing the number of wait states because of lower CPU frequency */\r
- if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))\r
- { \r
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
- __HAL_FLASH_SET_LATENCY(FLatency);\r
-\r
- /* Check that the new number of wait states is taken into account to access the Flash\r
- memory by reading the FLASH_ACR register */\r
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)\r
- {\r
- return HAL_ERROR;\r
- }\r
- } \r
-#endif /* FLASH_ACR_LATENCY */\r
-\r
- /*-------------------------- PCLK1 Configuration ---------------------------*/ \r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
- {\r
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r
- }\r
- \r
- /*-------------------------- PCLK2 Configuration ---------------------------*/ \r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
- {\r
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));\r
- }\r
-\r
- /* Update the SystemCoreClock global variable */\r
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];\r
-\r
- /* Configure the source of time base considering new system clocks settings*/\r
- HAL_InitTick (TICK_INT_PRIORITY);\r
- \r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions\r
- * @brief RCC clocks control functions\r
- *\r
- @verbatim \r
- ===============================================================================\r
- ##### Peripheral Control functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection provides a set of functions allowing to control the RCC Clocks \r
- frequencies.\r
-\r
- @endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Selects the clock source to output on MCO pin.\r
- * @note MCO pin should be configured in alternate function mode.\r
- * @param RCC_MCOx specifies the output direction for the clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).\r
- * @param RCC_MCOSource specifies the clock source to output.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock\r
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock\r
- @if STM32F105xC\r
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source\r
- @endif\r
- @if STM32F107xC\r
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source\r
- @endif\r
- * @param RCC_MCODiv specifies the MCO DIV.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCODIV_1 no division applied to MCO clock\r
- * @retval None\r
- */\r
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r
-{\r
- GPIO_InitTypeDef gpio = {0U};\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_MCO(RCC_MCOx));\r
- assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r
-\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(RCC_MCOx);\r
- UNUSED(RCC_MCODiv);\r
-\r
- /* Configure the MCO1 pin in alternate function mode */\r
- gpio.Mode = GPIO_MODE_AF_PP;\r
- gpio.Speed = GPIO_SPEED_FREQ_HIGH;\r
- gpio.Pull = GPIO_NOPULL;\r
- gpio.Pin = MCO1_PIN;\r
-\r
- /* MCO1 Clock Enable */\r
- MCO1_CLK_ENABLE();\r
-\r
- HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);\r
-\r
- /* Configure the MCO clock source */\r
- __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);\r
-}\r
-\r
-/**\r
- * @brief Enables the Clock Security System.\r
- * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
- * is automatically disabled and an interrupt is generated to inform the\r
- * software about the failure (Clock Security System Interrupt, CSSI),\r
- * allowing the MCU to perform rescue operations. The CSSI is linked to \r
- * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. \r
- * @retval None\r
- */\r
-void HAL_RCC_EnableCSS(void)\r
-{\r
- *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;\r
-}\r
-\r
-/**\r
- * @brief Disables the Clock Security System.\r
- * @retval None\r
- */\r
-void HAL_RCC_DisableCSS(void)\r
-{\r
- *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;\r
-}\r
-\r
-/**\r
- * @brief Returns the SYSCLK frequency \r
- * @note The system frequency computed by this function is not the real \r
- * frequency in the chip. It is calculated based on the predefined \r
- * constant and the selected clock source:\r
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
- * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE\r
- * divided by PREDIV factor(**)\r
- * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE\r
- * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.\r
- * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value\r
- * 8 MHz) but the real value may vary depending on the variations\r
- * in voltage and temperature.\r
- * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value\r
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
- * frequency of the crystal used. Otherwise, this function may\r
- * have wrong result.\r
- * \r
- * @note The result of this function could be not correct when using fractional\r
- * value for HSE crystal.\r
- * \r
- * @note This function can be used by the user application to compute the \r
- * baud-rate for the communication peripherals or configure other parameters.\r
- * \r
- * @note Each time SYSCLK changes, this function must be called to update the\r
- * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r
- * \r
- * @retval SYSCLK frequency\r
- */\r
-uint32_t HAL_RCC_GetSysClockFreq(void)\r
-{\r
-#if defined(RCC_CFGR2_PREDIV1SRC)\r
- const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};\r
- const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};\r
-#else\r
- const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};\r
-#if defined(RCC_CFGR2_PREDIV1)\r
- const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};\r
-#else\r
- const uint8_t aPredivFactorTable[2] = {1, 2};\r
-#endif /*RCC_CFGR2_PREDIV1*/\r
-\r
-#endif\r
- uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;\r
- uint32_t sysclockfreq = 0U;\r
-#if defined(RCC_CFGR2_PREDIV1SRC)\r
- uint32_t prediv2 = 0U, pll2mul = 0U;\r
-#endif /*RCC_CFGR2_PREDIV1SRC*/\r
-\r
- tmpreg = RCC->CFGR;\r
-\r
- /* Get SYSCLK source -------------------------------------------------------*/\r
- switch (tmpreg & RCC_CFGR_SWS)\r
- {\r
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */\r
- {\r
- sysclockfreq = HSE_VALUE;\r
- break;\r
- }\r
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */\r
- {\r
- pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];\r
- if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)\r
- {\r
-#if defined(RCC_CFGR2_PREDIV1)\r
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];\r
-#else\r
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];\r
-#endif /*RCC_CFGR2_PREDIV1*/\r
-#if defined(RCC_CFGR2_PREDIV1SRC)\r
-\r
- if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))\r
- {\r
- /* PLL2 selected as Prediv1 source */\r
- /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */\r
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;\r
- pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;\r
- pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv));\r
- }\r
- else\r
- {\r
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */\r
- pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);\r
- }\r
-\r
- /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */\r
- /* In this case need to divide pllclk by 2 */\r
- if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])\r
- {\r
- pllclk = pllclk / 2;\r
- }\r
-#else\r
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */\r
- pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);\r
-#endif /*RCC_CFGR2_PREDIV1SRC*/\r
- }\r
- else\r
- {\r
- /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */\r
- pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);\r
- }\r
- sysclockfreq = pllclk;\r
- break;\r
- }\r
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */\r
- default: /* HSI used as system clock */\r
- {\r
- sysclockfreq = HSI_VALUE;\r
- break;\r
- }\r
- }\r
- return sysclockfreq;\r
-}\r
-\r
-/**\r
- * @brief Returns the HCLK frequency \r
- * @note Each time HCLK changes, this function must be called to update the\r
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.\r
- * \r
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency \r
- * and updated within this function\r
- * @retval HCLK frequency\r
- */\r
-uint32_t HAL_RCC_GetHCLKFreq(void)\r
-{\r
- return SystemCoreClock;\r
-}\r
-\r
-/**\r
- * @brief Returns the PCLK1 frequency \r
- * @note Each time PCLK1 changes, this function must be called to update the\r
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
- * @retval PCLK1 frequency\r
- */\r
-uint32_t HAL_RCC_GetPCLK1Freq(void)\r
-{\r
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);\r
-} \r
-\r
-/**\r
- * @brief Returns the PCLK2 frequency \r
- * @note Each time PCLK2 changes, this function must be called to update the\r
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r
- * @retval PCLK2 frequency\r
- */\r
-uint32_t HAL_RCC_GetPCLK2Freq(void)\r
-{\r
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);\r
-} \r
-\r
-/**\r
- * @brief Configures the RCC_OscInitStruct according to the internal \r
- * RCC configuration registers.\r
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that \r
- * will be configured.\r
- * @retval None\r
- */\r
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(RCC_OscInitStruct != NULL);\r
-\r
- /* Set all possible values for the Oscillator type parameter ---------------*/\r
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \\r
- | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\r
-\r
-#if defined(RCC_CFGR2_PREDIV1SRC)\r
- /* Get the Prediv1 source --------------------------------------------------*/\r
- RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);\r
-#endif /* RCC_CFGR2_PREDIV1SRC */\r
-\r
- /* Get the HSE configuration -----------------------------------------------*/\r
- if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r
- {\r
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r
- }\r
- else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\r
- {\r
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r
- }\r
- RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();\r
-\r
- /* Get the HSI configuration -----------------------------------------------*/\r
- if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\r
- {\r
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r
- }\r
-\r
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);\r
-\r
- /* Get the LSE configuration -----------------------------------------------*/\r
- if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r
- {\r
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r
- }\r
- else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r
- {\r
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r
- }\r
- \r
- /* Get the LSI configuration -----------------------------------------------*/\r
- if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\r
- {\r
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r
- }\r
- \r
-\r
- /* Get the PLL configuration -----------------------------------------------*/\r
- if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\r
- {\r
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r
- }\r
- RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);\r
- RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);\r
-#if defined(RCC_CR_PLL2ON)\r
- /* Get the PLL2 configuration -----------------------------------------------*/\r
- if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)\r
- {\r
- RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;\r
- }\r
- RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();\r
- RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);\r
-#endif /* RCC_CR_PLL2ON */\r
-}\r
-\r
-/**\r
- * @brief Get the RCC_ClkInitStruct according to the internal \r
- * RCC configuration registers.\r
- * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that \r
- * contains the current clock configuration.\r
- * @param pFLatency Pointer on the Flash Latency.\r
- * @retval None\r
- */\r
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)\r
-{\r
- /* Check the parameters */\r
- assert_param(RCC_ClkInitStruct != NULL);\r
- assert_param(pFLatency != NULL);\r
-\r
- /* Set all possible values for the Clock type parameter --------------------*/\r
- RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r
- \r
- /* Get the SYSCLK configuration --------------------------------------------*/ \r
- RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);\r
- \r
- /* Get the HCLK configuration ----------------------------------------------*/ \r
- RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); \r
- \r
- /* Get the APB1 configuration ----------------------------------------------*/ \r
- RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); \r
- \r
- /* Get the APB2 configuration ----------------------------------------------*/ \r
- RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);\r
- \r
-#if defined(FLASH_ACR_LATENCY)\r
- /* Get the Flash Wait State (Latency) configuration ------------------------*/ \r
- *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); \r
-#else\r
- /* For VALUE lines devices, only LATENCY_0 can be set*/\r
- *pFLatency = (uint32_t)FLASH_LATENCY_0; \r
-#endif\r
-}\r
-\r
-/**\r
- * @brief This function handles the RCC CSS interrupt request.\r
- * @note This API should be called under the NMI_Handler().\r
- * @retval None\r
- */\r
-void HAL_RCC_NMI_IRQHandler(void)\r
-{\r
- /* Check RCC CSSF flag */\r
- if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r
- {\r
- /* RCC Clock Security System interrupt user callback */\r
- HAL_RCC_CSSCallback();\r
- \r
- /* Clear RCC CSS pending bit */\r
- __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function provides delay (in milliseconds) based on CPU cycles method.\r
- * @param mdelay: specifies the delay time length, in milliseconds.\r
- * @retval None\r
- */\r
-static void RCC_Delay(uint32_t mdelay)\r
-{\r
- __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);\r
- do \r
- {\r
- __NOP();\r
- } \r
- while (Delay --);\r
-}\r
-\r
-/**\r
- * @brief RCC Clock Security System interrupt callback\r
- * @retval none\r
- */\r
-__weak void HAL_RCC_CSSCallback(void)\r
-{\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_RCC_CSSCallback could be implemented in the user file\r
- */ \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_RCC_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_rcc_ex.c\r
- * @author MCD Application Team\r
- * @brief Extended RCC HAL module driver.\r
- * This file provides firmware functions to manage the following \r
- * functionalities RCC extension peripheral:\r
- * + Extended Peripheral Control functions\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_RCC_MODULE_ENABLED\r
-\r
-/** @defgroup RCCEx RCCEx\r
- * @brief RCC Extension HAL module driver.\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants\r
- * @{\r
- */\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r
- * @{\r
- */\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions \r
- * @brief Extended Peripheral Control functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Extended Peripheral Control functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection provides a set of functions allowing to control the RCC Clocks \r
- frequencies.\r
- [..] \r
- (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r
- select the RTC clock source; in this case the Backup domain will be reset in \r
- order to modify the RTC Clock source, as consequence RTC registers (including \r
- the backup registers) are set to their reset values.\r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the\r
- * RCC_PeriphCLKInitTypeDef.\r
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\r
- * contains the configuration information for the Extended Peripherals clocks(RTC clock).\r
- *\r
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select \r
- * the RTC clock source; in this case the Backup domain will be reset in \r
- * order to modify the RTC Clock source, as consequence RTC registers (including \r
- * the backup registers) are set to their reset values.\r
- *\r
- * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on \r
- * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to\r
- * manually disable it.\r
- *\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
-{\r
- uint32_t tickstart = 0U, temp_reg = 0U;\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- uint32_t pllactive = 0U;\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r
- \r
- /*------------------------------- RTC/LCD Configuration ------------------------*/ \r
- if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
- {\r
- /* check for RTC Parameters used to output RTCCLK */\r
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r
-\r
- FlagStatus pwrclkchanged = RESET;\r
-\r
- /* As soon as function is called to change RTC clock source, activation of the \r
- power domain is done. */\r
- /* Requires to enable write access to Backup Domain of necessary */\r
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
- {\r
- __HAL_RCC_PWR_CLK_ENABLE();\r
- pwrclkchanged = SET;\r
- }\r
- \r
- if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\r
- {\r
- /* Enable write access to Backup domain */\r
- SET_BIT(PWR->CR, PWR_CR_DBP);\r
- \r
- /* Wait for Backup domain Write protection disable */\r
- tickstart = HAL_GetTick();\r
- \r
- while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\r
- {\r
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- \r
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ \r
- temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);\r
- if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\r
- {\r
- /* Store the content of BDCR register before the reset of Backup Domain */\r
- temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\r
- /* RTC Clock selection can be changed only if the Backup Domain is reset */\r
- __HAL_RCC_BACKUPRESET_FORCE();\r
- __HAL_RCC_BACKUPRESET_RELEASE();\r
- /* Restore the Content of BDCR register */\r
- RCC->BDCR = temp_reg;\r
-\r
- /* Wait for LSERDY if LSE was enabled */\r
- if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))\r
- {\r
- /* Get Start Tick */\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till LSE is ready */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- } \r
- } \r
- }\r
- }\r
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); \r
-\r
- /* Require to disable power clock if necessary */\r
- if(pwrclkchanged == SET)\r
- {\r
- __HAL_RCC_PWR_CLK_DISABLE();\r
- }\r
- }\r
-\r
- /*------------------------------ ADC clock Configuration ------------------*/ \r
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));\r
- \r
- /* Configure the ADC clock source */\r
- __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);\r
- }\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- /*------------------------------ I2S2 Configuration ------------------------*/ \r
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));\r
-\r
- /* Configure the I2S2 clock source */\r
- __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);\r
- }\r
-\r
- /*------------------------------ I2S3 Configuration ------------------------*/ \r
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));\r
- \r
- /* Configure the I2S3 clock source */\r
- __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);\r
- }\r
-\r
- /*------------------------------ PLL I2S Configuration ----------------------*/ \r
- /* Check that PLLI2S need to be enabled */\r
- if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))\r
- {\r
- /* Update flag to indicate that PLL I2S should be active */\r
- pllactive = 1;\r
- }\r
-\r
- /* Check if PLL I2S need to be enabled */\r
- if (pllactive == 1)\r
- {\r
- /* Enable PLL I2S only if not active */\r
- if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));\r
- assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));\r
-\r
- /* Prediv2 can be written only when the PLL2 is disabled. */\r
- /* Return an error only if new value is different from the programmed value */\r
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \\r
- (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Configure the HSE prediv2 factor --------------------------------*/\r
- __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);\r
-\r
- /* Configure the main PLLI2S multiplication factors. */\r
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);\r
- \r
- /* Enable the main PLLI2S. */\r
- __HAL_RCC_PLLI2S_ENABLE();\r
- \r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till PLLI2S is ready */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */\r
- if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- }\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\\r
- || defined(STM32F105xC) || defined(STM32F107xC)\r
- /*------------------------------ USB clock Configuration ------------------*/ \r
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));\r
- \r
- /* Configure the USB clock source */\r
- __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);\r
- }\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Get the PeriphClkInit according to the internal\r
- * RCC configuration registers.\r
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that \r
- * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).\r
- * @retval None\r
- */\r
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
-{\r
- uint32_t srcclk = 0U;\r
- \r
- /* Set all possible values for the extended clock type parameter------------*/\r
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;\r
-\r
- /* Get the RTC configuration -----------------------------------------------*/\r
- srcclk = __HAL_RCC_GET_RTC_SOURCE();\r
- /* Source clock is LSE or LSI*/\r
- PeriphClkInit->RTCClockSelection = srcclk;\r
-\r
- /* Get the ADC clock configuration -----------------------------------------*/\r
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;\r
- PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- /* Get the I2S2 clock configuration -----------------------------------------*/\r
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;\r
- PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();\r
-\r
- /* Get the I2S3 clock configuration -----------------------------------------*/\r
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;\r
- PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();\r
-\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-#if defined(STM32F103xE) || defined(STM32F103xG)\r
- /* Get the I2S2 clock configuration -----------------------------------------*/\r
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;\r
- PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;\r
-\r
- /* Get the I2S3 clock configuration -----------------------------------------*/\r
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;\r
- PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;\r
-\r
-#endif /* STM32F103xE || STM32F103xG */\r
-\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\\r
- || defined(STM32F105xC) || defined(STM32F107xC)\r
- /* Get the USB clock configuration -----------------------------------------*/\r
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;\r
- PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-}\r
-\r
-/**\r
- * @brief Returns the peripheral clock frequency\r
- * @note Returns 0 if peripheral clock is unknown\r
- * @param PeriphClk Peripheral clock identifier\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock\r
- @if STM32F103xE\r
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- @endif\r
- @if STM32F103xG\r
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock\r
- @endif\r
- @if STM32F105xC\r
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock\r
- @endif\r
- @if STM32F107xC\r
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock\r
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock\r
- @endif\r
- @if STM32F102xx\r
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock\r
- @endif\r
- @if STM32F103xx\r
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock\r
- @endif\r
- * @retval Frequency in Hz (0: means that no available frequency for the peripheral)\r
- */\r
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r
-{\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};\r
- const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};\r
-\r
- uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;\r
- uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;\r
-#endif /* STM32F105xC || STM32F107xC */\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \\r
- defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\r
- const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};\r
- const uint8_t aPredivFactorTable[2] = {1, 2};\r
-\r
- uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */\r
- uint32_t temp_reg = 0U, frequency = 0U;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));\r
- \r
- switch (PeriphClk)\r
- {\r
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\\r
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\\r
- || defined(STM32F105xC) || defined(STM32F107xC)\r
- case RCC_PERIPHCLK_USB: \r
- {\r
- /* Get RCC configuration ------------------------------------------------------*/\r
- temp_reg = RCC->CFGR;\r
- \r
- /* Check if PLL is enabled */\r
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))\r
- {\r
- pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];\r
- if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)\r
- {\r
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\\r
- || defined(STM32F100xE)\r
- prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];\r
-#else\r
- prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];\r
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))\r
- {\r
- /* PLL2 selected as Prediv1 source */\r
- /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */\r
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;\r
- pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;\r
- pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);\r
- }\r
- else\r
- {\r
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */\r
- pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);\r
- }\r
- \r
- /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */\r
- /* In this case need to divide pllclk by 2 */\r
- if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])\r
- {\r
- pllclk = pllclk / 2;\r
- }\r
-#else\r
- if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)\r
- {\r
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */\r
- pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);\r
- }\r
-#endif /* STM32F105xC || STM32F107xC */\r
- }\r
- else\r
- {\r
- /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */\r
- pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);\r
- }\r
-\r
- /* Calcul of the USB frequency*/\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */\r
- if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)\r
- {\r
- /* Prescaler of 2 selected for USB */ \r
- frequency = pllclk;\r
- }\r
- else\r
- {\r
- /* Prescaler of 3 selected for USB */ \r
- frequency = (2 * pllclk) / 3;\r
- }\r
-#else\r
- /* USBCLK = PLLCLK / USB prescaler */\r
- if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)\r
- {\r
- /* No prescaler selected for USB */\r
- frequency = pllclk;\r
- }\r
- else\r
- {\r
- /* Prescaler of 1.5 selected for USB */ \r
- frequency = (pllclk * 2) / 3;\r
- }\r
-#endif\r
- }\r
- break;\r
- }\r
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)\r
- case RCC_PERIPHCLK_I2S2: \r
- {\r
-#if defined(STM32F103xE) || defined(STM32F103xG)\r
- /* SYSCLK used as source clock for I2S2 */\r
- frequency = HAL_RCC_GetSysClockFreq();\r
-#else\r
- if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)\r
- {\r
- /* SYSCLK used as source clock for I2S2 */\r
- frequency = HAL_RCC_GetSysClockFreq();\r
- }\r
- else\r
- {\r
- /* Check if PLLI2S is enabled */\r
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))\r
- {\r
- /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */\r
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;\r
- pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;\r
- frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));\r
- }\r
- }\r
-#endif /* STM32F103xE || STM32F103xG */\r
- break;\r
- }\r
- case RCC_PERIPHCLK_I2S3:\r
- {\r
-#if defined(STM32F103xE) || defined(STM32F103xG)\r
- /* SYSCLK used as source clock for I2S3 */\r
- frequency = HAL_RCC_GetSysClockFreq();\r
-#else\r
- if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)\r
- {\r
- /* SYSCLK used as source clock for I2S3 */\r
- frequency = HAL_RCC_GetSysClockFreq();\r
- }\r
- else\r
- {\r
- /* Check if PLLI2S is enabled */\r
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))\r
- {\r
- /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */\r
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;\r
- pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;\r
- frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));\r
- }\r
- }\r
-#endif /* STM32F103xE || STM32F103xG */\r
- break;\r
- }\r
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */\r
- case RCC_PERIPHCLK_RTC: \r
- {\r
- /* Get RCC BDCR configuration ------------------------------------------------------*/\r
- temp_reg = RCC->BDCR;\r
-\r
- /* Check if LSE is ready if RTC clock selection is LSE */\r
- if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))\r
- {\r
- frequency = LSE_VALUE;\r
- }\r
- /* Check if LSI is ready if RTC clock selection is LSI */\r
- else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))\r
- {\r
- frequency = LSI_VALUE;\r
- }\r
- else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))\r
- {\r
- frequency = HSE_VALUE / 128U;\r
- }\r
- /* Clock not enabled for RTC*/\r
- else\r
- {\r
- frequency = 0U;\r
- }\r
- break;\r
- }\r
- case RCC_PERIPHCLK_ADC: \r
- {\r
- frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);\r
- break;\r
- }\r
- default: \r
- {\r
- break;\r
- }\r
- }\r
- return(frequency);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
-/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function\r
- * @brief PLLI2S Management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Extended PLLI2S Management functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection provides a set of functions allowing to control the PLLI2S\r
- activation or deactivation\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enable PLLI2S\r
- * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that\r
- * contains the configuration information for the PLLI2S\r
- * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)\r
-{\r
- uint32_t tickstart = 0U;\r
-\r
- /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/\r
- if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));\r
- assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));\r
-\r
- /* Prediv2 can be written only when the PLL2 is disabled. */\r
- /* Return an error only if new value is different from the programmed value */\r
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \\r
- (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Disable the main PLLI2S. */\r
- __HAL_RCC_PLLI2S_DISABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till PLLI2S is ready */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Configure the HSE prediv2 factor --------------------------------*/\r
- __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);\r
- \r
-\r
- /* Configure the main PLLI2S multiplication factors. */\r
- __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);\r
- \r
- /* Enable the main PLLI2S. */\r
- __HAL_RCC_PLLI2S_ENABLE();\r
- \r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till PLLI2S is ready */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */\r
- return HAL_ERROR;\r
- }\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Disable PLLI2S\r
- * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)\r
-{\r
- uint32_t tickstart = 0U;\r
-\r
- /* Disable PLL I2S as not requested by I2S2 or I2S3*/\r
- if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))\r
- {\r
- /* Disable the main PLLI2S. */\r
- __HAL_RCC_PLLI2S_DISABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till PLLI2S is ready */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/\r
- return HAL_ERROR;\r
- }\r
- \r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function\r
- * @brief PLL2 Management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Extended PLL2 Management functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection provides a set of functions allowing to control the PLL2\r
- activation or deactivation\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enable PLL2\r
- * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that\r
- * contains the configuration information for the PLL2\r
- * @note The PLL2 configuration not modified if used indirectly as system clock.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)\r
-{\r
- uint32_t tickstart = 0U;\r
-\r
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system \r
- clock (i.e. it is used as PLL clock entry that is used as system clock). */\r
- if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \\r
- (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \\r
- ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));\r
- assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));\r
-\r
- /* Prediv2 can be written only when the PLLI2S is disabled. */\r
- /* Return an error only if new value is different from the programmed value */\r
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \\r
- (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Disable the main PLL2. */\r
- __HAL_RCC_PLL2_DISABLE();\r
- \r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till PLL2 is disabled */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- \r
- /* Configure the HSE prediv2 factor --------------------------------*/\r
- __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);\r
-\r
- /* Configure the main PLL2 multiplication factors. */\r
- __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);\r
- \r
- /* Enable the main PLL2. */\r
- __HAL_RCC_PLL2_ENABLE();\r
- \r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till PLL2 is ready */\r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Disable PLL2\r
- * @note PLL2 is not disabled if used indirectly as system clock.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)\r
-{\r
- uint32_t tickstart = 0U;\r
-\r
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system \r
- clock (i.e. it is used as PLL clock entry that is used as system clock). */\r
- if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \\r
- (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \\r
- ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- /* Disable the main PLL2. */\r
- __HAL_RCC_PLL2_DISABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
- \r
- /* Wait till PLL2 is disabled */ \r
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)\r
- {\r
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-#endif /* STM32F105xC || STM32F107xC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_RCC_MODULE_ENABLED */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_tim.c\r
- * @author MCD Application Team\r
- * @brief TIM HAL module driver\r
- * This file provides firmware functions to manage the following \r
- * functionalities of the Timer (TIM) peripheral:\r
- * + Time Base Initialization\r
- * + Time Base Start\r
- * + Time Base Start Interruption\r
- * + Time Base Start DMA\r
- * + Time Output Compare/PWM Initialization\r
- * + Time Output Compare/PWM Channel Configuration\r
- * + Time Output Compare/PWM Start\r
- * + Time Output Compare/PWM Start Interruption\r
- * + Time Output Compare/PWM Start DMA\r
- * + Time Input Capture Initialization\r
- * + Time Input Capture Channel Configuration\r
- * + Time Input Capture Start\r
- * + Time Input Capture Start Interruption \r
- * + Time Input Capture Start DMA\r
- * + Time One Pulse Initialization\r
- * + Time One Pulse Channel Configuration\r
- * + Time One Pulse Start \r
- * + Time Encoder Interface Initialization\r
- * + Time Encoder Interface Start\r
- * + Time Encoder Interface Start Interruption\r
- * + Time Encoder Interface Start DMA\r
- * + Commutation Event configuration with Interruption and DMA\r
- * + Time OCRef clear configuration\r
- * + Time External Clock configuration\r
- @verbatim\r
- ==============================================================================\r
- ##### TIMER Generic features #####\r
- ==============================================================================\r
- [..] The Timer features include:\r
- (#) 16-bit up, down, up/down auto-reload counter.\r
- (#) 16-bit programmable prescaler allowing dividing (also on the fly) the \r
- counter clock frequency either by any factor between 1 and 65536.\r
- (#) Up to 4 independent channels for:\r
- (++) Input Capture\r
- (++) Output Compare\r
- (++) PWM generation (Edge and Center-aligned Mode)\r
- (++) One-pulse mode output \r
-\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..]\r
- (#) Initialize the TIM low level resources by implementing the following functions \r
- depending from feature used :\r
- (++) Time Base : HAL_TIM_Base_MspInit()\r
- (++) Input Capture : HAL_TIM_IC_MspInit()\r
- (++) Output Compare : HAL_TIM_OC_MspInit()\r
- (++) PWM generation : HAL_TIM_PWM_MspInit()\r
- (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
- (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r
-\r
- (#) Initialize the TIM low level resources :\r
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
- (##) TIM pins configuration\r
- (+++) Enable the clock for the TIM GPIOs using the following function:\r
- __HAL_RCC_GPIOx_CLK_ENABLE();\r
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
-\r
- (#) The external Clock can be configured, if needed (the default clock is the \r
- internal clock from the APBx), using the following function:\r
- HAL_TIM_ConfigClockSource, the clock configuration should be done before \r
- any start function.\r
-\r
- (#) Configure the TIM in the desired functioning mode using one of the \r
- Initialization function of this driver:\r
- (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r
- (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an \r
- Output Compare signal.\r
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a \r
- PWM signal.\r
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an \r
- external signal.\r
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer \r
- in One Pulse Mode.\r
- (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r
-\r
- (#) Activate the TIM peripheral using one of the start functions depending from the feature used:\r
- (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r
- (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r
- (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r
- (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r
- (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r
- (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r
-\r
- (#) The DMA Burst is managed with the two following functions:\r
- HAL_TIM_DMABurst_WriteStart()\r
- HAL_TIM_DMABurst_ReadStart()\r
-\r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM TIM\r
- * @brief TIM HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_TIM_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup TIM_Private_Functions TIM Private Functions\r
- * @{\r
- */\r
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
- uint32_t TIM_ICFilter);\r
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
- uint32_t TIM_ICFilter);\r
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
- uint32_t TIM_ICFilter);\r
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,\r
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\r
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);\r
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
- TIM_SlaveConfigTypeDef * sSlaveConfig);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup TIM_Exported_Functions TIM Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions \r
- * @brief Time Base functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Time Base functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Initialize and configure the TIM base.\r
- (+) De-initialize the TIM base.\r
- (+) Start the Time Base.\r
- (+) Stop the Time Base.\r
- (+) Start the Time Base and enable interrupt.\r
- (+) Stop the Time Base and disable interrupt.\r
- (+) Start the Time Base and enable DMA transfer.\r
- (+) Stop the Time Base and disable DMA transfer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-/**\r
- * @brief Initializes the TIM Time base Unit according to the specified\r
- * parameters in the TIM_HandleTypeDef and create the associated handle.\r
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
- * requires a timer reset to avoid unexpected direction\r
- * due to DIR bit readonly in center aligned mode.\r
- * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()\r
- * @param htim : TIM Base handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the TIM handle allocation */\r
- if(htim == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-\r
- if(htim->State == HAL_TIM_STATE_RESET)\r
- {\r
- /* Allocate lock resource and initialize it */\r
- htim->Lock = HAL_UNLOCKED;\r
- \r
- /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
- HAL_TIM_Base_MspInit(htim);\r
- }\r
-\r
- /* Set the TIM state */\r
- htim->State= HAL_TIM_STATE_BUSY;\r
-\r
- /* Set the Time Base configuration */\r
- TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
- /* Initialize the TIM state*/\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief DeInitializes the TIM Base peripheral \r
- * @param htim : TIM Base handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Disable the TIM Peripheral Clock */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
- HAL_TIM_Base_MspDeInit(htim);\r
-\r
- /* Change TIM state */\r
- htim->State = HAL_TIM_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM Base MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_Base_MspInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief DeInitializes TIM Base MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_Base_MspDeInit could be implemented in the user file\r
- */\r
-}\r
-\r
-\r
-/**\r
- * @brief Starts the TIM Base generation.\r
- * @param htim : TIM handle\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- /* Set the TIM state */\r
- htim->State= HAL_TIM_STATE_BUSY;\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Change the TIM state*/\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Base generation.\r
- * @param htim : TIM handle\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- /* Set the TIM state */\r
- htim->State= HAL_TIM_STATE_BUSY;\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the TIM state*/\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Base generation in interrupt mode.\r
- * @param htim : TIM handle\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- /* Enable the TIM Update interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Base generation in interrupt mode.\r
- * @param htim : TIM handle\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
- /* Disable the TIM Update interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Base generation in DMA mode.\r
- * @param htim : TIM handle\r
- * @param pData : The source Buffer address.\r
- * @param Length : The length of data to be transferred from memory to peripheral.\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if((pData == 0U) && (Length > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);\r
-\r
- /* Enable the TIM Update DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Base generation in DMA mode.\r
- * @param htim : TIM handle\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
-\r
- /* Disable the TIM Update DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the htim state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions \r
- * @brief Time Output Compare functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Time Output Compare functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Initialize and configure the TIM Output Compare.\r
- (+) De-initialize the TIM Output Compare.\r
- (+) Start the Time Output Compare.\r
- (+) Stop the Time Output Compare.\r
- (+) Start the Time Output Compare and enable interrupt.\r
- (+) Stop the Time Output Compare and disable interrupt.\r
- (+) Start the Time Output Compare and enable DMA transfer.\r
- (+) Stop the Time Output Compare and disable DMA transfer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-/**\r
- * @brief Initializes the TIM Output Compare according to the specified\r
- * parameters in the TIM_HandleTypeDef and create the associated handle.\r
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
- * requires a timer reset to avoid unexpected direction\r
- * due to DIR bit readonly in center aligned mode.\r
- * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()\r
- * @param htim : TIM Output Compare handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)\r
-{\r
- /* Check the TIM handle allocation */\r
- if(htim == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-\r
- if(htim->State == HAL_TIM_STATE_RESET)\r
- {\r
- /* Allocate lock resource and initialize it */\r
- htim->Lock = HAL_UNLOCKED;\r
- \r
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
- HAL_TIM_OC_MspInit(htim);\r
- }\r
-\r
- /* Set the TIM state */\r
- htim->State= HAL_TIM_STATE_BUSY;\r
-\r
- /* Init the base time for the Output Compare */\r
- TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
- /* Initialize the TIM state*/\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief DeInitializes the TIM peripheral \r
- * @param htim : TIM Output Compare handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Disable the TIM Peripheral Clock */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
- HAL_TIM_OC_MspDeInit(htim);\r
-\r
- /* Change TIM state */\r
- htim->State = HAL_TIM_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM Output Compare MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_OC_MspInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief DeInitializes TIM Output Compare MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_OC_MspDeInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Output Compare signal generation.\r
- * @param htim : TIM Output Compare handle \r
- * @param Channel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Enable the Output compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Enable the main output */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
- }\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Output Compare signal generation.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Disable the Output compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Output Compare signal generation in interrupt mode.\r
- * @param htim : TIM OC handle\r
- * @param Channel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Enable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Enable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Enable the TIM Capture/Compare 3 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Enable the TIM Capture/Compare 4 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Enable the Output compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Enable the main output */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
- }\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Output Compare signal generation in interrupt mode.\r
- * @param htim : TIM Output Compare handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Capture/Compare 3 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Disable the TIM Capture/Compare 4 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the Output compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Output Compare signal generation in DMA mode.\r
- * @param htim : TIM Output Compare handle\r
- * @param Channel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @param pData : The source Buffer address.\r
- * @param Length : The length of data to be transferred from memory to TIM peripheral\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if(((uint32_t)pData == 0U) && (Length > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
-\r
- /* Enable the TIM Capture/Compare 1 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
-\r
- /* Enable the TIM Capture/Compare 2 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
-\r
- /* Enable the TIM Capture/Compare 3 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
-\r
- /* Enable the TIM Capture/Compare 4 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Enable the Output compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Enable the main output */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
- }\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Output Compare signal generation in DMA mode.\r
- * @param htim : TIM Output Compare handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Capture/Compare 1 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Capture/Compare 2 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Capture/Compare 3 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Disable the TIM Capture/Compare 4 interrupt */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the Output compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the htim state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions \r
- * @brief Time PWM functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Time PWM functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Initialize and configure the TIM PWM.\r
- (+) De-initialize the TIM PWM.\r
- (+) Start the Time PWM.\r
- (+) Stop the Time PWM.\r
- (+) Start the Time PWM and enable interrupt.\r
- (+) Stop the Time PWM and disable interrupt.\r
- (+) Start the Time PWM and enable DMA transfer.\r
- (+) Stop the Time PWM and disable DMA transfer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-/**\r
- * @brief Initializes the TIM PWM Time Base according to the specified\r
- * parameters in the TIM_HandleTypeDef and create the associated handle.\r
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
- * requires a timer reset to avoid unexpected direction\r
- * due to DIR bit readonly in center aligned mode.\r
- * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()\r
- * @param htim : TIM handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the TIM handle allocation */\r
- if(htim == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-\r
- if(htim->State == HAL_TIM_STATE_RESET)\r
- {\r
- /* Allocate lock resource and initialize it */\r
- htim->Lock = HAL_UNLOCKED;\r
- \r
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
- HAL_TIM_PWM_MspInit(htim);\r
- }\r
-\r
- /* Set the TIM state */\r
- htim->State= HAL_TIM_STATE_BUSY;\r
-\r
- /* Init the base time for the PWM */\r
- TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
- /* Initialize the TIM state*/\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief DeInitializes the TIM peripheral \r
- * @param htim : TIM handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Disable the TIM Peripheral Clock */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
- HAL_TIM_PWM_MspDeInit(htim);\r
-\r
- /* Change TIM state */\r
- htim->State = HAL_TIM_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM PWM MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_PWM_MspInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief DeInitializes TIM PWM MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Starts the PWM signal generation.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Enable the Capture compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Enable the main output */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
- }\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the PWM signal generation.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channels to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Disable the Capture compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the htim state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the PWM signal generation in interrupt mode.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Enable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Enable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Enable the TIM Capture/Compare 3 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Enable the TIM Capture/Compare 4 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Enable the Capture compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Enable the main output */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
- }\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the PWM signal generation in interrupt mode.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channels to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Capture/Compare 3 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Disable the TIM Capture/Compare 4 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the Capture compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM PWM signal generation in DMA mode.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @param pData : The source Buffer address.\r
- * @param Length : The length of data to be transferred from memory to TIM peripheral\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if(((uint32_t)pData == 0U) && (Length > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
-\r
- /* Enable the TIM Capture/Compare 1 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
-\r
- /* Enable the TIM Capture/Compare 2 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
-\r
- /* Enable the TIM Output Capture/Compare 3 request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
-\r
- /* Enable the TIM Capture/Compare 4 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Enable the Capture compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Enable the main output */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
- }\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM PWM signal generation in DMA mode.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channels to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Capture/Compare 1 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Capture/Compare 2 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Capture/Compare 3 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Disable the TIM Capture/Compare 4 interrupt */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the Capture compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the htim state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions \r
- * @brief Time Input Capture functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Time Input Capture functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Initialize and configure the TIM Input Capture.\r
- (+) De-initialize the TIM Input Capture.\r
- (+) Start the Time Input Capture.\r
- (+) Stop the Time Input Capture.\r
- (+) Start the Time Input Capture and enable interrupt.\r
- (+) Stop the Time Input Capture and disable interrupt.\r
- (+) Start the Time Input Capture and enable DMA transfer.\r
- (+) Stop the Time Input Capture and disable DMA transfer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-/**\r
- * @brief Initializes the TIM Input Capture Time base according to the specified\r
- * parameters in the TIM_HandleTypeDef and create the associated handle.\r
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
- * requires a timer reset to avoid unexpected direction\r
- * due to DIR bit readonly in center aligned mode.\r
- * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()\r
- * @param htim : TIM Input Capture handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the TIM handle allocation */\r
- if(htim == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
-\r
- if(htim->State == HAL_TIM_STATE_RESET)\r
- {\r
- /* Allocate lock resource and initialize it */\r
- htim->Lock = HAL_UNLOCKED;\r
- \r
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
- HAL_TIM_IC_MspInit(htim);\r
- }\r
-\r
- /* Set the TIM state */\r
- htim->State= HAL_TIM_STATE_BUSY;\r
-\r
- /* Init the base time for the input capture */\r
- TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
- /* Initialize the TIM state*/\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief DeInitializes the TIM peripheral \r
- * @param htim : TIM Input Capture handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Disable the TIM Peripheral Clock */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
- HAL_TIM_IC_MspDeInit(htim);\r
-\r
- /* Change TIM state */\r
- htim->State = HAL_TIM_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM Input Capture MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_IC_MspInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief DeInitializes TIM Input Capture MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_IC_MspDeInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Input Capture measurement.\r
- * @param htim : TIM Input Capture handle\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Enable the Input Capture channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Input Capture measurement.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channels to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Disable the Input Capture channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Input Capture measurement in interrupt mode.\r
- * @param htim : TIM Input Capture handle\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Enable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Enable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Enable the TIM Capture/Compare 3 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Enable the TIM Capture/Compare 4 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- /* Enable the Input Capture channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Input Capture measurement in interrupt mode.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channels to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Capture/Compare 3 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Disable the TIM Capture/Compare 4 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the Input Capture channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Input Capture measurement in DMA mode.\r
- * @param htim : TIM Input Capture handle\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @param pData : The destination Buffer address.\r
- * @param Length : The length of data to be transferred from TIM peripheral to memory.\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if((pData == 0U) && (Length > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);\r
-\r
- /* Enable the TIM Capture/Compare 1 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);\r
-\r
- /* Enable the TIM Capture/Compare 2 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);\r
-\r
- /* Enable the TIM Capture/Compare 3 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);\r
-\r
- /* Enable the TIM Capture/Compare 4 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Enable the Input Capture channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Input Capture measurement in DMA mode.\r
- * @param htim : TIM Input Capture handle\r
- * @param Channel : TIM Channels to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Capture/Compare 1 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Capture/Compare 2 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Capture/Compare 3 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Disable the TIM Capture/Compare 4 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the Input Capture channel */\r
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the htim state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions \r
- * @brief Time One Pulse functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Time One Pulse functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Initialize and configure the TIM One Pulse.\r
- (+) De-initialize the TIM One Pulse.\r
- (+) Start the Time One Pulse.\r
- (+) Stop the Time One Pulse.\r
- (+) Start the Time One Pulse and enable interrupt.\r
- (+) Stop the Time One Pulse and disable interrupt.\r
- (+) Start the Time One Pulse and enable DMA transfer.\r
- (+) Stop the Time One Pulse and disable DMA transfer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-/**\r
- * @brief Initializes the TIM One Pulse Time Base according to the specified\r
- * parameters in the TIM_HandleTypeDef and create the associated handle.\r
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
- * requires a timer reset to avoid unexpected direction\r
- * due to DIR bit readonly in center aligned mode.\r
- * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()\r
- * @param htim : TIM OnePulse handle\r
- * @param OnePulseMode : Select the One pulse mode.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r
-{\r
- /* Check the TIM handle allocation */\r
- if(htim == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
- assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r
-\r
- if(htim->State == HAL_TIM_STATE_RESET)\r
- {\r
- /* Allocate lock resource and initialize it */\r
- htim->Lock = HAL_UNLOCKED;\r
- \r
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
- HAL_TIM_OnePulse_MspInit(htim);\r
- }\r
-\r
- /* Set the TIM state */\r
- htim->State= HAL_TIM_STATE_BUSY;\r
-\r
- /* Configure the Time base in the One Pulse Mode */\r
- TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
- /* Reset the OPM Bit */\r
- htim->Instance->CR1 &= ~TIM_CR1_OPM;\r
-\r
- /* Configure the OPM Mode */\r
- htim->Instance->CR1 |= OnePulseMode;\r
-\r
- /* Initialize the TIM state*/\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief DeInitializes the TIM One Pulse \r
- * @param htim : TIM One Pulse handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Disable the TIM Peripheral Clock */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
- HAL_TIM_OnePulse_MspDeInit(htim);\r
-\r
- /* Change TIM state */\r
- htim->State = HAL_TIM_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM One Pulse MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief DeInitializes TIM One Pulse MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM One Pulse signal generation.\r
- * @param htim : TIM One Pulse handle\r
- * @param OutputChannel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(OutputChannel);\r
-\r
- /* Enable the Capture compare and the Input Capture channels \r
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r
-\r
- No need to enable the counter, it's enabled automatically by hardware \r
- (the counter starts in response to a stimulus and generate a pulse */\r
-\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Enable the main output */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
- }\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM One Pulse signal generation.\r
- * @param htim : TIM One Pulse handle\r
- * @param OutputChannel : TIM Channels to be disable\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(OutputChannel);\r
-\r
- /* Disable the Capture compare and the Input Capture channels\r
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
-\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM One Pulse signal generation in interrupt mode.\r
- * @param htim : TIM One Pulse handle\r
- * @param OutputChannel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(OutputChannel);\r
-\r
- /* Enable the Capture compare and the Input Capture channels \r
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r
-\r
- No need to enable the counter, it's enabled automatically by hardware \r
- (the counter starts in response to a stimulus and generate a pulse */\r
-\r
- /* Enable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-\r
- /* Enable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Enable the main output */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
- }\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM One Pulse signal generation in interrupt mode.\r
- * @param htim : TIM One Pulse handle\r
- * @param OutputChannel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(OutputChannel);\r
-\r
- /* Disable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-\r
- /* Disable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-\r
- /* Disable the Capture compare and the Input Capture channels \r
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
- {\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions \r
- * @brief Time Encoder functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Time Encoder functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Initialize and configure the TIM Encoder.\r
- (+) De-initialize the TIM Encoder.\r
- (+) Start the Time Encoder.\r
- (+) Stop the Time Encoder.\r
- (+) Start the Time Encoder and enable interrupt.\r
- (+) Stop the Time Encoder and disable interrupt.\r
- (+) Start the Time Encoder and enable DMA transfer.\r
- (+) Stop the Time Encoder and disable DMA transfer.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-/**\r
- * @brief Initializes the TIM Encoder Interface and create the associated handle.\r
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
- * requires a timer reset to avoid unexpected direction\r
- * due to DIR bit readonly in center aligned mode.\r
- * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()\r
- * @param htim : TIM Encoder Interface handle\r
- * @param sConfig : TIM Encoder Interface configuration structure\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)\r
-{\r
- uint32_t tmpsmcr = 0U;\r
- uint32_t tmpccmr1 = 0U;\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Check the TIM handle allocation */\r
- if(htim == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
- assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r
-\r
- if(htim->State == HAL_TIM_STATE_RESET)\r
- {\r
- /* Allocate lock resource and initialize it */\r
- htim->Lock = HAL_UNLOCKED;\r
- \r
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
- HAL_TIM_Encoder_MspInit(htim);\r
- }\r
-\r
- /* Set the TIM state */\r
- htim->State= HAL_TIM_STATE_BUSY;\r
-\r
- /* Reset the SMS bits */\r
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
-\r
- /* Configure the Time base in the Encoder Mode */\r
- TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = htim->Instance->SMCR;\r
-\r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = htim->Instance->CCMR1;\r
-\r
- /* Get the TIMx CCER register value */\r
- tmpccer = htim->Instance->CCER;\r
-\r
- /* Set the encoder Mode */\r
- tmpsmcr |= sConfig->EncoderMode;\r
-\r
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));\r
-\r
- /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);\r
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);\r
-\r
- /* Set the TI1 and the TI2 Polarities */\r
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);\r
-\r
- /* Write to TIMx SMCR */\r
- htim->Instance->SMCR = tmpsmcr;\r
-\r
- /* Write to TIMx CCMR1 */\r
- htim->Instance->CCMR1 = tmpccmr1;\r
-\r
- /* Write to TIMx CCER */\r
- htim->Instance->CCER = tmpccer;\r
-\r
- /* Initialize the TIM state*/\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-\r
-/**\r
- * @brief DeInitializes the TIM Encoder interface \r
- * @param htim : TIM Encoder handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Disable the TIM Peripheral Clock */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
- HAL_TIM_Encoder_MspDeInit(htim);\r
-\r
- /* Change TIM state */\r
- htim->State = HAL_TIM_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM Encoder Interface MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_Encoder_MspInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief DeInitializes TIM Encoder Interface MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Encoder Interface.\r
- * @param htim : TIM Encoder Interface handle\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
- /* Enable the encoder interface channels */\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
- break;\r
- }\r
- case TIM_CHANNEL_2:\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
- break;\r
- }\r
- default :\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
- break;\r
- }\r
- }\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Encoder Interface.\r
- * @param htim : TIM Encoder Interface handle\r
- * @param Channel : TIM Channels to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
- /* Disable the Input Capture channels 1 and 2\r
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
- break;\r
- }\r
- case TIM_CHANNEL_2:\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
- break;\r
- }\r
- default :\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
- break;\r
- }\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Encoder Interface in interrupt mode.\r
- * @param htim : TIM Encoder Interface handle\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
- /* Enable the encoder interface channels */\r
- /* Enable the capture compare Interrupts 1 and/or 2 */\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
- break;\r
- }\r
- case TIM_CHANNEL_2:\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
- break;\r
- }\r
- default :\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
- break;\r
- }\r
- }\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Encoder Interface in interrupt mode.\r
- * @param htim : TIM Encoder Interface handle\r
- * @param Channel : TIM Channels to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
- /* Disable the Input Capture channels 1 and 2\r
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
- if(Channel == TIM_CHANNEL_1)\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
- /* Disable the capture compare Interrupts 1 */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- else if(Channel == TIM_CHANNEL_2)\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
- /* Disable the capture compare Interrupts 2 */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- else\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
- /* Disable the capture compare Interrupts 1 and 2 */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the htim state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Encoder Interface in DMA mode.\r
- * @param htim : TIM Encoder Interface handle\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
- * @param pData1 : The destination Buffer address for IC1.\r
- * @param pData2 : The destination Buffer address for IC2.\r
- * @param Length : The length of data to be transferred from TIM peripheral to memory.\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);\r
-\r
- /* Enable the TIM Input Capture DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Enable the Capture compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r
-\r
- /* Enable the TIM Input Capture DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Enable the Capture compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_ALL:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);\r
-\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Enable the Capture compare channel */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
-\r
- /* Enable the TIM Input Capture DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
- /* Enable the TIM Input Capture DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Encoder Interface in DMA mode.\r
- * @param htim : TIM Encoder Interface handle\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
-\r
- /* Disable the Input Capture channels 1 and 2\r
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
- if(Channel == TIM_CHANNEL_1)\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
- /* Disable the capture compare DMA Request 1 */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- else if(Channel == TIM_CHANNEL_2)\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
- /* Disable the capture compare DMA Request 2 */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- else\r
- {\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
-\r
- /* Disable the capture compare DMA Request 1 and 2 */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the htim state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management \r
- * @brief IRQ handler management \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### IRQ handler management #####\r
- ==============================================================================\r
- [..]\r
- This section provides Timer IRQ handler function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-/**\r
- * @brief This function handles TIM interrupts requests.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r
-{\r
- /* Capture compare 1 event */\r
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r
- {\r
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)\r
- {\r
- {\r
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
-\r
- /* Input capture event */\r
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)\r
- {\r
- HAL_TIM_IC_CaptureCallback(htim);\r
- }\r
- /* Output compare event */\r
- else\r
- {\r
- HAL_TIM_OC_DelayElapsedCallback(htim);\r
- HAL_TIM_PWM_PulseFinishedCallback(htim);\r
- }\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
- }\r
- }\r
- }\r
- /* Capture compare 2 event */\r
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r
- {\r
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)\r
- {\r
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
- /* Input capture event */\r
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)\r
- {\r
- HAL_TIM_IC_CaptureCallback(htim);\r
- }\r
- /* Output compare event */\r
- else\r
- {\r
- HAL_TIM_OC_DelayElapsedCallback(htim);\r
- HAL_TIM_PWM_PulseFinishedCallback(htim);\r
- }\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
- }\r
- }\r
- /* Capture compare 3 event */\r
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r
- {\r
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)\r
- {\r
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
- /* Input capture event */\r
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)\r
- {\r
- HAL_TIM_IC_CaptureCallback(htim);\r
- }\r
- /* Output compare event */\r
- else\r
- {\r
- HAL_TIM_OC_DelayElapsedCallback(htim);\r
- HAL_TIM_PWM_PulseFinishedCallback(htim);\r
- }\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
- }\r
- }\r
- /* Capture compare 4 event */\r
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r
- {\r
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)\r
- {\r
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
- /* Input capture event */\r
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)\r
- {\r
- HAL_TIM_IC_CaptureCallback(htim);\r
- }\r
- /* Output compare event */\r
- else\r
- {\r
- HAL_TIM_OC_DelayElapsedCallback(htim);\r
- HAL_TIM_PWM_PulseFinishedCallback(htim);\r
- }\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
- }\r
- }\r
- /* TIM Update event */\r
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r
- {\r
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)\r
- {\r
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r
- HAL_TIM_PeriodElapsedCallback(htim);\r
- }\r
- }\r
- /* TIM Break input event */\r
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\r
- {\r
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)\r
- {\r
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r
- HAL_TIMEx_BreakCallback(htim);\r
- }\r
- }\r
- /* TIM Trigger detection event */\r
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r
- {\r
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)\r
- {\r
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r
- HAL_TIM_TriggerCallback(htim);\r
- }\r
- }\r
- /* TIM commutation event */\r
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\r
- {\r
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)\r
- {\r
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\r
- HAL_TIMEx_CommutationCallback(htim);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions\r
- * @brief Peripheral Control functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Peripheral Control functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.\r
- (+) Configure External Clock source.\r
- (+) Configure Complementary channels, break features and dead time.\r
- (+) Configure Master and the Slave synchronization.\r
- (+) Configure the DMA Burst Mode.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the TIM Output Compare Channels according to the specified\r
- * parameters in the TIM_OC_InitTypeDef.\r
- * @param htim : TIM Output Compare handle\r
- * @param sConfig : TIM Output Compare configuration structure\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CHANNELS(Channel));\r
- assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
-\r
- /* Check input state */\r
- __HAL_LOCK(htim);\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
- /* Configure the TIM Channel 1 in Output Compare */\r
- TIM_OC1_SetConfig(htim->Instance, sConfig);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
- /* Configure the TIM Channel 2 in Output Compare */\r
- TIM_OC2_SetConfig(htim->Instance, sConfig);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
- /* Configure the TIM Channel 3 in Output Compare */\r
- TIM_OC3_SetConfig(htim->Instance, sConfig);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
- /* Configure the TIM Channel 4 in Output Compare */\r
- TIM_OC4_SetConfig(htim->Instance, sConfig);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM Input Capture Channels according to the specified\r
- * parameters in the TIM_IC_InitTypeDef.\r
- * @param htim : TIM IC handle\r
- * @param sConfig : TIM Input Capture configuration structure\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r
- assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r
- assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r
- assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r
-\r
- __HAL_LOCK(htim);\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- if (Channel == TIM_CHANNEL_1)\r
- {\r
- /* TI1 Configuration */\r
- TIM_TI1_SetConfig(htim->Instance,\r
- sConfig->ICPolarity,\r
- sConfig->ICSelection,\r
- sConfig->ICFilter);\r
-\r
- /* Reset the IC1PSC Bits */\r
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
-\r
- /* Set the IC1PSC value */\r
- htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r
- }\r
- else if (Channel == TIM_CHANNEL_2)\r
- {\r
- /* TI2 Configuration */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
- TIM_TI2_SetConfig(htim->Instance,\r
- sConfig->ICPolarity,\r
- sConfig->ICSelection,\r
- sConfig->ICFilter);\r
-\r
- /* Reset the IC2PSC Bits */\r
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
-\r
- /* Set the IC2PSC value */\r
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);\r
- }\r
- else if (Channel == TIM_CHANNEL_3)\r
- {\r
- /* TI3 Configuration */\r
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
-\r
- TIM_TI3_SetConfig(htim->Instance,\r
- sConfig->ICPolarity,\r
- sConfig->ICSelection,\r
- sConfig->ICFilter);\r
-\r
- /* Reset the IC3PSC Bits */\r
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r
-\r
- /* Set the IC3PSC value */\r
- htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r
- }\r
- else\r
- {\r
- /* TI4 Configuration */\r
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
-\r
- TIM_TI4_SetConfig(htim->Instance,\r
- sConfig->ICPolarity,\r
- sConfig->ICSelection,\r
- sConfig->ICFilter);\r
-\r
- /* Reset the IC4PSC Bits */\r
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r
-\r
- /* Set the IC4PSC value */\r
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);\r
- }\r
-\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM PWM channels according to the specified\r
- * parameters in the TIM_OC_InitTypeDef.\r
- * @param htim : TIM handle\r
- * @param sConfig : TIM PWM configuration structure\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r
-{\r
- __HAL_LOCK(htim);\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CHANNELS(Channel));\r
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
- /* Configure the Channel 1 in PWM mode */\r
- TIM_OC1_SetConfig(htim->Instance, sConfig);\r
-\r
- /* Set the Preload enable bit for channel1 */\r
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
-\r
- /* Configure the Output Fast mode */\r
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
- htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
- /* Configure the Channel 2 in PWM mode */\r
- TIM_OC2_SetConfig(htim->Instance, sConfig);\r
-\r
- /* Set the Preload enable bit for channel2 */\r
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
-\r
- /* Configure the Output Fast mode */\r
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
- /* Configure the Channel 3 in PWM mode */\r
- TIM_OC3_SetConfig(htim->Instance, sConfig);\r
-\r
- /* Set the Preload enable bit for channel3 */\r
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
-\r
- /* Configure the Output Fast mode */\r
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
- htim->Instance->CCMR2 |= sConfig->OCFastMode;\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
- /* Configure the Channel 4 in PWM mode */\r
- TIM_OC4_SetConfig(htim->Instance, sConfig);\r
-\r
- /* Set the Preload enable bit for channel4 */\r
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
-\r
- /* Configure the Output Fast mode */\r
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM One Pulse Channels according to the specified\r
- * parameters in the TIM_OnePulse_InitTypeDef.\r
- * @param htim : TIM One Pulse handle\r
- * @param sConfig : TIM One Pulse configuration structure\r
- * @param OutputChannel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @param InputChannel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)\r
-{\r
- TIM_OC_InitTypeDef temp1;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r
- assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r
-\r
- if(OutputChannel != InputChannel)\r
- {\r
- __HAL_LOCK(htim);\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Extract the Ouput compare configuration from sConfig structure */\r
- temp1.OCMode = sConfig->OCMode;\r
- temp1.Pulse = sConfig->Pulse;\r
- temp1.OCPolarity = sConfig->OCPolarity;\r
- temp1.OCNPolarity = sConfig->OCNPolarity;\r
- temp1.OCIdleState = sConfig->OCIdleState;\r
- temp1.OCNIdleState = sConfig->OCNIdleState;\r
-\r
- switch (OutputChannel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-\r
- TIM_OC1_SetConfig(htim->Instance, &temp1);\r
- }\r
- break;\r
- case TIM_CHANNEL_2:\r
- {\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
- TIM_OC2_SetConfig(htim->Instance, &temp1);\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
- switch (InputChannel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-\r
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r
- sConfig->ICSelection, sConfig->ICFilter);\r
-\r
- /* Reset the IC1PSC Bits */\r
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
-\r
- /* Select the Trigger source */\r
- htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
- htim->Instance->SMCR |= TIM_TS_TI1FP1;\r
-\r
- /* Select the Slave Mode */\r
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
- }\r
- break;\r
- case TIM_CHANNEL_2:\r
- {\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r
- sConfig->ICSelection, sConfig->ICFilter);\r
-\r
- /* Reset the IC2PSC Bits */\r
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
-\r
- /* Select the Trigger source */\r
- htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
- htim->Instance->SMCR |= TIM_TS_TI2FP2;\r
-\r
- /* Select the Slave Mode */\r
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
- else\r
- {\r
- return HAL_ERROR;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral \r
- * @param htim : TIM handle\r
- * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMABASE_CR1 \r
- * @arg TIM_DMABASE_CR2\r
- * @arg TIM_DMABASE_SMCR\r
- * @arg TIM_DMABASE_DIER\r
- * @arg TIM_DMABASE_SR\r
- * @arg TIM_DMABASE_EGR\r
- * @arg TIM_DMABASE_CCMR1\r
- * @arg TIM_DMABASE_CCMR2\r
- * @arg TIM_DMABASE_CCER\r
- * @arg TIM_DMABASE_CNT \r
- * @arg TIM_DMABASE_PSC \r
- * @arg TIM_DMABASE_ARR\r
- * @arg TIM_DMABASE_RCR\r
- * @arg TIM_DMABASE_CCR1\r
- * @arg TIM_DMABASE_CCR2\r
- * @arg TIM_DMABASE_CCR3 \r
- * @arg TIM_DMABASE_CCR4\r
- * @arg TIM_DMABASE_BDTR\r
- * @arg TIM_DMABASE_DCR\r
- * @param BurstRequestSrc : TIM DMA Request sources\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
- * @arg TIM_DMA_COM: TIM Commutation DMA source\r
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
- * @param BurstBuffer : The Buffer address.\r
- * @param BurstLength : DMA Burst length. This parameter can be one value\r
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
- uint32_t* BurstBuffer, uint32_t BurstLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if((BurstBuffer == 0U) && (BurstLength > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
- switch(BurstRequestSrc)\r
- {\r
- case TIM_DMA_UPDATE:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_CC1:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_CC2:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_CC3:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_CC4:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_COM:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_TRIGGER:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
- /* configure the DMA Burst Mode */\r
- htim->Instance->DCR = BurstBaseAddress | BurstLength;\r
-\r
- /* Enable the TIM DMA Request */\r
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
-\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM DMA Burst mode \r
- * @param htim : TIM handle\r
- * @param BurstRequestSrc : TIM DMA Request sources to disable\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
-\r
- /* Abort the DMA transfer (at least disable the DMA channel) */\r
- switch(BurstRequestSrc)\r
- {\r
- case TIM_DMA_UPDATE:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r
- }\r
- break;\r
- case TIM_DMA_CC1:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r
- }\r
- break;\r
- case TIM_DMA_CC2:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r
- }\r
- break;\r
- case TIM_DMA_CC3:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r
- }\r
- break;\r
- case TIM_DMA_CC4:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r
- }\r
- break;\r
- case TIM_DMA_COM:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
- }\r
- break;\r
- case TIM_DMA_TRIGGER:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the TIM Update DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory \r
- * @param htim : TIM handle\r
- * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMABASE_CR1 \r
- * @arg TIM_DMABASE_CR2\r
- * @arg TIM_DMABASE_SMCR\r
- * @arg TIM_DMABASE_DIER\r
- * @arg TIM_DMABASE_SR\r
- * @arg TIM_DMABASE_EGR\r
- * @arg TIM_DMABASE_CCMR1\r
- * @arg TIM_DMABASE_CCMR2\r
- * @arg TIM_DMABASE_CCER\r
- * @arg TIM_DMABASE_CNT \r
- * @arg TIM_DMABASE_PSC \r
- * @arg TIM_DMABASE_ARR\r
- * @arg TIM_DMABASE_RCR\r
- * @arg TIM_DMABASE_CCR1\r
- * @arg TIM_DMABASE_CCR2\r
- * @arg TIM_DMABASE_CCR3 \r
- * @arg TIM_DMABASE_CCR4\r
- * @arg TIM_DMABASE_BDTR\r
- * @arg TIM_DMABASE_DCR\r
- * @param BurstRequestSrc : TIM DMA Request sources\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
- * @arg TIM_DMA_COM: TIM Commutation DMA source\r
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
- * @param BurstBuffer : The Buffer address.\r
- * @param BurstLength : DMA Burst length. This parameter can be one value\r
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
- uint32_t *BurstBuffer, uint32_t BurstLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if((BurstBuffer == 0U) && (BurstLength > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
- switch(BurstRequestSrc)\r
- {\r
- case TIM_DMA_UPDATE:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_CC1:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_CC2:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_CC3:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_CC4:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_COM:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- case TIM_DMA_TRIGGER:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- /* configure the DMA Burst Mode */\r
- htim->Instance->DCR = BurstBaseAddress | BurstLength;\r
-\r
- /* Enable the TIM DMA Request */\r
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
-\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stop the DMA burst reading \r
- * @param htim : TIM handle\r
- * @param BurstRequestSrc : TIM DMA Request sources to disable.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
-\r
- /* Abort the DMA transfer (at least disable the DMA channel) */\r
- switch(BurstRequestSrc)\r
- {\r
- case TIM_DMA_UPDATE:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r
- }\r
- break;\r
- case TIM_DMA_CC1:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r
- }\r
- break;\r
- case TIM_DMA_CC2:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r
- }\r
- break;\r
- case TIM_DMA_CC3:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r
- }\r
- break;\r
- case TIM_DMA_CC4:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r
- }\r
- break;\r
- case TIM_DMA_COM:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
- }\r
- break;\r
- case TIM_DMA_TRIGGER:\r
- {\r
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the TIM Update DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Generate a software event\r
- * @param htim : TIM handle\r
- * @param EventSource : specifies the event source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r
- * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r
- * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r
- * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r
- * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r
- * @arg TIM_EVENTSOURCE_COM: Timer COM event source \r
- * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r
- * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\r
- * @note TIM6 and TIM7 can only generate an update event.\r
- * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.\r
- * @retval HAL status\r
- */\r
-\r
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(htim);\r
-\r
- /* Change the TIM state */\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Set the event sources */\r
- htim->Instance->EGR = EventSource;\r
-\r
- /* Change the TIM state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Configures the OCRef clear feature\r
- * @param htim : TIM handle\r
- * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that\r
- * contains the OCREF clear feature and parameters for the TIM peripheral.\r
- * @param Channel : specifies the TIM Channel\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1\r
- * @arg TIM_CHANNEL_2: TIM Channel 2\r
- * @arg TIM_CHANNEL_3: TIM Channel 3\r
- * @arg TIM_CHANNEL_4: TIM Channel 4\r
- * @retval HAL status\r
- */ \r
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)\r
-{\r
- uint32_t tmpsmcr = 0U;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(htim);\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- switch (sClearInputConfig->ClearInputSource)\r
- {\r
- case TIM_CLEARINPUTSOURCE_NONE:\r
- {\r
-\r
- /* Clear the ETR Bits */\r
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
-\r
- /* Set TIMx_SMCR */\r
- htim->Instance->SMCR = tmpsmcr;\r
- }\r
- break;\r
-\r
- case TIM_CLEARINPUTSOURCE_ETR:\r
- {\r
- TIM_ETR_SetConfig(htim->Instance,\r
- sClearInputConfig->ClearInputPrescaler,\r
- sClearInputConfig->ClearInputPolarity,\r
- sClearInputConfig->ClearInputFilter);\r
-\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- if(sClearInputConfig->ClearInputState != RESET)\r
- {\r
- /* Enable the Ocref clear feature for Channel 1 */\r
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;\r
- }\r
- else\r
- {\r
- /* Disable the Ocref clear feature for Channel 1 */\r
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;\r
- }\r
- }\r
- break;\r
- case TIM_CHANNEL_2:\r
- {\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
- if(sClearInputConfig->ClearInputState != RESET)\r
- {\r
- /* Enable the Ocref clear feature for Channel 2 */\r
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;\r
- }\r
- else\r
- {\r
- /* Disable the Ocref clear feature for Channel 2 */\r
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;\r
- }\r
- }\r
- break;\r
- case TIM_CHANNEL_3:\r
- {\r
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
- if(sClearInputConfig->ClearInputState != RESET)\r
- {\r
- /* Enable the Ocref clear feature for Channel 3 */\r
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;\r
- }\r
- else\r
- {\r
- /* Disable the Ocref clear feature for Channel 3 */\r
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;\r
- }\r
- }\r
- break;\r
- case TIM_CHANNEL_4:\r
- {\r
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
- if(sClearInputConfig->ClearInputState != RESET)\r
- {\r
- /* Enable the Ocref clear feature for Channel 4 */\r
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;\r
- }\r
- else\r
- {\r
- /* Disable the Ocref clear feature for Channel 4 */\r
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;\r
- }\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Configures the clock source to be used\r
- * @param htim : TIM handle\r
- * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that\r
- * contains the clock source information for the TIM peripheral.\r
- * @retval HAL status\r
- */ \r
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)\r
-{\r
- uint32_t tmpsmcr = 0U;\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(htim);\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r
-\r
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r
- tmpsmcr = htim->Instance->SMCR;\r
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
- htim->Instance->SMCR = tmpsmcr;\r
-\r
- switch (sClockSourceConfig->ClockSource)\r
- {\r
- case TIM_CLOCKSOURCE_INTERNAL:\r
- {\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
- /* Disable slave mode to clock the prescaler directly with the internal clock */\r
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
- }\r
- break;\r
-\r
- case TIM_CLOCKSOURCE_ETRMODE1:\r
- {\r
- /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/\r
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
-\r
- /* Check ETR input conditioning related parameters */\r
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
- \r
- /* Configure the ETR Clock source */\r
- TIM_ETR_SetConfig(htim->Instance,\r
- sClockSourceConfig->ClockPrescaler,\r
- sClockSourceConfig->ClockPolarity,\r
- sClockSourceConfig->ClockFilter);\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = htim->Instance->SMCR;\r
- /* Reset the SMS and TS Bits */\r
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
- /* Select the External clock mode1 and the ETRF trigger */\r
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r
- /* Write to TIMx SMCR */\r
- htim->Instance->SMCR = tmpsmcr;\r
- }\r
- break;\r
-\r
- case TIM_CLOCKSOURCE_ETRMODE2:\r
- {\r
- /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/\r
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));\r
-\r
- /* Check ETR input conditioning related parameters */\r
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
- \r
- /* Configure the ETR Clock source */\r
- TIM_ETR_SetConfig(htim->Instance,\r
- sClockSourceConfig->ClockPrescaler,\r
- sClockSourceConfig->ClockPolarity,\r
- sClockSourceConfig->ClockFilter);\r
- /* Enable the External clock mode2 */\r
- htim->Instance->SMCR |= TIM_SMCR_ECE;\r
- }\r
- break;\r
-\r
- case TIM_CLOCKSOURCE_TI1:\r
- {\r
- /* Check whether or not the timer instance supports external clock mode 1 */\r
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
-\r
- /* Check TI1 input conditioning related parameters */\r
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
- \r
- TIM_TI1_ConfigInputStage(htim->Instance,\r
- sClockSourceConfig->ClockPolarity,\r
- sClockSourceConfig->ClockFilter);\r
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r
- }\r
- break;\r
- case TIM_CLOCKSOURCE_TI2:\r
- {\r
- /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/\r
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
-\r
- /* Check TI2 input conditioning related parameters */\r
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
-\r
- TIM_TI2_ConfigInputStage(htim->Instance,\r
- sClockSourceConfig->ClockPolarity,\r
- sClockSourceConfig->ClockFilter);\r
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r
- }\r
- break;\r
- case TIM_CLOCKSOURCE_TI1ED:\r
- {\r
- /* Check whether or not the timer instance supports external clock mode 1 */\r
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
-\r
- /* Check TI1 input conditioning related parameters */\r
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
-\r
- TIM_TI1_ConfigInputStage(htim->Instance,\r
- sClockSourceConfig->ClockPolarity,\r
- sClockSourceConfig->ClockFilter);\r
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r
- }\r
- break;\r
- case TIM_CLOCKSOURCE_ITR0:\r
- {\r
- /* Check whether or not the timer instance supports external clock mode 1 */\r
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
-\r
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);\r
- }\r
- break;\r
- case TIM_CLOCKSOURCE_ITR1:\r
- {\r
- /* Check whether or not the timer instance supports external clock mode 1 */\r
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
-\r
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);\r
- }\r
- break;\r
- case TIM_CLOCKSOURCE_ITR2:\r
- {\r
- /* Check whether or not the timer instance supports external clock mode 1 */\r
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
-\r
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);\r
- }\r
- break;\r
- case TIM_CLOCKSOURCE_ITR3:\r
- {\r
- /* Check whether or not the timer instance supports external clock mode 1 */\r
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
-\r
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Selects the signal connected to the TI1 input: direct from CH1_input\r
- * or a XOR combination between CH1_input, CH2_input & CH3_input\r
- * @param htim : TIM handle.\r
- * @param TI1_Selection : Indicate whether or not channel 1 is connected to the\r
- * output of a XOR gate.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r
- * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r
- * pins are connected to the TI1 input (XOR combination)\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r
-{\r
- uint32_t tmpcr2 = 0U;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r
-\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = htim->Instance->CR2;\r
-\r
- /* Reset the TI1 selection */\r
- tmpcr2 &= ~TIM_CR2_TI1S;\r
-\r
- /* Set the the TI1 selection */\r
- tmpcr2 |= TI1_Selection;\r
-\r
- /* Write to TIMxCR2 */\r
- htim->Instance->CR2 = tmpcr2;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIM in Slave mode\r
- * @param htim : TIM handle.\r
- * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that\r
- * contains the selected trigger (internal trigger input, filtered\r
- * timer input or external trigger input) and the ) and the Slave \r
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
-\r
- __HAL_LOCK(htim);\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);\r
-\r
- /* Disable Trigger Interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);\r
-\r
- /* Disable Trigger DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
-\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
- }\r
-\r
-/**\r
- * @brief Configures the TIM in Slave mode in interrupt mode\r
- * @param htim: TIM handle.\r
- * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that\r
- * contains the selected trigger (internal trigger input, filtered\r
- * timer input or external trigger input) and the ) and the Slave \r
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,\r
- TIM_SlaveConfigTypeDef * sSlaveConfig)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
-\r
- __HAL_LOCK(htim);\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);\r
-\r
- /* Enable Trigger Interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r
-\r
- /* Disable Trigger DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
-\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Read the captured value from Capture Compare unit\r
- * @param htim : TIM handle.\r
- * @param Channel : TIM Channels to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1 : TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2 : TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3 : TIM Channel 3 selected\r
- * @arg TIM_CHANNEL_4 : TIM Channel 4 selected\r
- * @retval Captured value\r
- */\r
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- uint32_t tmpreg = 0U;\r
-\r
- __HAL_LOCK(htim);\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
-\r
- /* Return the capture 1 value */\r
- tmpreg = htim->Instance->CCR1;\r
-\r
- break;\r
- }\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
-\r
- /* Return the capture 2 value */\r
- tmpreg = htim->Instance->CCR2;\r
-\r
- break;\r
- }\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
-\r
- /* Return the capture 3 value */\r
- tmpreg = htim->Instance->CCR3;\r
-\r
- break;\r
- }\r
-\r
- case TIM_CHANNEL_4:\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
-\r
- /* Return the capture 4 value */\r
- tmpreg = htim->Instance->CCR4;\r
-\r
- break;\r
- }\r
-\r
- default:\r
- break;\r
- }\r
-\r
- __HAL_UNLOCK(htim);\r
- return tmpreg;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
- * @brief TIM Callbacks functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### TIM Callbacks functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides TIM callback functions:\r
- (+) Timer Period elapsed callback\r
- (+) Timer Output Compare callback\r
- (+) Timer Input capture callback\r
- (+) Timer Trigger callback\r
- (+) Timer Error callback\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Period elapsed callback in non blocking mode \r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r
- */\r
-\r
-}\r
-/**\r
- * @brief Output Compare callback in non blocking mode \r
- * @param htim : TIM OC handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r
- */\r
-}\r
-/**\r
- * @brief Input Capture callback in non blocking mode \r
- * @param htim : TIM IC handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the __HAL_TIM_IC_CaptureCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief PWM Pulse finished callback in non blocking mode \r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Hall Trigger detection callback in non blocking mode \r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_TriggerCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Timer error callback in non blocking mode \r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIM_ErrorCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions \r
- * @brief Peripheral State functions \r
- *\r
-@verbatim \r
- ==============================================================================\r
- ##### Peripheral State functions #####\r
- ==============================================================================\r
- [..]\r
- This subsection permit to get in run-time the status of the peripheral \r
- and the data flow.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Return the TIM Base state\r
- * @param htim : TIM Base handle\r
- * @retval HAL state\r
- */\r
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r
-{\r
- return htim->State;\r
-}\r
-\r
-/**\r
- * @brief Return the TIM OC state\r
- * @param htim : TIM Ouput Compare handle\r
- * @retval HAL state\r
- */\r
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r
-{\r
- return htim->State;\r
-}\r
-\r
-/**\r
- * @brief Return the TIM PWM state\r
- * @param htim : TIM handle\r
- * @retval HAL state\r
- */\r
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r
-{\r
- return htim->State;\r
-}\r
-\r
-/**\r
- * @brief Return the TIM Input Capture state\r
- * @param htim : TIM IC handle\r
- * @retval HAL state\r
- */\r
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r
-{\r
- return htim->State;\r
-}\r
-\r
-/**\r
- * @brief Return the TIM One Pulse Mode state\r
- * @param htim : TIM OPM handle\r
- * @retval HAL state\r
- */\r
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r
-{\r
- return htim->State;\r
-}\r
-\r
-/**\r
- * @brief Return the TIM Encoder Mode state\r
- * @param htim : TIM Encoder handle\r
- * @retval HAL state\r
- */\r
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r
-{\r
- return htim->State;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup TIM_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief TIM DMA error callback \r
- * @param hdma : pointer to DMA handle.\r
- * @retval None\r
- */\r
-void TIM_DMAError(DMA_HandleTypeDef *hdma)\r
-{\r
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
-\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- HAL_TIM_ErrorCallback(htim);\r
-}\r
-\r
-/**\r
- * @brief TIM DMA Delay Pulse complete callback.\r
- * @param hdma : pointer to DMA handle.\r
- * @retval None\r
- */\r
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
-\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
- {\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
- }\r
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
- {\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
- }\r
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
- {\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
- }\r
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
- {\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
- }\r
-\r
- HAL_TIM_PWM_PulseFinishedCallback(htim);\r
-\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-}\r
-/**\r
- * @brief TIM DMA Capture complete callback.\r
- * @param hdma : pointer to DMA handle.\r
- * @retval None\r
- */\r
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
-\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
- {\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
- }\r
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
- {\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
- }\r
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
- {\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
- }\r
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
- {\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
- }\r
-\r
- HAL_TIM_IC_CaptureCallback(htim);\r
-\r
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
-}\r
-\r
-/**\r
- * @brief TIM DMA Period Elapse complete callback.\r
- * @param hdma : pointer to DMA handle.\r
- * @retval None\r
- */\r
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
-\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- HAL_TIM_PeriodElapsedCallback(htim);\r
-}\r
-\r
-/**\r
- * @brief TIM DMA Trigger callback.\r
- * @param hdma : pointer to DMA handle.\r
- * @retval None\r
- */\r
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
-\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- HAL_TIM_TriggerCallback(htim);\r
-}\r
-\r
-/**\r
- * @brief Time Base configuration\r
- * @param TIMx : TIM periheral\r
- * @param Structure : TIM Base configuration structure\r
- * @retval None\r
- */\r
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r
-{\r
- uint32_t tmpcr1 = 0U;\r
- tmpcr1 = TIMx->CR1;\r
-\r
- /* Set TIM Time Base Unit parameters ---------------------------------------*/\r
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))\r
- {\r
- /* Select the Counter Mode */\r
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r
- tmpcr1 |= Structure->CounterMode;\r
- }\r
-\r
- if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))\r
- {\r
- /* Set the clock division */\r
- tmpcr1 &= ~TIM_CR1_CKD;\r
- tmpcr1 |= (uint32_t)Structure->ClockDivision;\r
- }\r
-\r
- /* Set the auto-reload preload */\r
- tmpcr1 &= ~TIM_CR1_ARPE;\r
- tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;\r
-\r
- TIMx->CR1 = tmpcr1;\r
-\r
- /* Set the Autoreload value */\r
- TIMx->ARR = (uint32_t)Structure->Period ;\r
-\r
- /* Set the Prescaler value */\r
- TIMx->PSC = (uint32_t)Structure->Prescaler;\r
-\r
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))\r
- {\r
- /* Set the Repetition Counter value */\r
- TIMx->RCR = Structure->RepetitionCounter;\r
- }\r
-\r
- /* Generate an update event to reload the Prescaler \r
- and the repetition counter(only for TIM1 and TIM8) value immediatly */\r
- TIMx->EGR = TIM_EGR_UG;\r
-}\r
-\r
-/**\r
- * @brief Time Ouput Compare 1 configuration\r
- * @param TIMx to select the TIM peripheral\r
- * @param OC_Config : The ouput configuration structure\r
- * @retval None\r
- */\r
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
-{\r
- uint32_t tmpccmrx = 0U;\r
- uint32_t tmpccer = 0U;\r
- uint32_t tmpcr2 = 0U;\r
-\r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= ~TIM_CCER_CC1E;\r
-\r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
-\r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
-\r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= ~TIM_CCMR1_OC1M;\r
- tmpccmrx &= ~TIM_CCMR1_CC1S;\r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= OC_Config->OCMode;\r
-\r
- /* Reset the Output Polarity level */\r
- tmpccer &= ~TIM_CCER_CC1P;\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= OC_Config->OCPolarity;\r
-\r
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))\r
- {\r
- /* Check parameters */\r
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
-\r
- /* Reset the Output N Polarity level */\r
- tmpccer &= ~TIM_CCER_CC1NP;\r
- /* Set the Output N Polarity */\r
- tmpccer |= OC_Config->OCNPolarity;\r
- /* Reset the Output N State */\r
- tmpccer &= ~TIM_CCER_CC1NE;\r
- }\r
-\r
- if(IS_TIM_BREAK_INSTANCE(TIMx))\r
- {\r
- /* Check parameters */\r
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
-\r
- /* Reset the Output Compare and Output Compare N IDLE State */\r
- tmpcr2 &= ~TIM_CR2_OIS1;\r
- tmpcr2 &= ~TIM_CR2_OIS1N;\r
- /* Set the Output Idle state */\r
- tmpcr2 |= OC_Config->OCIdleState;\r
- /* Set the Output N Idle state */\r
- tmpcr2 |= OC_Config->OCNIdleState;\r
- }\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
-\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR1 = OC_Config->Pulse;\r
-\r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Time Ouput Compare 2 configuration\r
- * @param TIMx to select the TIM peripheral\r
- * @param OC_Config : The ouput configuration structure\r
- * @retval None\r
- */\r
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
-{\r
- uint32_t tmpccmrx = 0U;\r
- uint32_t tmpccer = 0U;\r
- uint32_t tmpcr2 = 0U;\r
-\r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= ~TIM_CCER_CC2E;\r
-\r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
-\r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
-\r
- /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
- tmpccmrx &= ~TIM_CCMR1_OC2M;\r
- tmpccmrx &= ~TIM_CCMR1_CC2S;\r
-\r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (OC_Config->OCMode << 8U);\r
-\r
- /* Reset the Output Polarity level */\r
- tmpccer &= ~TIM_CCER_CC2P;\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (OC_Config->OCPolarity << 4U);\r
-\r
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))\r
- {\r
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
-\r
- /* Reset the Output N Polarity level */\r
- tmpccer &= ~TIM_CCER_CC2NP;\r
- /* Set the Output N Polarity */\r
- tmpccer |= (OC_Config->OCNPolarity << 4U);\r
- /* Reset the Output N State */\r
- tmpccer &= ~TIM_CCER_CC2NE;\r
-\r
- }\r
-\r
- if(IS_TIM_BREAK_INSTANCE(TIMx))\r
- {\r
- /* Check parameters */\r
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
-\r
- /* Reset the Output Compare and Output Compare N IDLE State */\r
- tmpcr2 &= ~TIM_CR2_OIS2;\r
- tmpcr2 &= ~TIM_CR2_OIS2N;\r
- /* Set the Output Idle state */\r
- tmpcr2 |= (OC_Config->OCIdleState << 2);\r
- /* Set the Output N Idle state */\r
- tmpcr2 |= (OC_Config->OCNIdleState << 2);\r
- }\r
-\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
-\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR2 = OC_Config->Pulse;\r
-\r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Time Ouput Compare 3 configuration\r
- * @param TIMx to select the TIM peripheral\r
- * @param OC_Config : The ouput configuration structure\r
- * @retval None\r
- */\r
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
-{\r
- uint32_t tmpccmrx = 0U;\r
- uint32_t tmpccer = 0U;\r
- uint32_t tmpcr2 = 0U;\r
-\r
- /* Disable the Channel 3: Reset the CC2E Bit */\r
- TIMx->CCER &= ~TIM_CCER_CC3E;\r
-\r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
-\r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
-\r
- /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
- tmpccmrx &= ~TIM_CCMR2_OC3M;\r
- tmpccmrx &= ~TIM_CCMR2_CC3S;\r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= OC_Config->OCMode;\r
-\r
- /* Reset the Output Polarity level */\r
- tmpccer &= ~TIM_CCER_CC3P;\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (OC_Config->OCPolarity << 8U);\r
-\r
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))\r
- {\r
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
-\r
- /* Reset the Output N Polarity level */\r
- tmpccer &= ~TIM_CCER_CC3NP;\r
- /* Set the Output N Polarity */\r
- tmpccer |= (OC_Config->OCNPolarity << 8U);\r
- /* Reset the Output N State */\r
- tmpccer &= ~TIM_CCER_CC3NE;\r
- }\r
-\r
- if(IS_TIM_BREAK_INSTANCE(TIMx))\r
- {\r
- /* Check parameters */\r
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
-\r
- /* Reset the Output Compare and Output Compare N IDLE State */\r
- tmpcr2 &= ~TIM_CR2_OIS3;\r
- tmpcr2 &= ~TIM_CR2_OIS3N;\r
- /* Set the Output Idle state */\r
- tmpcr2 |= (OC_Config->OCIdleState << 4U);\r
- /* Set the Output N Idle state */\r
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);\r
- }\r
-\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
-\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR3 = OC_Config->Pulse;\r
-\r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Time Ouput Compare 4 configuration\r
- * @param TIMx to select the TIM peripheral\r
- * @param OC_Config : The ouput configuration structure\r
- * @retval None\r
- */\r
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
-{\r
- uint32_t tmpccmrx = 0U;\r
- uint32_t tmpccer = 0U;\r
- uint32_t tmpcr2 = 0U;\r
-\r
- /* Disable the Channel 4: Reset the CC4E Bit */\r
- TIMx->CCER &= ~TIM_CCER_CC4E;\r
-\r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
-\r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
-\r
- /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
- tmpccmrx &= ~TIM_CCMR2_OC4M;\r
- tmpccmrx &= ~TIM_CCMR2_CC4S;\r
-\r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (OC_Config->OCMode << 8U);\r
-\r
- /* Reset the Output Polarity level */\r
- tmpccer &= ~TIM_CCER_CC4P;\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (OC_Config->OCPolarity << 12U);\r
-\r
- if(IS_TIM_BREAK_INSTANCE(TIMx))\r
- {\r
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
-\r
- /* Reset the Output Compare IDLE State */\r
- tmpcr2 &= ~TIM_CR2_OIS4;\r
- /* Set the Output Idle state */\r
- tmpcr2 |= (OC_Config->OCIdleState << 6);\r
- }\r
-\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
-\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR4 = OC_Config->Pulse;\r
-\r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-\r
-/**\r
- * @brief Time Slave configuration\r
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
- * the configuration information for TIM module.\r
- * @param sSlaveConfig: The slave configuration structure\r
- * @retval None\r
- */\r
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
- TIM_SlaveConfigTypeDef * sSlaveConfig)\r
-{\r
- uint32_t tmpsmcr = 0U;\r
- uint32_t tmpccmr1 = 0U;\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = htim->Instance->SMCR;\r
-\r
- /* Reset the Trigger Selection Bits */\r
- tmpsmcr &= ~TIM_SMCR_TS;\r
- /* Set the Input Trigger source */\r
- tmpsmcr |= sSlaveConfig->InputTrigger;\r
-\r
- /* Reset the slave mode Bits */\r
- tmpsmcr &= ~TIM_SMCR_SMS;\r
- /* Set the slave mode */\r
- tmpsmcr |= sSlaveConfig->SlaveMode;\r
-\r
- /* Write to TIMx SMCR */\r
- htim->Instance->SMCR = tmpsmcr;\r
-\r
- /* Configure the trigger prescaler, filter, and polarity */\r
- switch (sSlaveConfig->InputTrigger)\r
- {\r
- case TIM_TS_ETRF:\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
- /* Configure the ETR Trigger source */\r
- TIM_ETR_SetConfig(htim->Instance,\r
- sSlaveConfig->TriggerPrescaler,\r
- sSlaveConfig->TriggerPolarity,\r
- sSlaveConfig->TriggerFilter);\r
- }\r
- break;\r
-\r
- case TIM_TS_TI1F_ED:\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
-\r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- tmpccer = htim->Instance->CCER;\r
- htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
- tmpccmr1 = htim->Instance->CCMR1;\r
-\r
- /* Set the filter */\r
- tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);\r
-\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- htim->Instance->CCMR1 = tmpccmr1;\r
- htim->Instance->CCER = tmpccer;\r
-\r
- }\r
- break;\r
-\r
- case TIM_TS_TI1FP1:\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
-\r
- /* Configure TI1 Filter and Polarity */\r
- TIM_TI1_ConfigInputStage(htim->Instance,\r
- sSlaveConfig->TriggerPolarity,\r
- sSlaveConfig->TriggerFilter);\r
- }\r
- break;\r
-\r
- case TIM_TS_TI2FP2:\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
-\r
- /* Configure TI2 Filter and Polarity */\r
- TIM_TI2_ConfigInputStage(htim->Instance,\r
- sSlaveConfig->TriggerPolarity,\r
- sSlaveConfig->TriggerFilter);\r
- }\r
- break;\r
-\r
- case TIM_TS_ITR0:\r
- {\r
- /* Check the parameter */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
- }\r
- break;\r
-\r
- case TIM_TS_ITR1:\r
- {\r
- /* Check the parameter */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
- }\r
- break;\r
-\r
- case TIM_TS_ITR2:\r
- {\r
- /* Check the parameter */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
- }\r
- break;\r
-\r
- case TIM_TS_ITR3:\r
- {\r
- /* Check the parameter */\r
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configure the TI1 as Input.\r
- * @param TIMx to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPOLARITY_RISING\r
- * @arg TIM_ICPOLARITY_FALLING\r
- * @arg TIM_ICPOLARITY_BOTHEDGE\r
- * @param TIM_ICSelection : specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.\r
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.\r
- * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.\r
- * @param TIM_ICFilter : Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 \r
- * (on channel2 path) is used as the input signal. Therefore CCMR1 must be \r
- * protected against un-initialized filter and polarity values.\r
- */\r
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
- uint32_t TIM_ICFilter)\r
-{\r
- uint32_t tmpccmr1 = 0U;\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= ~TIM_CCER_CC1E;\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
-\r
- /* Select the Input */\r
- if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r
- {\r
- tmpccmr1 &= ~TIM_CCMR1_CC1S;\r
- tmpccmr1 |= TIM_ICSelection;\r
- }\r
- else\r
- {\r
- tmpccmr1 |= TIM_CCMR1_CC1S_0;\r
- }\r
-\r
- /* Set the filter */\r
- tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
- tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);\r
-\r
- /* Select the Polarity and set the CC1E Bit */\r
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
- tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
-\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the Polarity and Filter for TI1.\r
- * @param TIMx to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPOLARITY_RISING \r
- * @arg TIM_ICPOLARITY_FALLING\r
- * @arg TIM_ICPOLARITY_BOTHEDGE\r
- * @param TIM_ICFilter : Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
-{\r
- uint32_t tmpccmr1 = 0U;\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- tmpccer = TIMx->CCER;\r
- TIMx->CCER &= ~TIM_CCER_CC1E;\r
- tmpccmr1 = TIMx->CCMR1;\r
-\r
- /* Set the filter */\r
- tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
- tmpccmr1 |= (TIM_ICFilter << 4U);\r
-\r
- /* Select the Polarity and set the CC1E Bit */\r
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
- tmpccer |= TIM_ICPolarity;\r
-\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI2 as Input.\r
- * @param TIMx to select the TIM peripheral\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPOLARITY_RISING \r
- * @arg TIM_ICPOLARITY_FALLING\r
- * @arg TIM_ICPOLARITY_BOTHEDGE\r
- * @param TIM_ICSelection : specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.\r
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.\r
- * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.\r
- * @param TIM_ICFilter : Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 \r
- * (on channel1 path) is used as the input signal. Therefore CCMR1 must be \r
- * protected against un-initialized filter and polarity values.\r
- */\r
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
- uint32_t TIM_ICFilter)\r
-{\r
- uint32_t tmpccmr1 = 0U;\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= ~TIM_CCER_CC2E;\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
-\r
- /* Select the Input */\r
- tmpccmr1 &= ~TIM_CCMR1_CC2S;\r
- tmpccmr1 |= (TIM_ICSelection << 8U);\r
-\r
- /* Set the filter */\r
- tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
- tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);\r
-\r
- /* Select the Polarity and set the CC2E Bit */\r
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
- tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
-\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1 ;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the Polarity and Filter for TI2.\r
- * @param TIMx to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPOLARITY_RISING \r
- * @arg TIM_ICPOLARITY_FALLING\r
- * @arg TIM_ICPOLARITY_BOTHEDGE\r
- * @param TIM_ICFilter : Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
-{\r
- uint32_t tmpccmr1 = 0U;\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= ~TIM_CCER_CC2E;\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
-\r
- /* Set the filter */\r
- tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
- tmpccmr1 |= (TIM_ICFilter << 12U);\r
-\r
- /* Select the Polarity and set the CC2E Bit */\r
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
- tmpccer |= (TIM_ICPolarity << 4U);\r
-\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1 ;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI3 as Input.\r
- * @param TIMx to select the TIM peripheral\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPOLARITY_RISING \r
- * @arg TIM_ICPOLARITY_FALLING\r
- * @param TIM_ICSelection : specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.\r
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.\r
- * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.\r
- * @param TIM_ICFilter : Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 \r
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r
- * protected against un-initialized filter and polarity values.\r
- */\r
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
- uint32_t TIM_ICFilter)\r
-{\r
- uint32_t tmpccmr2 = 0U;\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Disable the Channel 3: Reset the CC3E Bit */\r
- TIMx->CCER &= ~TIM_CCER_CC3E;\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
-\r
- /* Select the Input */\r
- tmpccmr2 &= ~TIM_CCMR2_CC3S;\r
- tmpccmr2 |= TIM_ICSelection;\r
-\r
- /* Set the filter */\r
- tmpccmr2 &= ~TIM_CCMR2_IC3F;\r
- tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);\r
-\r
- /* Select the Polarity and set the CC3E Bit */\r
- tmpccer &= ~(TIM_CCER_CC3P);\r
- tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P));\r
-\r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI4 as Input.\r
- * @param TIMx to select the TIM peripheral\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPOLARITY_RISING \r
- * @arg TIM_ICPOLARITY_FALLING\r
- * @param TIM_ICSelection : specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.\r
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.\r
- * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.\r
- * @param TIM_ICFilter : Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 \r
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r
- * protected against un-initialized filter and polarity values.\r
- * @retval None\r
- */\r
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
- uint32_t TIM_ICFilter)\r
-{\r
- uint32_t tmpccmr2 = 0U;\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Disable the Channel 4: Reset the CC4E Bit */\r
- TIMx->CCER &= ~TIM_CCER_CC4E;\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
-\r
- /* Select the Input */\r
- tmpccmr2 &= ~TIM_CCMR2_CC4S;\r
- tmpccmr2 |= (TIM_ICSelection << 8U);\r
-\r
- /* Set the filter */\r
- tmpccmr2 &= ~TIM_CCMR2_IC4F;\r
- tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);\r
-\r
- /* Select the Polarity and set the CC4E Bit */\r
- tmpccer &= ~TIM_CCER_CC4P;\r
- tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);\r
-\r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer ;\r
-}\r
-\r
-/**\r
- * @brief Selects the Input Trigger source\r
- * @param TIMx to select the TIM peripheral\r
- * @param InputTriggerSource : The Input Trigger source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TS_ITR0 : Internal Trigger 0\r
- * @arg TIM_TS_ITR1 : Internal Trigger 1\r
- * @arg TIM_TS_ITR2 : Internal Trigger 2\r
- * @arg TIM_TS_ITR3 : Internal Trigger 3\r
- * @arg TIM_TS_TI1F_ED : TI1 Edge Detector\r
- * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1\r
- * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2\r
- * @arg TIM_TS_ETRF : External Trigger input\r
- * @retval None\r
- */\r
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)\r
-{\r
- uint32_t tmpsmcr = 0U;\r
-\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the TS Bits */\r
- tmpsmcr &= ~TIM_SMCR_TS;\r
- /* Set the Input Trigger source and the slave mode*/\r
- tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-/**\r
- * @brief Configures the TIMx External Trigger (ETR).\r
- * @param TIMx to select the TIM peripheral\r
- * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.\r
- * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity : The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.\r
- * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.\r
- * @param ExtTRGFilter : External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,\r
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r
-{\r
- uint32_t tmpsmcr = 0U;\r
-\r
- tmpsmcr = TIMx->SMCR;\r
-\r
- /* Reset the ETR Bits */\r
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
-\r
- /* Set the Prescaler, the Filter value and the Polarity */\r
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));\r
-\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIM Capture Compare Channel x.\r
- * @param TIMx to select the TIM peripheral\r
- * @param Channel : specifies the TIM Channel\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1\r
- * @arg TIM_CHANNEL_2: TIM Channel 2\r
- * @arg TIM_CHANNEL_3: TIM Channel 3\r
- * @arg TIM_CHANNEL_4: TIM Channel 4\r
- * @param ChannelState : specifies the TIM Channel CCxE bit new state.\r
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.\r
- * @retval None\r
- */\r
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)\r
-{\r
- uint32_t tmp = 0U;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));\r
- assert_param(IS_TIM_CHANNELS(Channel));\r
-\r
- tmp = TIM_CCER_CC1E << Channel;\r
-\r
- /* Reset the CCxE Bit */\r
- TIMx->CCER &= ~tmp;\r
-\r
- /* Set or reset the CCxE Bit */\r
- TIMx->CCER |= (uint32_t)(ChannelState << Channel);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_TIM_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_tim_ex.c\r
- * @author MCD Application Team\r
- * @brief TIM HAL module driver.\r
- * This file provides firmware functions to manage the following\r
- * functionalities of the Timer Extended peripheral:\r
- * + Time Hall Sensor Interface Initialization\r
- * + Time Hall Sensor Interface Start\r
- * + Time Complementary signal bread and dead time configuration\r
- * + Time Master and Slave synchronization configuration\r
- * + Timer remapping capabilities configuration\r
- @verbatim\r
- ==============================================================================\r
- ##### TIMER Extended features #####\r
- ==============================================================================\r
- [..]\r
- The Timer Extended features include:\r
- (#) Complementary outputs with programmable dead-time for :\r
- (++) Output Compare\r
- (++) PWM generation (Edge and Center-aligned Mode)\r
- (++) One-pulse mode output\r
- (#) Synchronization circuit to control the timer with external signals and to\r
- interconnect several timers together.\r
- (#) Break input to put the timer output signals in reset state or in a known state.\r
- (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for\r
- positioning purposes\r
-\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..]\r
- (#) Initialize the TIM low level resources by implementing the following functions\r
- depending from feature used :\r
- (++) Complementary Output Compare : HAL_TIM_OC_MspInit()\r
- (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()\r
- (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()\r
-\r
- (#) Initialize the TIM low level resources :\r
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
- (##) TIM pins configuration\r
- (+++) Enable the clock for the TIM GPIOs using the following function:\r
- __HAL_RCC_GPIOx_CLK_ENABLE();\r
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
-\r
- (#) The external Clock can be configured, if needed (the default clock is the\r
- internal clock from the APBx), using the following function:\r
- HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
- any start function.\r
-\r
- (#) Configure the TIM in the desired functioning mode using one of the\r
- initialization function of this driver:\r
- (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the\r
- Timer Hall Sensor Interface and the commutation event with the corresponding\r
- Interrupt and DMA request if needed (Note that One Timer is used to interface\r
- with the Hall sensor Interface and another Timer should be used to use\r
- the commutation event).\r
-\r
- (#) Activate the TIM peripheral using one of the start functions:\r
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()\r
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()\r
- (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()\r
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().\r
-\r
-\r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
-*/\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/** @addtogroup STM32F1xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup TIMEx TIMEx\r
- * @brief TIM Extended HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_TIM_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions\r
- * @{\r
- */\r
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);\r
-/**\r
- * @}\r
- */\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-\r
-/* Exported functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions\r
- * @{\r
- */\r
-\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions\r
- * @brief Timer Hall Sensor functions\r
- *\r
-@verbatim\r
- ==============================================================================\r
- ##### Timer Hall Sensor functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Initialize and configure TIM HAL Sensor.\r
- (+) De-initialize TIM HAL Sensor.\r
- (+) Start the Hall Sensor Interface.\r
- (+) Stop the Hall Sensor Interface.\r
- (+) Start the Hall Sensor Interface and enable interrupts.\r
- (+) Stop the Hall Sensor Interface and disable interrupts.\r
- (+) Start the Hall Sensor Interface and enable DMA transfers.\r
- (+) Stop the Hall Sensor Interface and disable DMA transfers.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-/**\r
- * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.\r
- * @param htim : TIM Encoder Interface handle\r
- * @param sConfig : TIM Hall Sensor configuration structure\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)\r
-{\r
- TIM_OC_InitTypeDef OC_Config;\r
-\r
- /* Check the TIM handle allocation */\r
- if(htim == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
-\r
- if(htim->State == HAL_TIM_STATE_RESET)\r
- {\r
- /* Allocate lock resource and initialize it */\r
- htim->Lock = HAL_UNLOCKED;\r
- \r
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
- HAL_TIMEx_HallSensor_MspInit(htim);\r
- }\r
-\r
- /* Set the TIM state */\r
- htim->State= HAL_TIM_STATE_BUSY;\r
-\r
- /* Configure the Time base in the Encoder Mode */\r
- TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
-\r
- /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */\r
- TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);\r
-\r
- /* Reset the IC1PSC Bits */\r
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
- /* Set the IC1PSC value */\r
- htim->Instance->CCMR1 |= sConfig->IC1Prescaler;\r
-\r
- /* Enable the Hall sensor interface (XOR function of the three inputs) */\r
- htim->Instance->CR2 |= TIM_CR2_TI1S;\r
-\r
- /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */\r
- htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
- htim->Instance->SMCR |= TIM_TS_TI1F_ED;\r
-\r
- /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */\r
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
- htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;\r
-\r
- /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/\r
- OC_Config.OCFastMode = TIM_OCFAST_DISABLE;\r
- OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\r
- OC_Config.OCMode = TIM_OCMODE_PWM2;\r
- OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\r
- OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\r
- OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\r
- OC_Config.Pulse = sConfig->Commutation_Delay;\r
-\r
- TIM_OC2_SetConfig(htim->Instance, &OC_Config);\r
-\r
- /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\r
- register to 101 */\r
- htim->Instance->CR2 &= ~TIM_CR2_MMS;\r
- htim->Instance->CR2 |= TIM_TRGO_OC2REF;\r
-\r
- /* Initialize the TIM state*/\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief DeInitializes the TIM Hall Sensor interface\r
- * @param htim : TIM Hall Sensor handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_INSTANCE(htim->Instance));\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Disable the TIM Peripheral Clock */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
- HAL_TIMEx_HallSensor_MspDeInit(htim);\r
-\r
- /* Change TIM state */\r
- htim->State = HAL_TIM_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM Hall Sensor MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief DeInitializes TIM Hall Sensor MSP.\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Hall Sensor Interface.\r
- * @param htim : TIM Hall Sensor handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
-\r
- /* Enable the Input Capture channel 1\r
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Hall sensor Interface.\r
- * @param htim : TIM Hall Sensor handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
-\r
- /* Disable the Input Capture channel 1\r
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Hall Sensor Interface in interrupt mode.\r
- * @param htim : TIM Hall Sensor handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
-\r
- /* Enable the capture compare Interrupts 1 event */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-\r
- /* Enable the Input Capture channel 1\r
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Hall Sensor Interface in interrupt mode.\r
- * @param htim : TIM handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
-\r
- /* Disable the Input Capture channel 1\r
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
- /* Disable the capture compare Interrupts event */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Hall Sensor Interface in DMA mode.\r
- * @param htim : TIM Hall Sensor handle\r
- * @param pData : The destination Buffer address.\r
- * @param Length : The length of data to be transferred from TIM peripheral to memory.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if(((uint32_t)pData == 0U) && (Length > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
- /* Enable the Input Capture channel 1\r
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
-\r
- /* Set the DMA Input Capture 1 Callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel for Capture 1*/\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);\r
-\r
- /* Enable the capture compare 1 Interrupt */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Hall Sensor Interface in DMA mode.\r
- * @param htim : TIM handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
-\r
- /* Disable the Input Capture channel 1\r
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
-\r
-\r
- /* Disable the capture compare Interrupts 1 event */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions\r
- * @brief Timer Complementary Output Compare functions\r
- *\r
-@verbatim\r
- ==============================================================================\r
- ##### Timer Complementary Output Compare functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Start the Complementary Output Compare/PWM.\r
- (+) Stop the Complementary Output Compare/PWM.\r
- (+) Start the Complementary Output Compare/PWM and enable interrupts.\r
- (+) Stop the Complementary Output Compare/PWM and disable interrupts.\r
- (+) Start the Complementary Output Compare/PWM and enable DMA transfers.\r
- (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Starts the TIM Output Compare signal generation on the complementary\r
- * output.\r
- * @param htim : TIM Output Compare handle\r
- * @param Channel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Enable the Capture compare channel N */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
- /* Enable the Main Ouput */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Output Compare signal generation on the complementary\r
- * output.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Disable the Capture compare channel N */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Output Compare signal generation in interrupt mode\r
- * on the complementary output.\r
- * @param htim : TIM OC handle\r
- * @param Channel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Enable the TIM Output Compare interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Enable the TIM Output Compare interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Enable the TIM Output Compare interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Enable the TIM Break interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
-\r
- /* Enable the Capture compare channel N */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
- /* Enable the Main Ouput */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Output Compare signal generation in interrupt mode\r
- * on the complementary output.\r
- * @param htim : TIM Output Compare handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Output Compare interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Output Compare interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Output Compare interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the Capture compare channel N */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
- /* Disable the TIM Break interrupt (only if no more channel is active) */\r
- tmpccer = htim->Instance->CCER;\r
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)\r
- {\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
- }\r
-\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM Output Compare signal generation in DMA mode\r
- * on the complementary output.\r
- * @param htim : TIM Output Compare handle\r
- * @param Channel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @param pData : The source Buffer address.\r
- * @param Length : The length of data to be transferred from memory to TIM peripheral\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if(((uint32_t)pData == 0U) && (Length > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
-\r
- /* Enable the TIM Output Compare DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
-\r
- /* Enable the TIM Output Compare DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
-\r
- /* Enable the TIM Output Compare DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Enable the Capture compare channel N */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
- /* Enable the Main Ouput */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM Output Compare signal generation in DMA mode\r
- * on the complementary output.\r
- * @param htim : TIM Output Compare handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Output Compare DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Output Compare DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Output Compare DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the Capture compare channel N */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the htim state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions\r
- * @brief Timer Complementary PWM functions\r
- *\r
-@verbatim\r
- ==============================================================================\r
- ##### Timer Complementary PWM functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Start the Complementary PWM.\r
- (+) Stop the Complementary PWM.\r
- (+) Start the Complementary PWM and enable interrupts.\r
- (+) Stop the Complementary PWM and disable interrupts.\r
- (+) Start the Complementary PWM and enable DMA transfers.\r
- (+) Stop the Complementary PWM and disable DMA transfers.\r
- (+) Start the Complementary Input Capture measurement.\r
- (+) Stop the Complementary Input Capture.\r
- (+) Start the Complementary Input Capture and enable interrupts.\r
- (+) Stop the Complementary Input Capture and disable interrupts.\r
- (+) Start the Complementary Input Capture and enable DMA transfers.\r
- (+) Stop the Complementary Input Capture and disable DMA transfers.\r
- (+) Start the Complementary One Pulse generation.\r
- (+) Stop the Complementary One Pulse.\r
- (+) Start the Complementary One Pulse and enable interrupts.\r
- (+) Stop the Complementary One Pulse and disable interrupts.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Starts the PWM signal generation on the complementary output.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Enable the complementary PWM output */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
- /* Enable the Main Ouput */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the PWM signal generation on the complementary output.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- /* Disable the complementary PWM output */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the PWM signal generation in interrupt mode on the\r
- * complementary output.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Enable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Enable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Enable the TIM Capture/Compare 3 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Enable the TIM Break interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
-\r
- /* Enable the complementary PWM output */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
- /* Enable the Main Ouput */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the PWM signal generation in interrupt mode on the\r
- * complementary output.\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- uint32_t tmpccer = 0U;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Capture/Compare 3 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the complementary PWM output */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
- /* Disable the TIM Break interrupt (only if no more channel is active) */\r
- tmpccer = htim->Instance->CCER;\r
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)\r
- {\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
- }\r
-\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM PWM signal generation in DMA mode on the\r
- * complementary output\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @param pData : The source Buffer address.\r
- * @param Length : The length of data to be transferred from memory to TIM peripheral\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- if((htim->State == HAL_TIM_STATE_BUSY))\r
- {\r
- return HAL_BUSY;\r
- }\r
- else if((htim->State == HAL_TIM_STATE_READY))\r
- {\r
- if(((uint32_t)pData == 0U) && (Length > 0U))\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- htim->State = HAL_TIM_STATE_BUSY;\r
- }\r
- }\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
-\r
- /* Enable the TIM Capture/Compare 1 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
-\r
- /* Enable the TIM Capture/Compare 2 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Set the DMA Period elapsed callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
-\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
-\r
- /* Enable the DMA channel */\r
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
-\r
- /* Enable the TIM Capture/Compare 3 DMA request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Enable the complementary PWM output */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
-\r
- /* Enable the Main Ouput */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
-\r
- /* Enable the Peripheral */\r
- __HAL_TIM_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM PWM signal generation in DMA mode on the complementary\r
- * output\r
- * @param htim : TIM handle\r
- * @param Channel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
-\r
- switch (Channel)\r
- {\r
- case TIM_CHANNEL_1:\r
- {\r
- /* Disable the TIM Capture/Compare 1 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_2:\r
- {\r
- /* Disable the TIM Capture/Compare 2 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
- }\r
- break;\r
-\r
- case TIM_CHANNEL_3:\r
- {\r
- /* Disable the TIM Capture/Compare 3 DMA request */\r
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- /* Disable the complementary PWM output */\r
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
-\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Change the htim state */\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions\r
- * @brief Timer Complementary One Pulse functions\r
- *\r
-@verbatim\r
- ==============================================================================\r
- ##### Timer Complementary One Pulse functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Start the Complementary One Pulse generation.\r
- (+) Stop the Complementary One Pulse.\r
- (+) Start the Complementary One Pulse and enable interrupts.\r
- (+) Stop the Complementary One Pulse and disable interrupts.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Starts the TIM One Pulse signal generation on the complemetary\r
- * output.\r
- * @param htim : TIM One Pulse handle\r
- * @param OutputChannel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
-\r
- /* Enable the complementary One Pulse output */\r
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
-\r
- /* Enable the Main Ouput */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM One Pulse signal generation on the complementary\r
- * output.\r
- * @param htim : TIM One Pulse handle\r
- * @param OutputChannel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
-\r
- /* Disable the complementary One Pulse output */\r
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
-\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Starts the TIM One Pulse signal generation in interrupt mode on the\r
- * complementary channel.\r
- * @param htim : TIM One Pulse handle\r
- * @param OutputChannel : TIM Channel to be enabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
-\r
- /* Enable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
-\r
- /* Enable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
-\r
- /* Enable the complementary One Pulse output */\r
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
-\r
- /* Enable the Main Ouput */\r
- __HAL_TIM_MOE_ENABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stops the TIM One Pulse signal generation in interrupt mode on the\r
- * complementary channel.\r
- * @param htim : TIM One Pulse handle\r
- * @param OutputChannel : TIM Channel to be disabled\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
-\r
- /* Disable the TIM Capture/Compare 1 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
-\r
- /* Disable the TIM Capture/Compare 2 interrupt */\r
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
-\r
- /* Disable the complementary One Pulse output */\r
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
-\r
- /* Disable the Main Ouput */\r
- __HAL_TIM_MOE_DISABLE(htim);\r
-\r
- /* Disable the Peripheral */\r
- __HAL_TIM_DISABLE(htim);\r
-\r
- /* Return function status */\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions\r
- * @brief Peripheral Control functions\r
- *\r
-@verbatim\r
- ==============================================================================\r
- ##### Peripheral Control functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides functions allowing to:\r
- (+) Configure the commutation event in case of use of the Hall sensor interface.\r
- (+) Configure Complementary channels, break features and dead time.\r
- (+) Configure Master synchronization.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-\r
-/**\r
- * @brief Configure the TIM commutation event sequence.\r
- * @note: this function is mandatory to use the commutation event in order to\r
- * update the configuration at each commutation detection on the TRGI input of the Timer,\r
- * the typical use of this feature is with the use of another Timer(interface Timer)\r
- * configured in Hall sensor interface, this interface Timer will generate the\r
- * commutation at its TRGO output (connected to Timer used in this function) each time\r
- * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
- * @param htim : TIM handle\r
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
- * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
- * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
- * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
- * @arg TIM_TS_NONE: No trigger is needed\r
- * @param CommutationSource : the Commutation Event source\r
- * This parameter can be one of the following values:\r
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
-\r
- __HAL_LOCK(htim);\r
-\r
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
- {\r
- /* Select the Input trigger */\r
- htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
- htim->Instance->SMCR |= InputTrigger;\r
- }\r
-\r
- /* Select the Capture Compare preload feature */\r
- htim->Instance->CR2 |= TIM_CR2_CCPC;\r
- /* Select the Commutation event source */\r
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
- htim->Instance->CR2 |= CommutationSource;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Configure the TIM commutation event sequence with interrupt.\r
- * @note: this function is mandatory to use the commutation event in order to\r
- * update the configuration at each commutation detection on the TRGI input of the Timer,\r
- * the typical use of this feature is with the use of another Timer(interface Timer)\r
- * configured in Hall sensor interface, this interface Timer will generate the\r
- * commutation at its TRGO output (connected to Timer used in this function) each time\r
- * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
- * @param htim : TIM handle\r
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
- * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
- * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
- * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
- * @arg TIM_TS_NONE: No trigger is needed\r
- * @param CommutationSource : the Commutation Event source\r
- * This parameter can be one of the following values:\r
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
-\r
- __HAL_LOCK(htim);\r
-\r
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
- {\r
- /* Select the Input trigger */\r
- htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
- htim->Instance->SMCR |= InputTrigger;\r
- }\r
-\r
- /* Select the Capture Compare preload feature */\r
- htim->Instance->CR2 |= TIM_CR2_CCPC;\r
- /* Select the Commutation event source */\r
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
- htim->Instance->CR2 |= CommutationSource;\r
-\r
- /* Enable the Commutation Interrupt Request */\r
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Configure the TIM commutation event sequence with DMA.\r
- * @note: this function is mandatory to use the commutation event in order to\r
- * update the configuration at each commutation detection on the TRGI input of the Timer,\r
- * the typical use of this feature is with the use of another Timer(interface Timer)\r
- * configured in Hall sensor interface, this interface Timer will generate the\r
- * commutation at its TRGO output (connected to Timer used in this function) each time\r
- * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
- * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set\r
- * @param htim : TIM handle\r
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
- * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
- * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
- * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
- * @arg TIM_TS_NONE: No trigger is needed\r
- * @param CommutationSource : the Commutation Event source\r
- * This parameter can be one of the following values:\r
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
-\r
- __HAL_LOCK(htim);\r
-\r
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
- {\r
- /* Select the Input trigger */\r
- htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
- htim->Instance->SMCR |= InputTrigger;\r
- }\r
-\r
- /* Select the Capture Compare preload feature */\r
- htim->Instance->CR2 |= TIM_CR2_CCPC;\r
- /* Select the Commutation event source */\r
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
- htim->Instance->CR2 |= CommutationSource;\r
-\r
- /* Enable the Commutation DMA Request */\r
- /* Set the DMA Commutation Callback */\r
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
- /* Set the DMA error callback */\r
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;\r
-\r
- /* Enable the Commutation DMA Request */\r
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State\r
- * and the AOE(automatic output enable).\r
- * @param htim : TIM handle\r
- * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that\r
- * contains the BDTR Register configuration information for the TIM peripheral.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\r
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)\r
-{\r
- uint32_t tmpbdtr = 0U;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));\r
- assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));\r
- assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));\r
- assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));\r
- assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));\r
- assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));\r
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(htim);\r
-\r
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\r
- the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
-\r
- /* Set the BDTR bits */\r
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);\r
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);\r
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);\r
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);\r
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);\r
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);\r
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);\r
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);\r
-\r
- /* Set TIMx_BDTR */\r
- htim->Instance->BDTR = tmpbdtr;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-\r
-/**\r
- * @brief Configures the TIM in master mode.\r
- * @param htim : TIM handle.\r
- * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that\r
- * contains the selected trigger output (TRGO) and the Master/Slave\r
- * mode.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));\r
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\r
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\r
-\r
- __HAL_LOCK(htim);\r
-\r
- htim->State = HAL_TIM_STATE_BUSY;\r
-\r
- /* Reset the MMS Bits */\r
- htim->Instance->CR2 &= ~TIM_CR2_MMS;\r
- /* Select the TRGO source */\r
- htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;\r
-\r
- /* Reset the MSM Bit */\r
- htim->Instance->SMCR &= ~TIM_SMCR_MSM;\r
- /* Set or Reset the MSM Bit */\r
- htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;\r
-\r
- htim->State = HAL_TIM_STATE_READY;\r
-\r
- __HAL_UNLOCK(htim);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions\r
- * @brief Extension Callbacks functions\r
- *\r
-@verbatim\r
- ==============================================================================\r
- ##### Extension Callbacks functions #####\r
- ==============================================================================\r
- [..]\r
- This section provides Extension TIM callback functions:\r
- (+) Timer Commutation callback\r
- (+) Timer Break callback\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Hall commutation changed callback in non blocking mode\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIMEx_CommutationCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Hall Break detection callback in non blocking mode\r
- * @param htim : TIM handle\r
- * @retval None\r
- */\r
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(htim);\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_TIMEx_BreakCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief TIM DMA Commutation callback.\r
- * @param hdma : pointer to DMA handle.\r
- * @retval None\r
- */\r
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
-\r
- htim->State= HAL_TIM_STATE_READY;\r
-\r
- HAL_TIMEx_CommutationCallback(htim);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-\r
-/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions\r
- * @brief Extension Peripheral State functions\r
- *\r
-@verbatim\r
- ==============================================================================\r
- ##### Extension Peripheral State functions #####\r
- ==============================================================================\r
- [..]\r
- This subsection permit to get in run-time the status of the peripheral\r
- and the data flow.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Return the TIM Hall Sensor interface state\r
- * @param htim : TIM Hall Sensor handle\r
- * @retval HAL state\r
- */\r
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)\r
-{\r
- return htim->State;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined (STM32F100xB) || defined (STM32F100xE) || \\r
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \\r
- defined (STM32F105xC) || defined (STM32F107xC)\r
-\r
-/** @addtogroup TIMEx_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the TIM Capture Compare Channel xN.\r
- * @param TIMx to select the TIM peripheral\r
- * @param Channel : specifies the TIM Channel\r
- * This parameter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @param ChannelNState : specifies the TIM Channel CCxNE bit new state.\r
- * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.\r
- * @retval None\r
- */\r
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)\r
-{\r
- uint32_t tmp = 0U;\r
-\r
- tmp = TIM_CCER_CC1NE << Channel;\r
-\r
- /* Reset the CCxNE Bit */\r
- TIMx->CCER &= ~tmp;\r
-\r
- /* Set or reset the CCxNE Bit */\r
- TIMx->CCER |= (uint32_t)(ChannelNState << Channel);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */\r
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */\r
- /* defined(STM32F105xC) || defined(STM32F107xC) */\r
-\r
-#endif /* HAL_TIM_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-# This is an genericBoard board with a single STM32F103RETx chip
-#
-# Generated by STM32CubeIDE
-# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
-
-source [find interface/stlink-tcp.cfg]
-
-set WORKAREASIZE 0x8000
-
-transport select "hla_swd"
-
-set CHIPNAME STM32F103RETx
-set BOARDNAME genericBoard
-
-# Enable debug when in low power modes
-set ENABLE_LOW_POWER 1
-
-# Stop Watchdog counters when halt
-set STOP_WATCHDOG 1
-
-# STlink Debug clock frequency
-set CLOCK_FREQ 4000
-
-# use software system reset
-reset_config none
-set CONNECT_UNDER_RESET 0
-
-# BCTM CPU variables
-
-source [find target/stm32f1x.cfg]
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
-<intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_div" value="8"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_DEVICE_SHAREABLE_ALLOWED" value="true"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_INTERFACE" value="Swd"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_INTERFACE_FREQUENCY" value="4000000.0"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_LOW_POWER_MODE_ALLOWED" value="true"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_RESET_MODE" value="soft"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_STOP_WATCHDOG_THEN_HALTED_ALLOWED" value="true"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_GENERATOR_OPTION" value="true"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_NAME" value=""${stm32cubeide_openocd_path}/openocd""/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_OTHER_OPTIONS" value=""/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_SCRIPT" value="${ProjDirPath}/F103RE.elf.cfg"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_SCRIPT_CHOICE" value="automated"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.ST-LINK" value="48FF72066767555730381267"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_external_loader" value="false"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader" value=""/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="/Users/ace/workspace/acecode/learn/stm32/F103RE/Debug/st-link_gdbserver_log.txt"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_ap_id" value="0"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
-<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="ST-LINK (OpenOCD)"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-none-eabi-gdb"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
-<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/F103RE.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="F103RE"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/F103RE"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
+++ /dev/null
-#MicroXplorer Configuration settings - do not modify
-File.Version=6
-KeepUserPlacement=false
-Mcu.Family=STM32F1
-Mcu.IP0=NVIC
-Mcu.IP1=RCC
-Mcu.IP2=SYS
-Mcu.IPNb=3
-Mcu.Name=STM32F103R(C-D-E)Tx
-Mcu.Package=LQFP64
-Mcu.Pin0=PD0-OSC_IN
-Mcu.Pin1=PD1-OSC_OUT
-Mcu.Pin2=PC0
-Mcu.Pin3=PA4
-Mcu.Pin4=PA5
-Mcu.Pin5=PA6
-Mcu.Pin6=PA7
-Mcu.Pin7=PA13
-Mcu.Pin8=PA14
-Mcu.Pin9=VP_SYS_VS_Systick
-Mcu.PinsNb=10
-Mcu.ThirdPartyNb=0
-Mcu.UserConstants=
-Mcu.UserName=STM32F103RETx
-MxCube.Version=5.2.0
-MxDb.Version=DB.5.0.20
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.EXTI0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.MemoryManagement_IRQn=true\:0\:0\:true\:false\:true\:false\:false
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.PriorityGroup=NVIC_PRIORITYGROUP_2
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-PA13.Mode=Serial_Wire
-PA13.Signal=SYS_JTMS-SWDIO
-PA14.Mode=Serial_Wire
-PA14.Signal=SYS_JTCK-SWCLK
-PA4.GPIOParameters=GPIO_Speed,GPIO_Label
-PA4.GPIO_Label=LED1
-PA4.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
-PA4.Locked=true
-PA4.Signal=GPIO_Output
-PA5.GPIOParameters=GPIO_Speed,GPIO_Label,GPIO_ModeDefaultOutputPP
-PA5.GPIO_Label=LED2
-PA5.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
-PA5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
-PA5.Locked=true
-PA5.Signal=GPIO_Output
-PA6.GPIOParameters=GPIO_Speed,GPIO_Label
-PA6.GPIO_Label=LED3
-PA6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
-PA6.Locked=true
-PA6.Signal=GPIO_Output
-PA7.GPIOParameters=GPIO_Speed,GPIO_Label,GPIO_ModeDefaultOutputPP
-PA7.GPIO_Label=LED4
-PA7.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
-PA7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
-PA7.Locked=true
-PA7.Signal=GPIO_Output
-PC0.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
-PC0.GPIO_Label=KEY1
-PC0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
-PC0.Locked=true
-PC0.Signal=GPXTI0
-PCC.Checker=false
-PCC.Line=STM32F103
-PCC.MCU=STM32F103R(C-D-E)Tx
-PCC.PartNumber=STM32F103RETx
-PCC.Seq0=0
-PCC.Series=STM32F1
-PCC.Temperature=25
-PCC.Vdd=3.3
-PD0-OSC_IN.Mode=HSE-External-Oscillator
-PD0-OSC_IN.Signal=RCC_OSC_IN
-PD1-OSC_OUT.Mode=HSE-External-Oscillator
-PD1-OSC_OUT.Signal=RCC_OSC_OUT
-PinOutPanel.RotationAngle=0
-ProjectManager.AskForMigrate=true
-ProjectManager.BackupPrevious=false
-ProjectManager.CompilerOptimize=6
-ProjectManager.ComputerToolchain=false
-ProjectManager.CoupleFile=true
-ProjectManager.CustomerFirmwarePackage=
-ProjectManager.DefaultFWLocation=true
-ProjectManager.DeletePrevious=true
-ProjectManager.DeviceId=STM32F103RETx
-ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.7.0
-ProjectManager.FreePins=false
-ProjectManager.HalAssertFull=false
-ProjectManager.HeapSize=0x200
-ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=true
-ProjectManager.LibraryCopy=1
-ProjectManager.MainLocation=Src
-ProjectManager.NoMain=false
-ProjectManager.PreviousToolchain=
-ProjectManager.ProjectBuild=false
-ProjectManager.ProjectFileName=F103RE.ioc
-ProjectManager.ProjectName=F103RE
-ProjectManager.StackSize=0x400
-ProjectManager.TargetToolchain=STM32CubeIDE
-ProjectManager.ToolChainLocation=
-ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false
-RCC.ADCFreqValue=36000000
-RCC.AHBFreq_Value=72000000
-RCC.APB1CLKDivider=RCC_HCLK_DIV2
-RCC.APB1Freq_Value=36000000
-RCC.APB1TimFreq_Value=72000000
-RCC.APB2Freq_Value=72000000
-RCC.APB2TimFreq_Value=72000000
-RCC.FCLKCortexFreq_Value=72000000
-RCC.FamilyName=M
-RCC.HCLKFreq_Value=72000000
-RCC.HSE_VALUE=12000000
-RCC.I2S2Freq_Value=72000000
-RCC.I2S3Freq_Value=72000000
-RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
-RCC.MCOFreq_Value=72000000
-RCC.PLLCLKFreq_Value=72000000
-RCC.PLLMCOFreq_Value=36000000
-RCC.PLLMUL=RCC_PLL_MUL6
-RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
-RCC.SDIOFreq_Value=72000000
-RCC.SDIOHCLKDiv2FreqValue=36000000
-RCC.SYSCLKFreq_VALUE=72000000
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.TimSysFreq_Value=72000000
-RCC.USBFreq_Value=72000000
-RCC.VCOOutput2Freq_Value=12000000
-SH.GPXTI0.0=GPIO_EXTI0
-SH.GPXTI0.ConfNb=1
-VP_SYS_VS_Systick.Mode=SysTick
-VP_SYS_VS_Systick.Signal=SYS_VS_Systick
-board=custom
-isbadioc=false
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * File Name : gpio.h\r
- * Description : This file contains all the functions prototypes for \r
- * the gpio \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __gpio_H\r
-#define __gpio_H\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "main.h"\r
-\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* USER CODE BEGIN Private defines */\r
-\r
-/* USER CODE END Private defines */\r
-\r
-void MX_GPIO_Init(void);\r
-\r
-/* USER CODE BEGIN Prototypes */\r
-\r
-/* USER CODE END Prototypes */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /*__ pinoutConfig_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/* USER CODE BEGIN Header */\r
-/**\r
- ******************************************************************************\r
- * @file : main.h\r
- * @brief : Header for main.c file.\r
- * This file contains the common defines of the application.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-/* USER CODE END Header */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __MAIN_H\r
-#define __MAIN_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f1xx_hal.h"\r
-\r
-/* Private includes ----------------------------------------------------------*/\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* USER CODE BEGIN ET */\r
-\r
-/* USER CODE END ET */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/* USER CODE BEGIN EC */\r
-\r
-/* USER CODE END EC */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* USER CODE BEGIN EM */\r
-\r
-/* USER CODE END EM */\r
-\r
-/* Exported functions prototypes ---------------------------------------------*/\r
-void Error_Handler(void);\r
-\r
-/* USER CODE BEGIN EFP */\r
-\r
-/* USER CODE END EFP */\r
-\r
-/* Private defines -----------------------------------------------------------*/\r
-#define KEY1_Pin GPIO_PIN_0\r
-#define KEY1_GPIO_Port GPIOC\r
-#define KEY1_EXTI_IRQn EXTI0_IRQn\r
-#define LED1_Pin GPIO_PIN_4\r
-#define LED1_GPIO_Port GPIOA\r
-#define LED2_Pin GPIO_PIN_5\r
-#define LED2_GPIO_Port GPIOA\r
-#define LED3_Pin GPIO_PIN_6\r
-#define LED3_GPIO_Port GPIOA\r
-#define LED4_Pin GPIO_PIN_7\r
-#define LED4_GPIO_Port GPIOA\r
-/* USER CODE BEGIN Private defines */\r
-\r
-/* USER CODE END Private defines */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __MAIN_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_hal_conf.h\r
- * @brief HAL configuration file.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_HAL_CONF_H\r
-#define __STM32F1xx_HAL_CONF_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/* ########################## Module Selection ############################## */\r
-/**\r
- * @brief This is the list of modules to be used in the HAL driver \r
- */\r
- \r
-#define HAL_MODULE_ENABLED \r
-/*#define HAL_ADC_MODULE_ENABLED */\r
-/*#define HAL_CRYP_MODULE_ENABLED */\r
-/*#define HAL_CAN_MODULE_ENABLED */\r
-/*#define HAL_CEC_MODULE_ENABLED */\r
-/*#define HAL_CORTEX_MODULE_ENABLED */\r
-/*#define HAL_CRC_MODULE_ENABLED */\r
-/*#define HAL_DAC_MODULE_ENABLED */\r
-/*#define HAL_DMA_MODULE_ENABLED */\r
-/*#define HAL_ETH_MODULE_ENABLED */\r
-/*#define HAL_FLASH_MODULE_ENABLED */\r
-#define HAL_GPIO_MODULE_ENABLED\r
-/*#define HAL_I2C_MODULE_ENABLED */\r
-/*#define HAL_I2S_MODULE_ENABLED */\r
-/*#define HAL_IRDA_MODULE_ENABLED */\r
-/*#define HAL_IWDG_MODULE_ENABLED */\r
-/*#define HAL_NOR_MODULE_ENABLED */\r
-/*#define HAL_NAND_MODULE_ENABLED */\r
-/*#define HAL_PCCARD_MODULE_ENABLED */\r
-/*#define HAL_PCD_MODULE_ENABLED */\r
-/*#define HAL_HCD_MODULE_ENABLED */\r
-/*#define HAL_PWR_MODULE_ENABLED */\r
-/*#define HAL_RCC_MODULE_ENABLED */\r
-/*#define HAL_RTC_MODULE_ENABLED */\r
-/*#define HAL_SD_MODULE_ENABLED */\r
-/*#define HAL_MMC_MODULE_ENABLED */\r
-/*#define HAL_SDRAM_MODULE_ENABLED */\r
-/*#define HAL_SMARTCARD_MODULE_ENABLED */\r
-/*#define HAL_SPI_MODULE_ENABLED */\r
-/*#define HAL_SRAM_MODULE_ENABLED */\r
-/*#define HAL_TIM_MODULE_ENABLED */\r
-/*#define HAL_UART_MODULE_ENABLED */\r
-/*#define HAL_USART_MODULE_ENABLED */\r
-/*#define HAL_WWDG_MODULE_ENABLED */\r
-/*#define HAL_EXTI_MODULE_ENABLED */\r
-\r
-#define HAL_CORTEX_MODULE_ENABLED\r
-#define HAL_DMA_MODULE_ENABLED\r
-#define HAL_FLASH_MODULE_ENABLED\r
-#define HAL_GPIO_MODULE_ENABLED\r
-#define HAL_PWR_MODULE_ENABLED\r
-#define HAL_RCC_MODULE_ENABLED\r
-\r
-/* ########################## Oscillator Values adaptation ####################*/\r
-/**\r
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r
- * This value is used by the RCC HAL module to compute the system frequency\r
- * (when HSE is used as system clock source, directly or through the PLL). \r
- */\r
-#if !defined (HSE_VALUE) \r
- #define HSE_VALUE ((uint32_t)12000000) /*!< Value of the External oscillator in Hz */\r
-#endif /* HSE_VALUE */\r
-\r
-#if !defined (HSE_STARTUP_TIMEOUT)\r
- #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */\r
-#endif /* HSE_STARTUP_TIMEOUT */\r
-\r
-/**\r
- * @brief Internal High Speed oscillator (HSI) value.\r
- * This value is used by the RCC HAL module to compute the system frequency\r
- * (when HSI is used as system clock source, directly or through the PLL). \r
- */\r
-#if !defined (HSI_VALUE)\r
- #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/\r
-#endif /* HSI_VALUE */\r
-\r
-/**\r
- * @brief Internal Low Speed oscillator (LSI) value.\r
- */\r
-#if !defined (LSI_VALUE) \r
- #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */\r
-#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz\r
- The real value may vary depending on the variations\r
- in voltage and temperature. */\r
-\r
-/**\r
- * @brief External Low Speed oscillator (LSE) value.\r
- * This value is used by the UART, RTC HAL module to compute the system frequency\r
- */\r
-#if !defined (LSE_VALUE)\r
- #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/\r
-#endif /* LSE_VALUE */\r
-\r
-#if !defined (LSE_STARTUP_TIMEOUT)\r
- #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */\r
-#endif /* LSE_STARTUP_TIMEOUT */\r
-\r
-/* Tip: To avoid modifying this file each time you need to use different HSE,\r
- === you can define the HSE value in your toolchain compiler preprocessor. */\r
-\r
-/* ########################### System Configuration ######################### */\r
-/**\r
- * @brief This is the HAL system configuration section\r
- */ \r
-#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ \r
-#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ \r
-#define USE_RTOS 0\r
-#define PREFETCH_ENABLE 1\r
-\r
-/* ########################## Assert Selection ############################## */\r
-/**\r
- * @brief Uncomment the line below to expanse the "assert_param" macro in the \r
- * HAL drivers code\r
- */\r
-/* #define USE_FULL_ASSERT 1U */\r
-\r
-/* ################## Ethernet peripheral configuration ##################### */\r
-\r
-/* Section 1 : Ethernet peripheral configuration */\r
-\r
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\r
-#define MAC_ADDR0 2\r
-#define MAC_ADDR1 0\r
-#define MAC_ADDR2 0\r
-#define MAC_ADDR3 0\r
-#define MAC_ADDR4 0\r
-#define MAC_ADDR5 0\r
-\r
-/* Definition of the Ethernet driver buffers size and count */ \r
-#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */\r
-#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */\r
-#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */\r
-#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */\r
-\r
-/* Section 2: PHY configuration section */\r
-\r
-/* DP83848_PHY_ADDRESS Address*/ \r
-#define DP83848_PHY_ADDRESS 0x01U\r
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ \r
-#define PHY_RESET_DELAY ((uint32_t)0x000000FF)\r
-/* PHY Configuration delay */\r
-#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)\r
-\r
-#define PHY_READ_TO ((uint32_t)0x0000FFFF)\r
-#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)\r
-\r
-/* Section 3: Common PHY Registers */\r
-\r
-#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */\r
-#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */\r
- \r
-#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */\r
-#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */\r
-#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */\r
-#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */\r
-#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */\r
-#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */\r
-#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */\r
-#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */\r
-#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */\r
-#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */\r
-\r
-#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */\r
-#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */\r
-#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */\r
- \r
-/* Section 4: Extended PHY Registers */\r
-#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */\r
-\r
-#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */\r
-#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-/**\r
- * @brief Include module's header file \r
- */\r
-\r
-#ifdef HAL_RCC_MODULE_ENABLED\r
- #include "stm32f1xx_hal_rcc.h"\r
-#endif /* HAL_RCC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_EXTI_MODULE_ENABLED\r
- #include "stm32f1xx_hal_exti.h"\r
-#endif /* HAL_EXTI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_GPIO_MODULE_ENABLED\r
- #include "stm32f1xx_hal_gpio.h"\r
-#endif /* HAL_GPIO_MODULE_ENABLED */\r
- \r
-#ifdef HAL_DMA_MODULE_ENABLED\r
- #include "stm32f1xx_hal_dma.h"\r
-#endif /* HAL_DMA_MODULE_ENABLED */\r
- \r
-#ifdef HAL_ETH_MODULE_ENABLED\r
- #include "stm32f1xx_hal_eth.h"\r
-#endif /* HAL_ETH_MODULE_ENABLED */ \r
- \r
-#ifdef HAL_CAN_MODULE_ENABLED\r
- #include "stm32f1xx_hal_can.h"\r
-#endif /* HAL_CAN_MODULE_ENABLED */\r
-\r
-#ifdef HAL_CEC_MODULE_ENABLED\r
- #include "stm32f1xx_hal_cec.h"\r
-#endif /* HAL_CEC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_CORTEX_MODULE_ENABLED\r
- #include "stm32f1xx_hal_cortex.h"\r
-#endif /* HAL_CORTEX_MODULE_ENABLED */\r
-\r
-#ifdef HAL_ADC_MODULE_ENABLED\r
- #include "stm32f1xx_hal_adc.h"\r
-#endif /* HAL_ADC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_CRC_MODULE_ENABLED\r
- #include "stm32f1xx_hal_crc.h"\r
-#endif /* HAL_CRC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_DAC_MODULE_ENABLED\r
- #include "stm32f1xx_hal_dac.h"\r
-#endif /* HAL_DAC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_FLASH_MODULE_ENABLED\r
- #include "stm32f1xx_hal_flash.h"\r
-#endif /* HAL_FLASH_MODULE_ENABLED */\r
-\r
-#ifdef HAL_SRAM_MODULE_ENABLED\r
- #include "stm32f1xx_hal_sram.h"\r
-#endif /* HAL_SRAM_MODULE_ENABLED */\r
-\r
-#ifdef HAL_NOR_MODULE_ENABLED\r
- #include "stm32f1xx_hal_nor.h"\r
-#endif /* HAL_NOR_MODULE_ENABLED */\r
-\r
-#ifdef HAL_I2C_MODULE_ENABLED\r
- #include "stm32f1xx_hal_i2c.h"\r
-#endif /* HAL_I2C_MODULE_ENABLED */\r
-\r
-#ifdef HAL_I2S_MODULE_ENABLED\r
- #include "stm32f1xx_hal_i2s.h"\r
-#endif /* HAL_I2S_MODULE_ENABLED */\r
-\r
-#ifdef HAL_IWDG_MODULE_ENABLED\r
- #include "stm32f1xx_hal_iwdg.h"\r
-#endif /* HAL_IWDG_MODULE_ENABLED */\r
-\r
-#ifdef HAL_PWR_MODULE_ENABLED\r
- #include "stm32f1xx_hal_pwr.h"\r
-#endif /* HAL_PWR_MODULE_ENABLED */\r
-\r
-#ifdef HAL_RTC_MODULE_ENABLED\r
- #include "stm32f1xx_hal_rtc.h"\r
-#endif /* HAL_RTC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_PCCARD_MODULE_ENABLED\r
- #include "stm32f1xx_hal_pccard.h"\r
-#endif /* HAL_PCCARD_MODULE_ENABLED */ \r
-\r
-#ifdef HAL_SD_MODULE_ENABLED\r
- #include "stm32f1xx_hal_sd.h"\r
-#endif /* HAL_SD_MODULE_ENABLED */ \r
-\r
-#ifdef HAL_MMC_MODULE_ENABLED\r
- #include "stm32f1xx_hal_mmc.h"\r
-#endif /* HAL_MMC_MODULE_ENABLED */\r
-\r
-#ifdef HAL_NAND_MODULE_ENABLED\r
- #include "stm32f1xx_hal_nand.h"\r
-#endif /* HAL_NAND_MODULE_ENABLED */ \r
-\r
-#ifdef HAL_SPI_MODULE_ENABLED\r
- #include "stm32f1xx_hal_spi.h"\r
-#endif /* HAL_SPI_MODULE_ENABLED */\r
-\r
-#ifdef HAL_TIM_MODULE_ENABLED\r
- #include "stm32f1xx_hal_tim.h"\r
-#endif /* HAL_TIM_MODULE_ENABLED */\r
-\r
-#ifdef HAL_UART_MODULE_ENABLED\r
- #include "stm32f1xx_hal_uart.h"\r
-#endif /* HAL_UART_MODULE_ENABLED */\r
-\r
-#ifdef HAL_USART_MODULE_ENABLED\r
- #include "stm32f1xx_hal_usart.h"\r
-#endif /* HAL_USART_MODULE_ENABLED */\r
-\r
-#ifdef HAL_IRDA_MODULE_ENABLED\r
- #include "stm32f1xx_hal_irda.h"\r
-#endif /* HAL_IRDA_MODULE_ENABLED */\r
-\r
-#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
- #include "stm32f1xx_hal_smartcard.h"\r
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
-\r
-#ifdef HAL_WWDG_MODULE_ENABLED\r
- #include "stm32f1xx_hal_wwdg.h"\r
-#endif /* HAL_WWDG_MODULE_ENABLED */\r
-\r
-#ifdef HAL_PCD_MODULE_ENABLED\r
- #include "stm32f1xx_hal_pcd.h"\r
-#endif /* HAL_PCD_MODULE_ENABLED */\r
-\r
-#ifdef HAL_HCD_MODULE_ENABLED\r
- #include "stm32f1xx_hal_hcd.h"\r
-#endif /* HAL_HCD_MODULE_ENABLED */ \r
- \r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-#ifdef USE_FULL_ASSERT\r
-/**\r
- * @brief The assert_param macro is used for function's parameters check.\r
- * @param expr: If expr is false, it calls assert_failed function\r
- * which reports the name of the source file and the source\r
- * line number of the call that failed. \r
- * If expr is true, it returns no value.\r
- * @retval None\r
- */\r
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\r
-/* Exported functions ------------------------------------------------------- */\r
- void assert_failed(uint8_t* file, uint32_t line);\r
-#else\r
- #define assert_param(expr) ((void)0U)\r
-#endif /* USE_FULL_ASSERT */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_HAL_CONF_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/* USER CODE BEGIN Header */\r
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_it.h\r
- * @brief This file contains the headers of the interrupt handlers.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-/* USER CODE END Header */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F1xx_IT_H\r
-#define __STM32F1xx_IT_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/* Private includes ----------------------------------------------------------*/\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* USER CODE BEGIN ET */\r
-\r
-/* USER CODE END ET */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/* USER CODE BEGIN EC */\r
-\r
-/* USER CODE END EC */\r
-\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* USER CODE BEGIN EM */\r
-\r
-/* USER CODE END EM */\r
-\r
-/* Exported functions prototypes ---------------------------------------------*/\r
-void NMI_Handler(void);\r
-void HardFault_Handler(void);\r
-void MemManage_Handler(void);\r
-void BusFault_Handler(void);\r
-void UsageFault_Handler(void);\r
-void SVC_Handler(void);\r
-void DebugMon_Handler(void);\r
-void PendSV_Handler(void);\r
-void SysTick_Handler(void);\r
-void EXTI0_IRQHandler(void);\r
-/* USER CODE BEGIN EFP */\r
-\r
-/* USER CODE END EFP */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F1xx_IT_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/*
-******************************************************************************
-**
-** File : LinkerScript.ld
-**
-** Author : Auto-generated by STM32CubeIDE
-**
-** Abstract : Linker script for STM32F103RETx Device from STM32F1 series
-** 512Kbytes FLASH
-** 64Kbytes RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Set memory bank area and size if external memory is used.
-**
-** Target : STMicroelectronics STM32
-**
-** Distribution: The file is distributed as is without any warranty
-** of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-** 1. Redistributions of source code must retain the above copyright notice,
-** this list of conditions and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright notice,
-** this list of conditions and the following disclaimer in the documentation
-** and/or other materials provided with the distribution.
-** 3. Neither the name of STMicroelectronics nor the names of its contributors
-** may be used to endorse or promote products derived from this software
-** without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x2000ffff; /* end of "RAM" Ram type memory */
-
-_Min_Heap_Size = 0x200 ; /* required amount of heap */
-_Min_Stack_Size = 0x400 ; /* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
-}
-
-/* Sections */
-SECTIONS
-{
- /* The startup code into "FLASH" Rom type memory */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* The program code and other data into "FLASH" Rom type memory */
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
-
- KEEP (*(.init))
- KEEP (*(.fini))
-
- . = ALIGN(4);
- _etext = .; /* define a global symbols at end of code */
- } >FLASH
-
- /* Constant data into "FLASH" Rom type memory */
- .rodata :
- {
- . = ALIGN(4);
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- . = ALIGN(4);
- } >FLASH
-
- .ARM.extab : {
- . = ALIGN(4);
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- . = ALIGN(4);
- } >FLASH
-
- .ARM : {
- . = ALIGN(4);
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- . = ALIGN(4);
- } >FLASH
-
- .preinit_array :
- {
- . = ALIGN(4);
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
- } >FLASH
-
- .init_array :
- {
- . = ALIGN(4);
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
- } >FLASH
-
- .fini_array :
- {
- . = ALIGN(4);
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array*))
- PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
- } >FLASH
-
- /* Used by the startup to initialize data */
- _sidata = LOADADDR(.data);
-
- /* Initialized data sections into "RAM" Ram type memory */
- .data :
- {
- . = ALIGN(4);
- _sdata = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
-
- . = ALIGN(4);
- _edata = .; /* define a global symbol at data end */
-
- } >RAM AT> FLASH
-
- /* Uninitialized data section into "RAM" Ram type memory */
- . = ALIGN(4);
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .; /* define a global symbol at bss start */
- __bss_start__ = _sbss;
- *(.bss)
- *(.bss*)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = .; /* define a global symbol at bss end */
- __bss_end__ = _ebss;
- } >RAM
-
- /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
- ._user_heap_stack :
- {
- . = ALIGN(8);
- PROVIDE ( end = . );
- PROVIDE ( _end = . );
- . = . + _Min_Heap_Size;
- . = . + _Min_Stack_Size;
- . = ALIGN(8);
- } >RAM
-
- /* Remove information from the compiler libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- .ARM.attributes 0 : { *(.ARM.attributes) }
-}
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * File Name : gpio.c\r
- * Description : This file provides code for the configuration\r
- * of all used GPIO pins.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "gpio.h"\r
-/* USER CODE BEGIN 0 */\r
-\r
-/* USER CODE END 0 */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Configure GPIO */\r
-/*----------------------------------------------------------------------------*/\r
-/* USER CODE BEGIN 1 */\r
-\r
-/* USER CODE END 1 */\r
-\r
-/** Configure pins as \r
- * Analog \r
- * Input \r
- * Output\r
- * EVENT_OUT\r
- * EXTI\r
-*/\r
-void MX_GPIO_Init(void)\r
-{\r
-\r
- GPIO_InitTypeDef GPIO_InitStruct = {0};\r
-\r
- /* GPIO Ports Clock Enable */\r
- __HAL_RCC_GPIOD_CLK_ENABLE();\r
- __HAL_RCC_GPIOC_CLK_ENABLE();\r
- __HAL_RCC_GPIOA_CLK_ENABLE();\r
-\r
- /*Configure GPIO pin Output Level */\r
- HAL_GPIO_WritePin(GPIOA, LED1_Pin|LED2_Pin|LED3_Pin|LED4_Pin, GPIO_PIN_RESET);\r
-\r
- /*Configure GPIO pin : PtPin */\r
- GPIO_InitStruct.Pin = KEY1_Pin;\r
- GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;\r
- GPIO_InitStruct.Pull = GPIO_NOPULL;\r
- HAL_GPIO_Init(KEY1_GPIO_Port, &GPIO_InitStruct);\r
-\r
- /*Configure GPIO pins : PAPin PAPin PAPin PAPin */\r
- GPIO_InitStruct.Pin = LED1_Pin|LED2_Pin|LED3_Pin|LED4_Pin;\r
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
- GPIO_InitStruct.Pull = GPIO_NOPULL;\r
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\r
- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
-\r
- /* EXTI interrupt init*/\r
- HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0);\r
- HAL_NVIC_EnableIRQ(EXTI0_IRQn);\r
-\r
-}\r
-\r
-/* USER CODE BEGIN 2 */\r
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {\r
- HAL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin);\r
-}\r
-/* USER CODE END 2 */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/* USER CODE BEGIN Header */\r
-/**\r
- ******************************************************************************\r
- * @file : main.c\r
- * @brief : Main program body\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-/* USER CODE END Header */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "main.h"\r
-#include "gpio.h"\r
-\r
-/* Private includes ----------------------------------------------------------*/\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* USER CODE BEGIN PTD */\r
-\r
-/* USER CODE END PTD */\r
-\r
-/* Private define ------------------------------------------------------------*/\r
-/* USER CODE BEGIN PD */\r
-\r
-/* USER CODE END PD */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* USER CODE BEGIN PM */\r
-\r
-/* USER CODE END PM */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-\r
-/* USER CODE BEGIN PV */\r
-\r
-/* USER CODE END PV */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-void SystemClock_Config(void);\r
-/* USER CODE BEGIN PFP */\r
-\r
-/* USER CODE END PFP */\r
-\r
-/* Private user code ---------------------------------------------------------*/\r
-/* USER CODE BEGIN 0 */\r
-\r
-/* USER CODE END 0 */\r
-\r
-/**\r
- * @brief The application entry point.\r
- * @retval int\r
- */\r
-int main(void)\r
-{\r
- /* USER CODE BEGIN 1 */\r
-\r
- /* USER CODE END 1 */\r
- \r
-\r
- /* MCU Configuration--------------------------------------------------------*/\r
-\r
- /* Reset of all peripherals, Initializes the Flash interface and the Systick. */\r
- HAL_Init();\r
-\r
- /* USER CODE BEGIN Init */\r
-\r
- /* USER CODE END Init */\r
-\r
- /* Configure the system clock */\r
- SystemClock_Config();\r
-\r
- /* USER CODE BEGIN SysInit */\r
-\r
- /* USER CODE END SysInit */\r
-\r
- /* Initialize all configured peripherals */\r
- MX_GPIO_Init();\r
- /* USER CODE BEGIN 2 */\r
-\r
- /* USER CODE END 2 */\r
-\r
- /* Infinite loop */\r
- /* USER CODE BEGIN WHILE */\r
- while (1)\r
- {\r
- HAL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);\r
- HAL_Delay(100);\r
- /* USER CODE END WHILE */\r
-\r
- /* USER CODE BEGIN 3 */\r
- }\r
- /* USER CODE END 3 */\r
-}\r
-\r
-/**\r
- * @brief System Clock Configuration\r
- * @retval None\r
- */\r
-void SystemClock_Config(void)\r
-{\r
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};\r
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};\r
-\r
- /** Initializes the CPU, AHB and APB busses clocks \r
- */\r
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\r
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;\r
- RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;\r
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;\r
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\r
- RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;\r
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)\r
- {\r
- Error_Handler();\r
- }\r
- /** Initializes the CPU, AHB and APB busses clocks \r
- */\r
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK\r
- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;\r
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;\r
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;\r
-\r
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)\r
- {\r
- Error_Handler();\r
- }\r
-}\r
-\r
-/* USER CODE BEGIN 4 */\r
-\r
-/* USER CODE END 4 */\r
-\r
-/**\r
- * @brief This function is executed in case of error occurrence.\r
- * @retval None\r
- */\r
-void Error_Handler(void)\r
-{\r
- /* USER CODE BEGIN Error_Handler_Debug */\r
- /* User can add his own implementation to report the HAL error return state */\r
-\r
- /* USER CODE END Error_Handler_Debug */\r
-}\r
-\r
-#ifdef USE_FULL_ASSERT\r
-/**\r
- * @brief Reports the name of the source file and the source line number\r
- * where the assert_param error has occurred.\r
- * @param file: pointer to the source file name\r
- * @param line: assert_param error line source number\r
- * @retval None\r
- */\r
-void assert_failed(uint8_t *file, uint32_t line)\r
-{ \r
- /* USER CODE BEGIN 6 */\r
- /* User can add his own implementation to report the file name and line number,\r
- tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
- /* USER CODE END 6 */\r
-}\r
-#endif /* USE_FULL_ASSERT */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/* USER CODE BEGIN Header */\r
-/**\r
- ******************************************************************************\r
- * File Name : stm32f1xx_hal_msp.c\r
- * Description : This file provides code for the MSP Initialization \r
- * and de-Initialization codes.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-/* USER CODE END Header */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "main.h"\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* USER CODE BEGIN TD */\r
-\r
-/* USER CODE END TD */\r
-\r
-/* Private define ------------------------------------------------------------*/\r
-/* USER CODE BEGIN Define */\r
- \r
-/* USER CODE END Define */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* USER CODE BEGIN Macro */\r
-\r
-/* USER CODE END Macro */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/* USER CODE BEGIN PV */\r
-\r
-/* USER CODE END PV */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* USER CODE BEGIN PFP */\r
-\r
-/* USER CODE END PFP */\r
-\r
-/* External functions --------------------------------------------------------*/\r
-/* USER CODE BEGIN ExternalFunctions */\r
-\r
-/* USER CODE END ExternalFunctions */\r
-\r
-/* USER CODE BEGIN 0 */\r
-\r
-/* USER CODE END 0 */\r
-/**\r
- * Initializes the Global MSP.\r
- */\r
-void HAL_MspInit(void)\r
-{\r
- /* USER CODE BEGIN MspInit 0 */\r
-\r
- /* USER CODE END MspInit 0 */\r
-\r
- __HAL_RCC_AFIO_CLK_ENABLE();\r
- __HAL_RCC_PWR_CLK_ENABLE();\r
-\r
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_2);\r
-\r
- /* System interrupt init*/\r
-\r
- /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled \r
- */\r
- __HAL_AFIO_REMAP_SWJ_NOJTAG();\r
-\r
- /* USER CODE BEGIN MspInit 1 */\r
-\r
- /* USER CODE END MspInit 1 */\r
-}\r
-\r
-/* USER CODE BEGIN 1 */\r
-\r
-/* USER CODE END 1 */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/* USER CODE BEGIN Header */\r
-/**\r
- ******************************************************************************\r
- * @file stm32f1xx_it.c\r
- * @brief Interrupt Service Routines.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-/* USER CODE END Header */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "main.h"\r
-#include "stm32f1xx_it.h"\r
-/* Private includes ----------------------------------------------------------*/\r
-/* USER CODE BEGIN Includes */\r
-/* USER CODE END Includes */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* USER CODE BEGIN TD */\r
-\r
-/* USER CODE END TD */\r
-\r
-/* Private define ------------------------------------------------------------*/\r
-/* USER CODE BEGIN PD */\r
- \r
-/* USER CODE END PD */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* USER CODE BEGIN PM */\r
-\r
-/* USER CODE END PM */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-/* USER CODE BEGIN PV */\r
-\r
-/* USER CODE END PV */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* USER CODE BEGIN PFP */\r
-\r
-/* USER CODE END PFP */\r
-\r
-/* Private user code ---------------------------------------------------------*/\r
-/* USER CODE BEGIN 0 */\r
-\r
-/* USER CODE END 0 */\r
-\r
-/* External variables --------------------------------------------------------*/\r
-\r
-/* USER CODE BEGIN EV */\r
-\r
-/* USER CODE END EV */\r
-\r
-/******************************************************************************/\r
-/* Cortex-M3 Processor Interruption and Exception Handlers */ \r
-/******************************************************************************/\r
-/**\r
- * @brief This function handles Non maskable interrupt.\r
- */\r
-void NMI_Handler(void)\r
-{\r
- /* USER CODE BEGIN NonMaskableInt_IRQn 0 */\r
-\r
- /* USER CODE END NonMaskableInt_IRQn 0 */\r
- /* USER CODE BEGIN NonMaskableInt_IRQn 1 */\r
-\r
- /* USER CODE END NonMaskableInt_IRQn 1 */\r
-}\r
-\r
-/**\r
- * @brief This function handles Hard fault interrupt.\r
- */\r
-void HardFault_Handler(void)\r
-{\r
- /* USER CODE BEGIN HardFault_IRQn 0 */\r
-\r
- /* USER CODE END HardFault_IRQn 0 */\r
- while (1)\r
- {\r
- /* USER CODE BEGIN W1_HardFault_IRQn 0 */\r
- /* USER CODE END W1_HardFault_IRQn 0 */\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles Memory management fault.\r
- */\r
-void MemManage_Handler(void)\r
-{\r
- /* USER CODE BEGIN MemoryManagement_IRQn 0 */\r
-\r
- /* USER CODE END MemoryManagement_IRQn 0 */\r
- while (1)\r
- {\r
- /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */\r
- /* USER CODE END W1_MemoryManagement_IRQn 0 */\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles Prefetch fault, memory access fault.\r
- */\r
-void BusFault_Handler(void)\r
-{\r
- /* USER CODE BEGIN BusFault_IRQn 0 */\r
-\r
- /* USER CODE END BusFault_IRQn 0 */\r
- while (1)\r
- {\r
- /* USER CODE BEGIN W1_BusFault_IRQn 0 */\r
- /* USER CODE END W1_BusFault_IRQn 0 */\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles Undefined instruction or illegal state.\r
- */\r
-void UsageFault_Handler(void)\r
-{\r
- /* USER CODE BEGIN UsageFault_IRQn 0 */\r
-\r
- /* USER CODE END UsageFault_IRQn 0 */\r
- while (1)\r
- {\r
- /* USER CODE BEGIN W1_UsageFault_IRQn 0 */\r
- /* USER CODE END W1_UsageFault_IRQn 0 */\r
- }\r
-}\r
-\r
-/**\r
- * @brief This function handles System service call via SWI instruction.\r
- */\r
-void SVC_Handler(void)\r
-{\r
- /* USER CODE BEGIN SVCall_IRQn 0 */\r
-\r
- /* USER CODE END SVCall_IRQn 0 */\r
- /* USER CODE BEGIN SVCall_IRQn 1 */\r
-\r
- /* USER CODE END SVCall_IRQn 1 */\r
-}\r
-\r
-/**\r
- * @brief This function handles Debug monitor.\r
- */\r
-void DebugMon_Handler(void)\r
-{\r
- /* USER CODE BEGIN DebugMonitor_IRQn 0 */\r
-\r
- /* USER CODE END DebugMonitor_IRQn 0 */\r
- /* USER CODE BEGIN DebugMonitor_IRQn 1 */\r
-\r
- /* USER CODE END DebugMonitor_IRQn 1 */\r
-}\r
-\r
-/**\r
- * @brief This function handles Pendable request for system service.\r
- */\r
-void PendSV_Handler(void)\r
-{\r
- /* USER CODE BEGIN PendSV_IRQn 0 */\r
-\r
- /* USER CODE END PendSV_IRQn 0 */\r
- /* USER CODE BEGIN PendSV_IRQn 1 */\r
-\r
- /* USER CODE END PendSV_IRQn 1 */\r
-}\r
-\r
-/**\r
- * @brief This function handles System tick timer.\r
- */\r
-void SysTick_Handler(void)\r
-{\r
- /* USER CODE BEGIN SysTick_IRQn 0 */\r
-\r
- /* USER CODE END SysTick_IRQn 0 */\r
- HAL_IncTick();\r
- /* USER CODE BEGIN SysTick_IRQn 1 */\r
-\r
- /* USER CODE END SysTick_IRQn 1 */\r
-}\r
-\r
-/******************************************************************************/\r
-/* STM32F1xx Peripheral Interrupt Handlers */\r
-/* Add here the Interrupt Handlers for the used peripherals. */\r
-/* For the available peripheral interrupt handler names, */\r
-/* please refer to the startup file (startup_stm32f1xx.s). */\r
-/******************************************************************************/\r
-\r
-/**\r
- * @brief This function handles EXTI line0 interrupt.\r
- */\r
-void EXTI0_IRQHandler(void)\r
-{\r
- /* USER CODE BEGIN EXTI0_IRQn 0 */\r
-\r
- /* USER CODE END EXTI0_IRQn 0 */\r
- HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);\r
- /* USER CODE BEGIN EXTI0_IRQn 1 */\r
-\r
- /* USER CODE END EXTI0_IRQn 1 */\r
-}\r
-\r
-/* USER CODE BEGIN 1 */\r
-\r
-/* USER CODE END 1 */\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**
-*****************************************************************************
-**
-** File : syscalls.c
-**
-** Author : Auto-generated by STM32CubeIDE
-**
-** Abstract : STM32CubeIDE Minimal System calls file
-**
-** For more information about which c-functions
-** need which of these lowlevel functions
-** please consult the Newlib libc-manual
-**
-** Environment : STM32CubeIDE MCU
-**
-** Distribution: The file is distributed as is, without any warranty
-** of any kind.
-**
-*****************************************************************************
-**
-** <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-** 1. Redistributions of source code must retain the above copyright notice,
-** this list of conditions and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright notice,
-** this list of conditions and the following disclaimer in the documentation
-** and/or other materials provided with the distribution.
-** 3. Neither the name of STMicroelectronics nor the names of its contributors
-** may be used to endorse or promote products derived from this software
-** without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**
-*****************************************************************************
-*/
-
-/* Includes */
-#include <sys/stat.h>
-#include <stdlib.h>
-#include <errno.h>
-#include <stdio.h>
-#include <signal.h>
-#include <time.h>
-#include <sys/time.h>
-#include <sys/times.h>
-
-
-/* Variables */
-//#undef errno
-extern int errno;
-extern int __io_putchar(int ch) __attribute__((weak));
-extern int __io_getchar(void) __attribute__((weak));
-
-register char * stack_ptr asm("sp");
-
-char *__env[1] = { 0 };
-char **environ = __env;
-
-
-/* Functions */
-void initialise_monitor_handles()
-{
-}
-
-int _getpid(void)
-{
- return 1;
-}
-
-int _kill(int pid, int sig)
-{
- errno = EINVAL;
- return -1;
-}
-
-void _exit (int status)
-{
- _kill(status, -1);
- while (1) {} /* Make sure we hang here */
-}
-
-__attribute__((weak)) int _read(int file, char *ptr, int len)
-{
- int DataIdx;
-
- for (DataIdx = 0; DataIdx < len; DataIdx++)
- {
- *ptr++ = __io_getchar();
- }
-
-return len;
-}
-
-__attribute__((weak)) int _write(int file, char *ptr, int len)
-{
- int DataIdx;
-
- for (DataIdx = 0; DataIdx < len; DataIdx++)
- {
- __io_putchar(*ptr++);
- }
- return len;
-}
-
-int _close(int file)
-{
- return -1;
-}
-
-
-int _fstat(int file, struct stat *st)
-{
- st->st_mode = S_IFCHR;
- return 0;
-}
-
-int _isatty(int file)
-{
- return 1;
-}
-
-int _lseek(int file, int ptr, int dir)
-{
- return 0;
-}
-
-int _open(char *path, int flags, ...)
-{
- /* Pretend like we always fail */
- return -1;
-}
-
-int _wait(int *status)
-{
- errno = ECHILD;
- return -1;
-}
-
-int _unlink(char *name)
-{
- errno = ENOENT;
- return -1;
-}
-
-int _times(struct tms *buf)
-{
- return -1;
-}
-
-int _stat(char *file, struct stat *st)
-{
- st->st_mode = S_IFCHR;
- return 0;
-}
-
-int _link(char *old, char *new)
-{
- errno = EMLINK;
- return -1;
-}
-
-int _fork(void)
-{
- errno = EAGAIN;
- return -1;
-}
-
-int _execve(char *name, char **argv, char **env)
-{
- errno = ENOMEM;
- return -1;
-}
+++ /dev/null
-/**
-*****************************************************************************
-**
-** File : sysmem.c
-**
-** Author : Auto-generated by STM32CubeIDE
-**
-** Abstract : STM32CubeIDE Minimal System Memory calls file
-**
-** For more information about which c-functions
-** need which of these lowlevel functions
-** please consult the Newlib libc-manual
-**
-** Environment : STM32CubeIDE MCU
-**
-** Distribution: The file is distributed as is, without any warranty
-** of any kind.
-**
-*****************************************************************************
-**
-** <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-** 1. Redistributions of source code must retain the above copyright notice,
-** this list of conditions and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright notice,
-** this list of conditions and the following disclaimer in the documentation
-** and/or other materials provided with the distribution.
-** 3. Neither the name of STMicroelectronics nor the names of its contributors
-** may be used to endorse or promote products derived from this software
-** without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**
-*****************************************************************************
-*/
-
-/* Includes */
-#include <errno.h>
-#include <stdio.h>
-
-/* Variables */
-extern int errno;
-register char * stack_ptr asm("sp");
-
-/* Functions */
-
-/**
- _sbrk
- Increase program data space. Malloc and related functions depend on this
-**/
-caddr_t _sbrk(int incr)
-{
- extern char end asm("end");
- static char *heap_end;
- char *prev_heap_end;
-
- if (heap_end == 0)
- heap_end = &end;
-
- prev_heap_end = heap_end;
- if (heap_end + incr > stack_ptr)
- {
- errno = ENOMEM;
- return (caddr_t) -1;
- }
-
- heap_end += incr;
-
- return (caddr_t) prev_heap_end;
-}
-
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32f1xx.c\r
- * @author MCD Application Team\r
- * @version V4.2.0\r
- * @date 31-March-2017\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
- * \r
- * 1. This file provides two functions and one global variable to be called from \r
- * user application:\r
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
- * factors, AHB/APBx prescalers and Flash settings). \r
- * This function is called at startup just after reset and \r
- * before branch to main program. This call is made inside\r
- * the "startup_stm32f1xx_xx.s" file.\r
- *\r
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
- * by the user application to setup the SysTick \r
- * timer or configure other parameters.\r
- * \r
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
- * be called whenever the core clock is changed\r
- * during program execution.\r
- *\r
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.\r
- * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to\r
- * configure the system clock before to branch to main program.\r
- *\r
- * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on\r
- * the product used), refer to "HSE_VALUE". \r
- * When HSE is used as system clock source, directly or through PLL, and you\r
- * are using different crystal you have to adapt the HSE value to your own\r
- * configuration.\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f1xx_system\r
- * @{\r
- */ \r
- \r
-/** @addtogroup STM32F1xx_System_Private_Includes\r
- * @{\r
- */\r
-\r
-#include "stm32f1xx.h"\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F1xx_System_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F1xx_System_Private_Defines\r
- * @{\r
- */\r
-\r
-#if !defined (HSE_VALUE) \r
- #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.\r
- This value can be provided and adapted by the user application. */\r
-#endif /* HSE_VALUE */\r
-\r
-#if !defined (HSI_VALUE)\r
- #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.\r
- This value can be provided and adapted by the user application. */\r
-#endif /* HSI_VALUE */\r
-\r
-/*!< Uncomment the following line if you need to use external SRAM */ \r
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\r
-/* #define DATA_IN_ExtSRAM */\r
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */\r
-\r
-/*!< Uncomment the following line if you need to relocate your vector Table in\r
- Internal SRAM. */ \r
-/* #define VECT_TAB_SRAM */\r
-#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. \r
- This value must be a multiple of 0x200. */\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F1xx_System_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F1xx_System_Private_Variables\r
- * @{\r
- */\r
-\r
-/*******************************************************************************\r
-* Clock Definitions\r
-*******************************************************************************/\r
-#if defined(STM32F100xB) ||defined(STM32F100xE)\r
- uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */\r
-#else /*!< HSI Selected as System Clock source */\r
- uint32_t SystemCoreClock = 72000000U; /*!< System Clock Frequency (Core Clock) */\r
-#endif\r
-\r
-const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
-const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\r
-#ifdef DATA_IN_ExtSRAM\r
- static void SystemInit_ExtMemCtl(void); \r
-#endif /* DATA_IN_ExtSRAM */\r
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F1xx_System_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Setup the microcontroller system\r
- * Initialize the Embedded Flash Interface, the PLL and update the \r
- * SystemCoreClock variable.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit (void)\r
-{\r
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
- /* Set HSION bit */\r
- RCC->CR |= 0x00000001U;\r
-\r
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
-#if !defined(STM32F105xC) && !defined(STM32F107xC)\r
- RCC->CFGR &= 0xF8FF0000U;\r
-#else\r
- RCC->CFGR &= 0xF0FF0000U;\r
-#endif /* STM32F105xC */ \r
- \r
- /* Reset HSEON, CSSON and PLLON bits */\r
- RCC->CR &= 0xFEF6FFFFU;\r
-\r
- /* Reset HSEBYP bit */\r
- RCC->CR &= 0xFFFBFFFFU;\r
-\r
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
- RCC->CFGR &= 0xFF80FFFFU;\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- /* Reset PLL2ON and PLL3ON bits */\r
- RCC->CR &= 0xEBFFFFFFU;\r
-\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x00FF0000U;\r
-\r
- /* Reset CFGR2 register */\r
- RCC->CFGR2 = 0x00000000U;\r
-#elif defined(STM32F100xB) || defined(STM32F100xE)\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x009F0000U;\r
-\r
- /* Reset CFGR2 register */\r
- RCC->CFGR2 = 0x00000000U; \r
-#else\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x009F0000U;\r
-#endif /* STM32F105xC */\r
- \r
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\r
- #ifdef DATA_IN_ExtSRAM\r
- SystemInit_ExtMemCtl(); \r
- #endif /* DATA_IN_ExtSRAM */\r
-#endif \r
-\r
-#ifdef VECT_TAB_SRAM\r
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */\r
-#else\r
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */\r
-#endif \r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock variable according to Clock Register Values.\r
- * The SystemCoreClock variable contains the core clock (HCLK), it can\r
- * be used by the user application to setup the SysTick timer or configure\r
- * other parameters.\r
- * \r
- * @note Each time the core clock (HCLK) changes, this function must be called\r
- * to update SystemCoreClock variable value. Otherwise, any configuration\r
- * based on this variable will be incorrect. \r
- * \r
- * @note - The system frequency computed by this function is not the real \r
- * frequency in the chip. It is calculated based on the predefined \r
- * constant and the selected clock source:\r
- * \r
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
- * \r
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
- * \r
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
- * or HSI_VALUE(*) multiplied by the PLL factors.\r
- * \r
- * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value\r
- * 8 MHz) but the real value may vary depending on the variations\r
- * in voltage and temperature. \r
- * \r
- * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value\r
- * 8 MHz or 25 MHz, depending on the product used), user has to ensure\r
- * that HSE_VALUE is same as the real frequency of the crystal used.\r
- * Otherwise, this function may have wrong result.\r
- * \r
- * - The result of this function could be not correct when using fractional\r
- * value for HSE crystal.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate (void)\r
-{\r
- uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;\r
-\r
-#if defined(STM32F105xC) || defined(STM32F107xC)\r
- uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;\r
-#endif /* STM32F105xC */\r
-\r
-#if defined(STM32F100xB) || defined(STM32F100xE)\r
- uint32_t prediv1factor = 0U;\r
-#endif /* STM32F100xB or STM32F100xE */\r
- \r
- /* Get SYSCLK source -------------------------------------------------------*/\r
- tmp = RCC->CFGR & RCC_CFGR_SWS;\r
- \r
- switch (tmp)\r
- {\r
- case 0x00U: /* HSI used as system clock */\r
- SystemCoreClock = HSI_VALUE;\r
- break;\r
- case 0x04U: /* HSE used as system clock */\r
- SystemCoreClock = HSE_VALUE;\r
- break;\r
- case 0x08U: /* PLL used as system clock */\r
-\r
- /* Get PLL clock source and multiplication factor ----------------------*/\r
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;\r
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
- \r
-#if !defined(STM32F105xC) && !defined(STM32F107xC) \r
- pllmull = ( pllmull >> 18U) + 2U;\r
- \r
- if (pllsource == 0x00U)\r
- {\r
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
- SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;\r
- }\r
- else\r
- {\r
- #if defined(STM32F100xB) || defined(STM32F100xE)\r
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;\r
- /* HSE oscillator clock selected as PREDIV1 clock entry */\r
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; \r
- #else\r
- /* HSE selected as PLL clock entry */\r
- if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)\r
- {/* HSE oscillator clock divided by 2 */\r
- SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;\r
- }\r
- else\r
- {\r
- SystemCoreClock = HSE_VALUE * pllmull;\r
- }\r
- #endif\r
- }\r
-#else\r
- pllmull = pllmull >> 18U;\r
- \r
- if (pllmull != 0x0DU)\r
- {\r
- pllmull += 2U;\r
- }\r
- else\r
- { /* PLL multiplication factor = PLL input clock * 6.5 */\r
- pllmull = 13U / 2U; \r
- }\r
- \r
- if (pllsource == 0x00U)\r
- {\r
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
- SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;\r
- }\r
- else\r
- {/* PREDIV1 selected as PLL clock entry */\r
- \r
- /* Get PREDIV1 clock source and division factor */\r
- prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;\r
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;\r
- \r
- if (prediv1source == 0U)\r
- { \r
- /* HSE oscillator clock selected as PREDIV1 clock entry */\r
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; \r
- }\r
- else\r
- {/* PLL2 clock selected as PREDIV1 clock entry */\r
- \r
- /* Get PREDIV2 division factor and PLL2 multiplication factor */\r
- prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;\r
- pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; \r
- SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; \r
- }\r
- }\r
-#endif /* STM32F105xC */ \r
- break;\r
-\r
- default:\r
- SystemCoreClock = HSI_VALUE;\r
- break;\r
- }\r
- \r
- /* Compute HCLK clock frequency ----------------*/\r
- /* Get HCLK prescaler */\r
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];\r
- /* HCLK clock frequency */\r
- SystemCoreClock >>= tmp; \r
-}\r
-\r
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\r
-/**\r
- * @brief Setup the external memory controller. Called in startup_stm32f1xx.s \r
- * before jump to __main\r
- * @param None\r
- * @retval None\r
- */ \r
-#ifdef DATA_IN_ExtSRAM\r
-/**\r
- * @brief Setup the external memory controller. \r
- * Called in startup_stm32f1xx_xx.s/.c before jump to main.\r
- * This function configures the external SRAM mounted on STM3210E-EVAL\r
- * board (STM32 High density devices). This SRAM will be used as program\r
- * data memory (including heap and stack).\r
- * @param None\r
- * @retval None\r
- */ \r
-void SystemInit_ExtMemCtl(void) \r
-{\r
- __IO uint32_t tmpreg;\r
- /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
- required, then adjust the Register Addresses */\r
-\r
- /* Enable FSMC clock */\r
- RCC->AHBENR = 0x00000114U;\r
-\r
- /* Delay after an RCC peripheral clock enabling */\r
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\r
- \r
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */\r
- RCC->APB2ENR = 0x000001E0U;\r
- \r
- /* Delay after an RCC peripheral clock enabling */\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\r
-\r
- (void)(tmpreg);\r
- \r
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/\r
-/*---------------- SRAM Address lines configuration -------------------------*/\r
-/*---------------- NOE and NWE configuration --------------------------------*/ \r
-/*---------------- NE3 configuration ----------------------------------------*/\r
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/\r
- \r
- GPIOD->CRL = 0x44BB44BBU; \r
- GPIOD->CRH = 0xBBBBBBBBU;\r
-\r
- GPIOE->CRL = 0xB44444BBU; \r
- GPIOE->CRH = 0xBBBBBBBBU;\r
-\r
- GPIOF->CRL = 0x44BBBBBBU; \r
- GPIOF->CRH = 0xBBBB4444U;\r
-\r
- GPIOG->CRL = 0x44BBBBBBU; \r
- GPIOG->CRH = 0x444B4B44U;\r
- \r
-/*---------------- FSMC Configuration ---------------------------------------*/ \r
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/\r
- \r
- FSMC_Bank1->BTCR[4U] = 0x00001091U;\r
- FSMC_Bank1->BTCR[5U] = 0x00110212U;\r
-}\r
-#endif /* DATA_IN_ExtSRAM */\r
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- *************** (C) COPYRIGHT 2017 STMicroelectronics ************************\r
- * @file startup_stm32f103xe.s\r
- * @author MCD Application Team\r
- * @version V4.2.0\r
- * @date 31-March-2017\r
- * @brief STM32F103xE Devices vector table for Atollic toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address\r
- * - Configure the clock system \r
- * - Configure external SRAM mounted on STM3210E-EVAL board\r
- * to be used as data memory (optional, to be enabled by user)\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- ******************************************************************************\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section.\r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */\r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF1E0F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called.\r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler:\r
-\r
-/* Copy the data segment initializers from flash to SRAM */\r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
-\r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */\r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
-\r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-\r
-/* Call the clock system intitialization function.*/\r
- bl SystemInit\r
-/* Call static constructors */\r
- bl __libc_init_array\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr\r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an\r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None\r
- * @retval : None\r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/\r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
-\r
-\r
-g_pfnVectors:\r
-\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTC_Alarm_IRQHandler\r
- .word USBWakeUp_IRQHandler\r
- .word TIM8_BRK_IRQHandler\r
- .word TIM8_UP_IRQHandler\r
- .word TIM8_TRG_COM_IRQHandler\r
- .word TIM8_CC_IRQHandler\r
- .word ADC3_IRQHandler\r
- .word FSMC_IRQHandler\r
- .word SDIO_IRQHandler\r
- .word TIM5_IRQHandler\r
- .word SPI3_IRQHandler\r
- .word UART4_IRQHandler\r
- .word UART5_IRQHandler\r
- .word TIM6_IRQHandler\r
- .word TIM7_IRQHandler\r
- .word DMA2_Channel1_IRQHandler\r
- .word DMA2_Channel2_IRQHandler\r
- .word DMA2_Channel3_IRQHandler\r
- .word DMA2_Channel4_5_IRQHandler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x1E0. This is for boot in RAM mode for\r
- STM32F10x High Density devices. */\r
-\r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler.\r
-* As they are weak aliases, any function with the same name will override\r
-* this definition.\r
-*\r
-*******************************************************************************/\r
-\r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTC_Alarm_IRQHandler\r
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_BRK_IRQHandler\r
- .thumb_set TIM8_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_UP_IRQHandler\r
- .thumb_set TIM8_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_TRG_COM_IRQHandler\r
- .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_CC_IRQHandler\r
- .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
-\r
- .weak ADC3_IRQHandler\r
- .thumb_set ADC3_IRQHandler,Default_Handler\r
-\r
- .weak FSMC_IRQHandler\r
- .thumb_set FSMC_IRQHandler,Default_Handler\r
-\r
- .weak SDIO_IRQHandler\r
- .thumb_set SDIO_IRQHandler,Default_Handler\r
-\r
- .weak TIM5_IRQHandler\r
- .thumb_set TIM5_IRQHandler,Default_Handler\r
-\r
- .weak SPI3_IRQHandler\r
- .thumb_set SPI3_IRQHandler,Default_Handler\r
-\r
- .weak UART4_IRQHandler\r
- .thumb_set UART4_IRQHandler,Default_Handler\r
-\r
- .weak UART5_IRQHandler\r
- .thumb_set UART5_IRQHandler,Default_Handler\r
-\r
- .weak TIM6_IRQHandler\r
- .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
- .weak TIM7_IRQHandler\r
- .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel1_IRQHandler\r
- .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel2_IRQHandler\r
- .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel3_IRQHandler\r
- .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel4_5_IRQHandler\r
- .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
func main() {
var port string
var baud int
- flag.StringVar(&port, "p", "/dev/cu.SLAB_USBtoUART", "serial port")
+ //flag.StringVar(&port, "p", "/dev/cu.SLAB_USBtoUART", "serial port")
+ flag.StringVar(&port, "p", "/dev/cu.wchusbserial1460", "serial port")
flag.IntVar(&baud, "b", 115200, "baud rate default 115200")
flag.Parse()
log.Printf("port: %s\n", port)
+ //c := &serial.Config{Name: port, Baud: baud}
c := &serial.Config{Name: port, Baud: baud}
s, err := serial.OpenPort(c)
if err != nil {
log.Fatal(err)
}
- n, err := s.Write([]byte("test"))
- if err != nil {
- log.Fatal(err)
- }
-
for {
buf := make([]byte, 4096)
- n, err = s.Read(buf)
+ n, err := s.Read(buf)
if err != nil {
log.Fatal(err)
}
