{ 0x10DE, 0x0110, "nVidia GeForce2 MX [NV11]" },
{ 0x10EC, 0x8029, "Realtek RTL8029" },
{ 0x10EC, 0x8129, "Realtek RTL8129" },
+ { 0x10EC, 0x8136, "Realtek RTL8101E Family" },
{ 0x10EC, 0x8139, "Realtek RTL8139" },
{ 0x10EC, 0x8167, "Realtek RTL8169/8110 Family Gigabit NIC" },
{ 0x10EC, 0x8169, "Realtek RTL8169" },
printf("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
rl_outw(port, 0x82, 0x01);
break;
+ case RL_TCR_HWVER_RTL8105E:
+ rep->re_model = "RTL8105E";
+ break;
default:
rep->re_model = "Unknown";
rep->re_mac = t;
rl_outw(port, RL_9346CR, RL_9346CR_EEM_CONFIG); /* Unlock */
- t = rl_inw(port, RL_CPLUSCMD);
- if ((rep->re_mac == RL_TCR_HWVER_RTL8169S) ||
- (rep->re_mac == RL_TCR_HWVER_RTL8110S)) {
+ switch (rep->re_mac) {
+ case RL_TCR_HWVER_RTL8169S:
+ case RL_TCR_HWVER_RTL8110S:
printf("Set MAC Reg C+CR Offset 0xE0. "
"Bit-3 and bit-14 MUST be 1\n");
+ t = rl_inw(port, RL_CPLUSCMD);
rl_outw(port, RL_CPLUSCMD, t | RL_CPLUS_MULRW | (1 << 14));
- } else
+ break;
+ case RL_TCR_HWVER_RTL8169:
+ case RL_TCR_HWVER_RTL8169SB:
+ case RL_TCR_HWVER_RTL8110SCd:
+ t = rl_inw(port, RL_CPLUSCMD);
rl_outw(port, RL_CPLUSCMD, t | RL_CPLUS_MULRW);
+ break;
+ }
rl_outw(port, RL_INTRMITIGATE, 0x00);
#define RL_TCR_HWVER_RTL8110S 0x04000000 /* RTL8110S */
#define RL_TCR_HWVER_RTL8169SB 0x10000000 /* RTL8169sb/8110sb */
#define RL_TCR_HWVER_RTL8110SCd 0x18000000 /* RTL8169sc/8110sc */
+#define RL_TCR_HWVER_RTL8105E 0x40800000 /* RTL8105E */
#define RL_TCR_RES1 0x00380000 /* Reserved */
#define RL_TCR_LBK_M 0x00060000 /* Loopback Test */
#define RL_TCR_LBK_NORMAL 0x00000000 /* Normal */