const char *pci_get_info(unsigned int classcode, unsigned int progif);
-int pci_read_config_byte(int reg) {
- outl(PCI_CONFIG_CMD(reg), PCI_ADDR);
- return inb(PCI_DATA + (PCI_GET_CMD_REG(reg) & 3));
+#if PCI_RW_ALIGN_MODE
+int pci_read_config_byte(int cmd) {
+ outl(PCI_CONFIG_CMD(cmd), PCI_ADDR);
+ return inb(PCI_DATA + (PCI_GET_CMD_REG(cmd) & 3));
}
-int pci_read_config_word(int reg) {
- outl(PCI_CONFIG_CMD(reg), PCI_ADDR);
- return inw(PCI_DATA + (PCI_GET_CMD_REG(reg) & 2));
+int pci_read_config_word(int cmd) {
+ outl(PCI_CONFIG_CMD(cmd), PCI_ADDR);
+ return inw(PCI_DATA + (PCI_GET_CMD_REG(cmd) & 2));
}
-int pci_read_config_long(int reg) {
- outl(PCI_CONFIG_CMD(reg), PCI_ADDR);
+int pci_read_config_long(int cmd) {
+ outl(PCI_CONFIG_CMD(cmd), PCI_ADDR);
return inl(PCI_DATA);
}
-void pci_write_config_byte(int value, int reg) {
- outl(PCI_CONFIG_CMD(reg), PCI_ADDR);
- outb(value & 0xFF, PCI_DATA + (reg & 3));
+void pci_write_config_byte(int value, int cmd) {
+ outl(PCI_CONFIG_CMD(cmd), PCI_ADDR);
+ outb(value & 0xFF, PCI_DATA + (cmd & 3));
}
-void pci_write_config_word(int value, int reg) {
- outl(PCI_CONFIG_CMD(reg), PCI_ADDR);
- outw(value & 0xFFFF, PCI_DATA + (reg & 2));
+void pci_write_config_word(int value, int cmd) {
+ outl(PCI_CONFIG_CMD(cmd), PCI_ADDR);
+ outw(value & 0xFFFF, PCI_DATA + (cmd & 2));
}
-void pci_write_config_long(int value, int reg) {
- outl(PCI_CONFIG_CMD(reg), PCI_ADDR);
+void pci_write_config_long(int value, int cmd) {
+ outl(PCI_CONFIG_CMD(cmd), PCI_ADDR);
outl(value, PCI_DATA);
}
+#else
+int pci_read_config_byte(int cmd) {
+ outl(cmd, PCI_ADDR);
+ return inb(PCI_DATA);
+}
+
+int pci_read_config_word(int cmd) {
+ outl(cmd, PCI_ADDR);
+ return inw(PCI_DATA);
+}
+
+int pci_read_config_long(int cmd) {
+ outl(cmd, PCI_ADDR);
+ return inl(PCI_DATA);
+}
+
+void pci_write_config_byte(int value, int cmd) {
+ outl(cmd, PCI_ADDR);
+ outb(value & 0xFF, PCI_DATA);
+}
+
+void pci_write_config_word(int value, int cmd) {
+ outl(cmd, PCI_ADDR);
+ outw(value & 0xFFFF, PCI_DATA);
+}
+
+void pci_write_config_long(int value, int cmd) {
+ outl(cmd, PCI_ADDR);
+ outl(value, PCI_DATA);
+}
+#endif
void scan_pci_bus(int bus) {
u8 dev, devfn;
#define PCI_ADDR 0xCF8 // CONFIG_ADDRESS
#define PCI_DATA 0xCFC // CONFIG_DATA
+// PCI Command
+// 这个PCI_CMD是写入PCI_ADDR的,通过bus,dev,fn,reg可以定位到某个PCI总线(可以有多条PCI总线)上的某个设备的某个功能的某个寄存器
+#define PCI_CMD(bus, dev, fn, reg) (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | reg)
+
+#if PCI_RW_ALIGN_MODE
+#define PCI_CONFIG_CMD(cmd) (cmd & ~3)
+#define PCI_GET_CMD_REG(cmd) (cmd & 0xFF)
+#endif
+
// PCI Device
// All PCI compliant devices must support the Vendor ID, Device ID, Command and Status, Revision ID, Class Code and
// Header Type fields.Implementation of the other registers is optional, depending upon the devices functionality.
#define PCI_MINGNT 0x3E
#define PCI_MAXLAT 0x3F
-// PCI Command Register
-#define PCI_CMD(bus, dev, devfn, reg) (0x80000000 | (bus << 16) | (dev << 11) | (devfn << 8) | reg)
-
-#define PCI_CONFIG_CMD(cmd) (cmd & ~3)
-#define PCI_GET_CMD_REG(cmd) (cmd & 0xFF)
-
/* PCI IDS */
// Display
#define PCI_BASE_CLASS_DISPLAY 0x03