...

diff --git a/learn/stm32/F103/src/main.c b/learn/stm32/F103/src/main.c
index 20439a69372d1b12564e4259faadbf64be57c25d..79eb6db27c882efbb97ae4b65b25ac14f00b03f9 100644 (file)
--- a/learn/stm32/F103/src/main.c
+++ b/learn/stm32/F103/src/main.c
@@ -12,27 +12,45 @@
 #include "gpio.h"
 #include "rcc.h"
 #include "systick.h"
-
-unsigned int pin = 9;
+#include "wdg.h"
+#include <stdio.h>
+unsigned int pin = 8;
 
 
 void SystemInit() {
        InitSystemClock();
 
+       // 不知道为啥低于IWDG_PRESCALER_64不能正常复位
+       IWDG_Init(IWDG_PRESCALER_64, 625*2);
+       EnableLSI();
+
+
+#define DBGMCU_CR (*((uint32_t*)0xE0042004))
+       DBGMCU_CR &= ~(1 << 8);
+
        InitSysTick();
 
        // 使能时钟
        RCCEnableGPIOBClock();
 
+
        GPIOSetOutput(GPIOB, pin, GPIO_OUTPUT_MODE_GP_PP, GPIO_OUTPUT_SPEED_50MHZ);
+       GPIOWrite(GPIOB, pin, HIGH);
 }
 
 void delay() {
-       Delay(200);
+       //Delay(100);
+       NoneIntDelay(100);
 }
 
 int main() {
+       delay();
+       GPIOWrite(GPIOB, pin, LOW);
+
+       uint32_t n = 0;
        while(1) {
+               IWDG_Feed();
+               continue;
                GPIOWrite(GPIOB, pin, HIGH);
                delay();
                GPIOWrite(GPIOB, pin, LOW);

diff --git a/learn/stm32/F103/src/rcc.c b/learn/stm32/F103/src/rcc.c
index eb48dd7e533d1ea9cedc4597710c0ee32fe50031..f7c38017ce7bc4940471a0e67d7606f552162420 100644 (file)
--- a/learn/stm32/F103/src/rcc.c
+++ b/learn/stm32/F103/src/rcc.c
@@ -94,7 +94,13 @@
 #define RCC_CFGR_MCO_HSE               0x06000000
 #define RCC_CFGR_MCO_PLL_HALF  0x07000000
 
+
+
+#define RCC_CSR_LSION                  0x00000001
+#define RCC_CSR_LSIRDY                 0x00000002
+
 #define HSE_STARTUP_TIMEOUT    0x500
+#define LSI_STARTUP_TIMEOUT    0x500
 
 void InitFlashAcr();
 
@@ -107,7 +113,6 @@ void InitSystemClock() {
        // 启动HSI
        RCC->CR |= RCC_CR_HSION;
 
-
        // SW： System Close Switch 重置为 HSI
        RCC->CFGR &= ~RCC_CFGR_SW_MASK;
        RCC->CFGR |= RCC_CFGR_SW_HSI;
@@ -171,6 +176,20 @@ void InitSystemClock() {
 }
 
 
+void EnableLSI() {
+       RCC->CSR |= RCC_CSR_LSION;
+
+       volatile uint32_t StartupCnt = 0;
+       volatile uint32_t Status = 0;
+
+       do {
+               Status = RCC->CSR & RCC_CSR_LSIRDY;
+               StartupCnt++;
+       } while(Status == 0 && StartupCnt < LSI_STARTUP_TIMEOUT);
+
+
+}
+
 
 void SetSystemClock72MHz() {
        RCC->CR |= RCC_CR_HSEON;

diff --git a/learn/stm32/F103/src/rcc.h b/learn/stm32/F103/src/rcc.h
index 96a0445852f054e8fca9d97c89210355d4f1adb0..1b98b2db479f07ee15391a3d642e7fe8f88e5c85 100644 (file)
--- a/learn/stm32/F103/src/rcc.h
+++ b/learn/stm32/F103/src/rcc.h
@@ -42,5 +42,6 @@ void __RCCEnableAPB2(uint32_t en);
 #define RCCEnableGPIOEClock() __RCCEnableAPB2(RCC_APB2ENR_IOPEEN)
 
 void InitSystemClock();
+void EnableLSI();
 
 #endif /* RCC_H_ */

diff --git a/learn/stm32/F103/src/wdg.c b/learn/stm32/F103/src/wdg.c
new file mode 100644 (file)
index 0000000..3e7692a
--- /dev/null
+++ b/learn/stm32/F103/src/wdg.c
@@ -0,0 +1,21 @@
+/*
+ * iwdg.c
+ *
+ *  Created on: May 29, 2019
+ *      Author: ace
+ */
+
+#include "wdg.h"
+
+void IWDG_Init(uint32_t prer, uint32_t rlr) {
+       IWDG->KR = IWDG_KEY_WRITE_ENABLE;
+       IWDG->PR = prer;
+       IWDG->RLR= rlr;
+       IWDG->KR = IWDG_KEY_RELOAD;
+       IWDG->KR = IWDG_KEY_ENABLE;
+}
+
+
+void IWDG_Feed() {
+       IWDG->KR = IWDG_KEY_RELOAD;
+}

diff --git a/learn/stm32/F103/src/wdg.h b/learn/stm32/F103/src/wdg.h
new file mode 100644 (file)
index 0000000..3752f07
--- /dev/null
+++ b/learn/stm32/F103/src/wdg.h
@@ -0,0 +1,53 @@
+/*
+ * iwdg.h
+ *
+ *  Created on: May 29, 2019
+ *      Author: ace
+ */
+
+#ifndef WDG_H_
+#define WDG_H_
+
+#include "stm32f103.h"
+
+
+#define IWDG_BASE (APB1PERIPH_BASE+0x3000)
+
+
+//  超时时间
+
+// Tout = ((2^(2+prer))xrlr)/40)
+typedef struct {
+       // 向KR里
+       // 写入0x5555取消PR、RLR的写保护
+       // 写入0xAAAA来喂狗
+       // 写入0xCCCC来启动看门狗
+       volatile uint32_t KR:16;        // 键寄存器
+       volatile uint32_t __KR:16;
+       volatile uint32_t PR:3; // 预分频寄存器
+       volatile uint32_t __PR:29;
+       volatile uint32_t RLR:12;       // 重装载寄存器
+       volatile uint32_t __RLR;
+       volatile uint32_t SR;   // 状态寄存器
+} IWDG_t;
+
+#define IWDG ((IWDG_t *)IWDG_BASE)
+
+#define IWDG_KEY_WRITE_DISABLE 0x0000
+#define IWDG_KEY_WRITE_ENABLE  0x5555
+#define IWDG_KEY_RELOAD                        0xAAAA
+#define IWDG_KEY_ENABLE                        0xCCCC
+
+
+#define IWDG_PRESCALER_4               0x00000000
+#define IWDG_PRESCALER_8               0x00000001
+#define IWDG_PRESCALER_16              0x00000002
+#define IWDG_PRESCALER_32              0x00000003
+#define IWDG_PRESCALER_64              0x00000004
+#define IWDG_PRESCALER_128             0x00000005
+#define IWDG_PRESCALER_256             0x00000006
+
+void IWDG_Init(uint32_t prer, uint32_t rlr);
+void IWDG_Feed();
+
+#endif /* WDG_H_ */