void bsp_reset_init(void);
void bsp_reset(void);
void bsp_poweroff(void);
+void bsp_disable_watchdog(void);
#endif /* _BSP_RESET_H_ */
/* map memory for reset control */
bsp_reset_init();
+
+ /* disable watchdog */
+ bsp_disable_watchdog();
}
#include "arch_proto.h"
#include "bsp_reset.h"
+#include "omap_timer_registers.h"
#include "omap_rtc.h"
#define AM335X_CM_BASE 0x44E00000
while (1);
}
}
+
+void bsp_disable_watchdog(void)
+{
+ if(BOARD_IS_BB(machine.board_id)) {
+ mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0xAAAA);
+ while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
+ mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0x5555);
+ while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
+ }
+}
+
#define AM335X_TIMER_TSICR 0x054 /* Control posted mode and functional SW reset */
#define AM335X_TIMER_TCAR2 0x058 /* Second captured value of counter register */
-
+#define AM335X_WDT_BASE 0x44E35000 /* watchdog timer */
+#define AM335X_WDT_WWPS 0x34 /* command posted status */
+#define AM335X_WDT_WSPR 0x48 /* activate/deactivate sequence */
/* Interrupt status register fields */
#define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */