case DAC1_CHAN: page = DAC_MEM_PAGE;
frame_count_reg = DAC1_BUFFER_SIZE;
dma_add_reg = DAC1_PCI_ADDRESS;
- break;;
+ break;
case DAC2_CHAN: page = DAC_MEM_PAGE;
frame_count_reg = DAC2_BUFFER_SIZE;
dma_add_reg = DAC2_PCI_ADDRESS;
- break;;
+ break;
default: return EIO;
}
pci_outb(reg(MEM_PAGE), page);
/* return status of interrupt bit of specified channel*/
switch (sub_dev) {
- case DAC1_CHAN: bit = DAC1;break;
- case DAC2_CHAN: bit = DAC2;break;
- case ADC1_CHAN: bit = ADC;break;
+ case DAC1_CHAN: bit = DAC1; break;
+ case DAC2_CHAN: bit = DAC2; break;
+ case ADC1_CHAN: bit = ADC; break;
+ default: return EINVAL;
}
int_status = pci_inl(reg(INTERRUPT_STATUS)) & bit;
case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
- default: EINVAL;
+ default: return EINVAL;
}
/* clear and reenable an interrupt */
case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
- default: EINVAL;
+ default: return EINVAL;
}
/* clear the interrupt */
ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
case DAC1_CHAN: bit = DAC1;break;
case DAC2_CHAN: bit = DAC2;break;
case ADC1_CHAN: bit = ADC;break;
+ default: return EINVAL;
}
int_status = pci_inl(reg(INTERRUPT_STATUS)) & bit;
case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
- default: EINVAL;
+ default: return EINVAL;
}
/* clear and reenable an interrupt */
case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
- default: EINVAL;
+ default: return EINVAL;
}
/* clear the interrupt */
ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));