From 3040c16ce6e01a643ccae61000328454352d9866 Mon Sep 17 00:00:00 2001
From: acevest <zhaoyanbai@126.com>
Date: Sun, 22 Sep 2024 10:03:44 +0800
Subject: [PATCH] =?utf8?q?=E4=BF=AE=E5=A4=8D=E5=BD=93IDE=20Controller?=
 =?utf8?q?=E7=9A=84BAR=E5=AF=84=E5=AD=98=E5=99=A8=E7=9A=84=E5=80=BC?=
 =?utf8?q?=E4=B8=8D=E4=B8=BA0=E6=97=B6IDE=E5=91=BD=E4=BB=A4=E5=92=8C?=
 =?utf8?q?=E6=8E=A7=E5=88=B6=E5=AF=84=E5=AD=98=E5=99=A8=E5=9C=B0=E5=9D=80?=
 =?utf8?q?=E8=AE=A1=E7=AE=97=E9=94=99=E8=AF=AF=E7=9A=84=E9=97=AE=E9=A2=98?=
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

---
 drivers/ide.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/ide.c b/drivers/ide.c
index 77308c6..1bd2658 100644
--- a/drivers/ide.c
+++ b/drivers/ide.c
@@ -132,11 +132,16 @@ void ide_pci_init(pci_device_t *pci) {
 
     for (int i = 0; i < 6; i++) {
         printd("ide pci BAR%u value 0x%08X\n", i, pci->bars[i]);
+        if (pci->bars[i] != 0) {
+            assert((pci->bars[i] & 0x1) == 0x1);
+        }
     }
 
     // BAR4开始有16个端口，有2组，每组8个，分别控制Primary和Secondary通道的DMA
     // BAR5: SATA AHCI Base Address
-    uint32_t iobase = pci->bars[4];
+    // 虽然iobase是uint32_t，但在PC机上最多有65536个端口，也就是有效位数为16bit
+    // 所以这里用0xFFFE或0xFFFFFFFE其实都可以
+    uint32_t iobase = pci->bars[4] & 0xFFFFFFFE;  // 最低为0是内存地址为1是端口地址
 
     for (int i = 0; i < NR_IDE_CONTROLLER; i++) {
         INIT_MUTEX(&ide_pci_controller[i].request_mutex);
@@ -152,10 +157,6 @@ void ide_pci_init(pci_device_t *pci) {
 
         iobase += i * 8;  // secondary channel 需要加8
         printd("ide pci Base IO Address Register %08x\n", iobase);
-        // 虽然iobase是uint32_t，但在PC机上最多有65536个端口，也就是有效位数为16bit
-        // 所以这里用0xFFFC或0xFFFFFFFC其实都可以
-
-        iobase &= 0xFFFC;  // 最低为0是内存地址为1是端口地址
         ide_pci_controller[i].bus_iobase = iobase;
         ide_pci_controller[i].bus_cmd = iobase + PCI_IDE_CMD;
         ide_pci_controller[i].bus_status = iobase + PCI_IDE_STATUS;
@@ -165,11 +166,11 @@ void ide_pci_init(pci_device_t *pci) {
         ide_pci_controller[i].pci = pci;
     }
 
-    IDE_CHL0_CMD_BASE = pci->bars[0] ? pci->bars[0] : IDE_CHL0_CMD_BASE;
-    IDE_CHL0_CTL_BASE = pci->bars[1] ? pci->bars[1] : IDE_CHL0_CTL_BASE;
+    IDE_CHL0_CMD_BASE = pci->bars[0] ? (pci->bars[0] & 0xFFFFFFFE) : IDE_CHL0_CMD_BASE;
+    IDE_CHL0_CTL_BASE = pci->bars[1] ? (pci->bars[1] & 0xFFFFFFFE) : IDE_CHL0_CTL_BASE;
 
-    IDE_CHL1_CMD_BASE = pci->bars[2] ? pci->bars[2] : IDE_CHL1_CMD_BASE;
-    IDE_CHL1_CTL_BASE = pci->bars[3] ? pci->bars[3] : IDE_CHL1_CTL_BASE;
+    IDE_CHL1_CMD_BASE = pci->bars[2] ? (pci->bars[2] & 0xFFFFFFFE) : IDE_CHL1_CMD_BASE;
+    IDE_CHL1_CTL_BASE = pci->bars[3] ? (pci->bars[3] & 0xFFFFFFFE) : IDE_CHL1_CTL_BASE;
 
     printd("ide channel 0: cmd %04x ctl %04x\n", IDE_CHL0_CMD_BASE, IDE_CHL0_CTL_BASE);
     printd("ide channel 1: cmd %04x ctl %04x\n", IDE_CHL1_CMD_BASE, IDE_CHL1_CTL_BASE);
@@ -260,9 +261,7 @@ void ide_init() {
     memset(ide_pci_controller, 0, sizeof(ide_pci_controller[0]) * NR_IDE_CONTROLLER);
 
     // 读PCI里 IDE相关寄存器的配置
-    // init_pci_controller(0x0106);
     init_pci_controller(0x0101);
-    // init_pci_controller(0x7010);
 
     request_irq(0x0E, ide_irq_handler, "hard", "IDE");
 
-- 
2.44.0